TWI579699B - Server system - Google Patents

Description

Server system

A server, especially a server system.

The ability to store and process data is an important part of the server. As the instruction cycle of the central processing unit becomes faster and faster, and the storage capacity of the storage device is also larger, such as a Hard Disk Driver (HDD), the overall performance of the server is affected by the data transmission speed of the hard disk. influences.

In order to avoid the impact of the overall performance of the server, it is bound to increase electronic components (such as complex programmable logic components, CPLD) and related circuit design to meet the speed of data transmission on the server as a whole. Due to the need to add electronic components, this will reduce the space used by the server board and increase the cost of using electronic components. Therefore, there is still room for improvement in the overall circuit design of the server.

The main object of the present invention is to provide a server system to solve the problems of high use and high cost of electronic components existing in the prior art.

To solve the above problem, an embodiment of the present invention provides a server system, including: a motherboard and a backplane. The motherboard includes: a central processing unit and an expansion unit. The central processing unit generates a Peripheral Component Interconnect Express (PCIE) format data signal, a first control signal having a PCIE format, and a second with an Inter-Integrated Circuit (I2C) bus format Control signal. The expansion unit is coupled to the central processing unit and transmits a PCIE format data signal, a first control signal having a PCIE format, and a second control signal having an I2C bus format. The backboard is coupled to the motherboard, and the backboard includes: a first connector, an indicator, and a control unit. The first connector is coupled to the expansion unit. The control unit is coupled to the first connector, the indicator light, and the hard disk, and receives the PCIE format data signal, the first control signal with the PCIE format, and the second control signal with the I2C bus format through the first connector, and the PCIE format The data signal is output to the hard disk, and the first control signal having the PCIE format and the second control signal having the I2C bus format are decoded to respectively control the indicator light and the hard disk.

The server system further includes: a clock signal generator and a south bridge chip, wherein the clock signal generator generates a clock signal and transmits the clock signal to the central processing unit and the south bridge chip.

The motherboard further includes a first slot coupled to the central processing unit, the expansion unit further includes a second connector and a second slot, wherein the second connector is coupled to the first slot, and the second slot is coupled First connector.

Wherein, the first slot and the second connector have slots and connectors of a PCIE transport protocol.

The second slot and the first connector are slots and connectors having a Mini Serial Attached SCSI (Mini SAS) transmission protocol.

The expansion unit is an expansion card with a non-volatile memory storage standard (Non-Volatile Memory Express, NVMe).

The first control signal in the PCIE format is an indicator light control signal in the PCIE format, and the second control signal in the I2C bus format is a hot plug control signal in the I2C bus format.

Wherein, the backboard includes a power connector, and the power connector generates a voltage to supply power to the hard disk.

Among them, the control unit is a PIC microcontroller.

The display state of the indicator light corresponds to the working state of the hard disk.

According to the technical solution of the present invention, the central processing unit is connected to the control unit through the expansion unit and the first connector (ie, the motherboard is connected to the backplane), so that the control unit can store the data signal generated by the central processing unit in the hard The disc and the first control signal and the second control signal generated by the central processing unit are parsed to control the indicator light and the hard disk through the parsed first control signal and the second control signal. In this way, the number of electronic components used can be effectively reduced, the component use cost can be reduced, and the working efficiency of the server system can also be improved.

The main idea of the present invention is to connect the central processing unit to the control unit (that is, to connect the motherboard to the backplane) through the expansion unit and the first connector, so that the control unit can store the data signals generated by the central processing unit in the control unit. The hard disk is configured to analyze the first control signal and the second control signal generated by the central processing unit to control the indicator light and the hard disk through the first control signal and the second control signal. In this way, the number of electronic components used can be effectively reduced, the component use cost can be reduced, and the working efficiency of the server system can also be improved.

The present invention will be further described in detail below with reference to the drawings and specific embodiments.

In accordance with an embodiment of the present invention, a server system is provided.

"FIG. 1" is a block diagram showing the structure of a server system according to an embodiment of the present invention. The server system 100 includes a motherboard 110 and a backplane 150. The motherboard 110 includes a central processing unit 120 and an expansion unit 130.

The central processing unit 120 generates a Peripheral Component Interconnect Express (PCIE) format data signal, a first control signal with a PCIE format, and an Inter-Integrated Circuit (I2C) bus format. The second control signal. In this embodiment, the PCIE format is an example of PCIE version 3.0, and the rated data transmission rate is 8 Gb/s, and the PCIE uses a serial method to transmit data, so that each device connected to the PCIE does not need to be shared. Bandwidth, this will effectively increase the rate of data transmission.

The expansion unit 130 is coupled to the central processing unit 120 and transmits a PCIE format data signal, a first control signal having a PCIE format, and a second control signal having an I2C bus format. In this embodiment, the expansion unit 130 is, for example, an expansion card having a Non-Volatile Memory Express (NVMe), so that the server system 100 can add more expansion devices to the central processor. The signal generated by 110 is transmitted to the expansion device on the back end, thereby increasing the performance of the server system 100.

The backboard 150 is coupled to the motherboard 110, and the backplane 150 includes a first connector 160, an indicator light 170, and a control unit 180. The first connector 160 is coupled to the expansion unit 130.

In the embodiment, the motherboard 110 further includes a first slot 111 , and the first slot 111 is coupled to the central processing unit 120 . The expansion unit 130 further includes a second connector 131 and a second slot 132. The second connector 131 is coupled to the first slot 111 , that is, the expansion unit 130 is inserted into the first slot 110 through the second connector 131 . The second slot 132 is coupled to the first connector 160 , that is, the backplane 150 is inserted into the second slot 132 through the first connector 160 .

Further, the first slot 111 and the second connector 131 are, for example, slots and connectors having a PCIE transmission protocol. Further, the first slot 111 and the second connector 131 adopt, for example, the 3.0 version of the PCIE of the 4 transmission channels, and the data transmission rate of each transmission channel is 8 Gb/s, so the first slot 111 and the second connection The data transfer rate of the device 131 can be, for example, 32 Gb/s to increase the operating efficiency of the server system 100. In addition, the second slot 132 and the first connector 160 are, for example, slots and connectors having a Mini Serial Attached SCSI (Mini SAS) transmission protocol.

The control unit 180 is coupled to the first connector 160, the indicator light 170, and the hard disk 190, and receives the PCIE format data signal, the first control signal in the PCIE format, and the second control signal in the I2C bus format through the first connector 160. And outputting the PCIE format data signal to the hard disk 190, and decoding the first control signal having the PCIE format and the second control signal having the I2C bus format to respectively control the indicator light 170 and the hard disk 190.

For example, when the control unit 180 receives the PCIE format data signal, the PCIE format data signal is output to the hard disk 190 to store the data in the hard disk 190. In addition, when the control unit 180 receives the first control signal having the PCIE format and the second control signal having the I2C bus format, the first control signal having the PCIE format and the second control signal having the I2C bus format are respectively performed. The analysis is performed to control the display state of the indicator light 170 through the first control signal after the analysis, and to control the startup, switching, and hot plugging of the hard disk 190 through the second control signal after the analysis.

Further, the first control signal having the PCIE format is, for example, a LED control signal of the PCIE format, that is, the first control signal is used to control the display state of the indicator light 170. In addition, the second control signal having the I2C bus format is a hot plug control signal of the I2C bus format, that is, the second control signal is used to control the startup, hot swapping, and the like of the hard disk 190.

Also, the display state of the indicator light 170 may correspond to, for example, the operating state of the hard disk. That is, when the display state of the indicator light 170 is bright, the working state of the hard disk 190 can be started; when the display state of the indicator light 170 is blinking, the working state of the hard disk 190 can be the hot insertion function; When the display state of the indicator light is off, the working state of the hard disk 190 may not work. The foregoing description is only one embodiment of the present embodiment. Without limiting the present invention, the user can adjust the corresponding relationship between the indicator light 170 and the hard disk 190 according to the needs of the user. Further, control unit 180 is, for example, a PIC microcontroller. In this way, by analyzing the control signal generated by the central processing unit 120 through the control unit 180, the number of electronic components of the server system 100 can be effectively reduced, and the use cost of the electronic component can be reduced.

In addition, in the embodiment, the server system 100 further includes a clock signal generator 191 and a south bridge chip 192. The clock signal generator 191 generates a clock signal and transmits the clock signal to the central processing unit 120 and the south bridge chip 192 to allow the central processing unit 120 and the south bridge chip 192 to process and transmit data using the current pulse signal. Moreover, the clock signal is also transmitted to the hard disk 190 through the expansion unit 130, the first connector 160, and the control unit 180, so that the hard disk 190 can utilize the current pulse signal to cooperate with the central processing unit 120 to perform data synchronization processing and transmission. .

In addition, the backplane 150 of the server system 100 also includes a power connector 193. The power connector 193 is used to generate a voltage corresponding to the hard disk 190 for powering the hard disk 190. Also, the power source of the power connector 193 is provided, for example, by a power supply or a motherboard 110.

In summary, according to the technical solution of the present invention, the central processing unit is connected to the control unit through the expansion unit and the first connector (that is, the motherboard is connected to the backboard), so that the control unit can generate the central processing unit. The data signal is stored on the hard disk, and the first control signal and the second control signal generated by the central processing unit are parsed to control the indicator light and the hard disk through the first control signal and the second control signal. In this way, the number of electronic components used can be effectively reduced, the use cost of the electronic components can be reduced, and the working efficiency of the server system can be improved.

The above is only the embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. within the spirit and scope of the invention are intended to be included within the scope of the appended claims.

100‧‧‧Server System
110‧‧‧ motherboard
111‧‧‧First slot
120‧‧‧Central Processing Unit
130‧‧‧Extension unit
131‧‧‧Second connector
132‧‧‧second slot
150‧‧‧ Backplane
160‧‧‧First connector
170‧‧‧ indicator lights
180‧‧‧Control unit
190‧‧‧ Hard disk
191‧‧‧clock signal generator
192‧‧‧South Bridge Chip
193‧‧‧Power connector

FIG. 1 is a block diagram showing the structure of a server system according to an embodiment of the present invention.

100‧‧‧Server system

110‧‧‧ motherboard

111‧‧‧First slot

120‧‧‧Central Processing Unit

130‧‧‧Extension unit

131‧‧‧Second connector

132‧‧‧second slot

150‧‧‧ Backplane

160‧‧‧First connector

170‧‧‧ indicator lights

180‧‧‧Control unit

190‧‧‧ Hard disk

191‧‧‧clock signal generator

192‧‧‧South Bridge Chip

193‧‧‧Power connector

Claims (10)

A server system comprising: a motherboard, the motherboard comprising: a central processing unit, generating a Peripheral Component Interconnect Express (PCIE) format data signal, a first control signal having a PCIE format, and a second control signal having an inter-integrated circuit (I2C) bus bar format; and an expansion unit coupled to the central processing unit to transmit the PCIE format data signal, the PCIE format The first control signal and the second control signal having the I2C bus bar format; and a backplane, the backplane is coupled to the motherboard, and the backplane includes: a first connector, coupled And the control unit is coupled to the first connector, the indicator light and the hard disk, and receives the PCIE format data signal through the first connector, and the a first control signal in a PCIE format and a second control signal having an I2C bus format, and outputting the PCIE format data signal to the hard disk, and decoding the A first control signal having a PCIE format and the second control signal having an I2C bus format to separately control the indicator light and the hard disk. The server system of claim 1, wherein the server system further comprises a clock signal generator and a south bridge chip, wherein the clock signal generator generates a clock signal, and the time is The pulse signal is transmitted to the central processing unit and the south bridge wafer. The server system of claim 1, wherein the motherboard further comprises a first slot coupled to the central processing unit, the expansion unit further comprising a second connector and a first a second slot, wherein the second connector is coupled to the first slot, and the second slot is coupled to the first connector. The server system of claim 3, wherein the first slot and the second connector are slots and connectors having a PCIE transport protocol. The server system of claim 3, wherein the second slot and the first connector are plugs with a Mini Serial Attached SCSI (Mini SAS) transmission protocol. Slots and connectors. The server system of claim 3, wherein the expansion unit is an expansion card having a Non-Volatile Memory Express (NVMe). The server system of claim 1, wherein the first control signal having the PCIE format is an indicator light control signal of the PCIE format, and the second control signal having the I2C bus format is an I2C bus. Format hot swap control signal. The server system of claim 1, wherein the backplane further comprises a power connector, the power connector generating a voltage to supply power to the hard disk. The server system of claim 1, wherein the control unit is a PIC microcontroller. The server system of claim 1, wherein the display state of the indicator light corresponds to an operating state of the hard disk.