TWI578439B - Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer - Google Patents

Description

Semiconductor device manufacturing method and semiconductor integrated circuit wafer [reference to relevant application]

The present application is based on the priority benefits of U.S. Patent Application Serial No. 61/950,576, filed on March 10, 2014, and U.S. Patent Application Serial No. 14/317,648, filed on Jun. It enjoys its benefits and all of its contents are included in the case by reference.

This embodiment relates to a general semiconductor device manufacturing method and a semiconductor integrated circuit wafer.

Conventionally, a technique in which a plurality of semiconductor wafers in which an integrated circuit is formed is laminated, and each semiconductor wafer is electrically connected to each other by TSV (Through Silicon Via) to reduce the occupied area of the semiconductor device has existed. In the manufacture of semiconductor wafers, a majority of the wafer field is formed on a semiconductor wafer via a dicing line. Then, the semiconductor wafer is cut along the cutting line and then monolithic after being inspected for electrical characteristics. Formed into individual semiconductor wafers. It is important to ensure the yield (the number of wafers per wafer) for semiconductor wafers to improve yield. On the other hand, the assurance of inspection fields is also important.

Further, in the photolithography method used in the manufacture of a semiconductor wafer, it is required to position the rapid exposure position such that cracks on the dicing line do not occur or the influence on the characteristics of the semiconductor wafer does not occur.

In the embodiment, the marking opening portion can be easily and quickly detected, and the workability of the exposure time can be improved.

Further, the embodiment can be ensured without lowering the yield, and the electrical characteristics of the integrated circuit and the electrical characteristics of the TSV can be evaluated from the back surface.

According to an embodiment of the invention, in a method of manufacturing a semiconductor device, a semiconductor substrate is formed in a plurality of wafer regions in which a bulk circuit is formed on one surface side of a semiconductor substrate, and a semiconductor substrate is formed in a thickness direction to reach a front memory circuit. In the dicing line in which the surface of the pre-recorded wafer is separated, the first mark opening portion and the second semiconductor substrate in the thickness direction are disposed in the peripheral region of the first mark opening portion. Marking the opening portion; detecting the first mark opening portion based on the position of the second mark opening portion; and performing the exposure position by the position of the first mark opening portion according to the foregoing The photolithography method is performed to form a photoresist pattern having a first opening portion exposed on the back surface of the pre-recorded semiconductor substrate, which is formed on the back surface of the pre-recorded semiconductor substrate, on the back surface of the pre-recorded semiconductor substrate; The conductive material is buried; the pre-recorded photoresist pattern is removed.

Further, an embodiment provides a semiconductor integrated circuit wafer including a plurality of wafer fields in which an integrated circuit is provided on one surface side of a semiconductor substrate, and a dicing line is formed in a pre-recorded semiconductor substrate The wafer area is divided; and the TEG is a front cut line provided on one side of the front surface semiconductor substrate; and the first through electrode is exposed on the back side of the front semiconductor substrate in the preceding cut line and the semiconductor substrate is printed from the front The back side is connected to the front surface TEG in the thickness direction through the front semiconductor substrate.

According to the embodiment, the marking opening portion can be easily and quickly detected, and the workability of the exposure time can be improved. Further, according to the embodiment, it is possible to ensure the electrical characteristics of the integrated circuit and the electrical characteristics of the TSV from the back surface without securing the yield.

1‧‧‧Semiconductor integrated circuit wafer

2‧‧‧ Wafer field

3‧‧‧ cutting line

11‧‧‧Semiconductor substrate

12‧‧‧ circuit layer

13‧‧‧Test circuit components

14‧‧‧Next layer

15‧‧‧Support substrate

16‧‧‧Integrated circuit

21‧‧‧through hole

22‧‧‧ Openings

23‧‧‧through holes

31‧‧‧ openings

32‧‧‧Test through hole

33‧‧‧1st mark opening

34‧‧‧2nd mark opening

35‧‧‧through holes

36‧‧‧through holes

37‧‧‧ openings

41‧‧‧Light resistance

42‧‧‧Light resistance

51‧‧‧Interlayer insulating film

61‧‧‧passivation film

62‧‧‧Protective film

63‧‧‧Upper electrode

64‧‧‧Upper electrode pad

71‧‧‧Oxide film

72‧‧‧ nitride film

73‧‧‧Oxide film

74‧‧‧ barrier metal

81‧‧‧Test probe

11a‧‧‧ Positioning Mark

16a‧‧‧Contacts

16b‧‧‧1st wiring layer

16c‧‧‧2nd wiring layer

16d‧‧‧3rd wiring layer

16e‧‧‧ barrier metal

21a‧‧‧Bumps

32a‧‧‧Bumps

Fig. 1 is a plan view of the semiconductor wafer according to the embodiment as viewed from the back side.

2A to 2D are diagrams showing the structure of a semiconductor wafer according to an embodiment.

3A to 3C are diagrams showing a manufacturing process of a semiconductor wafer according to an embodiment.

4A to 4C are diagrams showing a manufacturing process of a semiconductor wafer according to an embodiment.

5A to 5C are diagrams showing a manufacturing process of a semiconductor wafer according to an embodiment.

6A to 6C are diagrams showing a manufacturing process of a semiconductor wafer according to an embodiment.

7A to 7C are diagrams showing a manufacturing process of a semiconductor wafer according to an embodiment.

8A and 8B are views showing examples of formation of a second mark opening portion in the dicing line according to the embodiment.

Fig. 9 is a cross-sectional view of an essential part of the wafer field of the semiconductor wafer according to the embodiment.

10A and 10B are cross-sectional views of essential parts for explaining a method of forming an element layer in the wafer field.

Fig. 11 is a schematic diagram for explaining the method of electrical characteristic test described in the embodiment.

According to the present embodiment, the one surface side of the semiconductor substrate is formed in the thickness direction in the plurality of wafer fields in which the integrated circuit is formed. a through hole that penetrates the semiconductor substrate before reaching the pre-recorded circuit; and a first mark opening portion is formed in the dicing line that separates the surface of the pre-recorded wafer in the semiconductor substrate, and the semiconductor substrate is inserted through the front semiconductor substrate in the thickness direction. The first mark is the first mark opening portion in the peripheral region of the opening portion. Next, the first mark opening portion is detected based on the position of the second mark opening portion, and the light lithography method is performed by positioning the exposure position based on the position of the first mark opening portion. The resist pattern of the first opening in which the back surface of the semiconductor substrate is exposed on the back surface of the through-hole is formed on the back surface of the pre-recorded semiconductor substrate. Then, a conductive material is filled in the through-holes, and the photoresist pattern is removed; and a method of manufacturing the semiconductor device having the above features is provided.

Hereinafter, a method of manufacturing a semiconductor device and a semiconductor integrated circuit wafer according to the embodiment will be described in detail with reference to the accompanying drawings. Further, the present invention is not limited to the embodiment. Further, in the drawings shown below, the scale of each member is sometimes different from the actual one for easy understanding. The same is true between the drawings. Moreover, even in the case of a plan view, sometimes a shadow is added in order to make the drawing easy to see.

Fig. 1 is a plan view of the semiconductor integrated circuit wafer 1 according to the embodiment as viewed from the back side. In the semiconductor integrated circuit wafer 1, the plurality of wafer fields 2 are formed in a matrix shape by being cut by the dicing lines 3. The semiconductor integrated circuit wafer 1 is diced into a plurality of wafer regions 2 by being cut along the dicing lines 3 to become a semiconductor wafer (semiconductor device).

2A to 2D are diagrams showing the structure of the semiconductor integrated circuit wafer 1 according to the embodiment. 2A is a semiconductor integrated circuit wafer 1 The enlarged view of the main part of the back side is enlarged. 2B is a cross-sectional view of an essential part of the wafer field 2 of the semiconductor integrated circuit wafer 1, and is a cross-sectional view taken along line A-A of FIG. 2A. 2C is a cross-sectional view of a principal part of a dicing line 3 of the semiconductor integrated circuit wafer 1, and is a cross-sectional view taken along line B-B of FIG. 2A. Fig. 2D is an enlarged view of an essential part showing an enlarged cross section of the cutting line 3. Here, in FIGS. 2B to 2D, the surface of the semiconductor integrated circuit wafer 1 is placed downward. In the following description, the surface of the semiconductor integrated circuit wafer 1 or the semiconductor substrate 11 means a surface on which the circuit layer 12 to be described later is provided. The back surface of the semiconductor integrated circuit wafer 1 or the semiconductor substrate 11 means the surface on the opposite side of the surface of the semiconductor integrated circuit wafer 1 or the semiconductor substrate 11.

In the semiconductor integrated circuit wafer 1, a circuit layer 12 on which an integrated circuit including an upper electrode pad or a circuit element is formed is provided on one surface (surface) of the semiconductor substrate 11. The circuit layer 12 can also be intermittently arranged as needed.

In the wafer field 2 on the back surface of the semiconductor integrated circuit wafer 1, a via hole 21 having a bump portion 21a which is exposed from the back surface of the semiconductor integrated circuit wafer 1 and which is exposed is provided. The through hole 21 is provided to penetrate the semiconductor substrate 11 in the thickness direction. When the semiconductor wafer in which the wafer area 2 is diced is multi-layered, the via hole 21 is electrically connected to the integrated circuit provided in the semiconductor circuit of the lower semiconductor wafer and the semiconductor wafer of the upper semiconductor wafer. Connect the required through electrode (TSV: Through Silicon Via). The through hole 21 is formed by, for example, nickel. In addition, the bump portions may be laminated with, for example, copper and solder. Wait.

The circuit layer 12 of the dicing line 3 is a test circuit layer formed as a test circuit element 13 of a TEG (Test Element Group). The TEG (Test Circuit Element 13) is provided in plural to indirectly inspect the electrical characteristics of the integrated circuit provided in the wafer field 2, and the electrical characteristics of the TSV (through hole 21) formed in the wafer field. An independent circuit pattern required for the electrical characteristics of the daisy-chain connection formed by stacking the semiconductor integrated circuit wafer 1 and the electrical characteristics.

The dicing line 3 on the back surface of the semiconductor integrated circuit wafer 1 is provided with an opening portion 31 and a test through hole 32 for projecting the exposed bump portion 32a from the back surface of the semiconductor integrated circuit wafer 1. The opening portion 31 is used as a positioning mark in the manufacture of the semiconductor integrated circuit wafer 1 as will be described later.

The test through hole 32 is a through electrode (TSV) that penetrates the semiconductor substrate 11 in the thickness direction and is connected to the test circuit element 13 as shown in FIG. 2C and FIG. 2D. The test through hole 32 is used for inspection of the electrical characteristics of the test circuit element 13. In addition, the test through hole 32 is also used in the test circuit provided in the lower semiconductor integrated circuit wafer 1 when the semiconductor integrated circuit wafer 1 is laminated in multiple layers to form a daisy chain connection. The element 13 and the test circuit element 13 provided in the upper semiconductor integrated circuit wafer 1 are electrically connected. The through hole 32 for testing is formed by, for example, nickel. Further, the bump portion may be laminated with, for example, copper, solder, or the like.

In addition, although it is also the width of the cutting line 3 and the cutting blade Depending on the width, when the semiconductor integrated circuit wafer 1 is cut along the dicing line 3 and the wafer area 2 is singulated, most of the dicing line 3 disappears. Therefore, when the wafer area 2 is singulated, the opening portion 31 and the test through hole 32 also disappear.

Next, the manufacturing process of the semiconductor integrated circuit wafer 1 according to the embodiment will be described. 3A to 7C are diagrams showing a manufacturing process of the semiconductor integrated circuit wafer 1 according to the embodiment. In FIGS. 3A to 7C, FIG. XA (X is an integer of 3 to 7) is a plan view, and FIG. XB (X is an integer of 3 to 7) is a cross-sectional view of AA in FIG. The system is an integer from 3 to 7) and is a BB cross-sectional view in Fig. XA.

In the manufacture of the semiconductor integrated circuit wafer 1, a resin-based adhesive is applied to the surface side of the semiconductor substrate 11 on which the circuit layer 12 is formed to form the adhesive layer 14, and then the support substrate 15 is pasted on the upper surface of the adhesive layer 15. . The circuit layer 12 has a thickness of, for example, about 3 μm. Then, the back surface side of the semiconductor substrate 11 is polished by, for example, CMP, and the semiconductor substrate 11 is thinned (FIGS. 3A to 3C). The thinning of the semiconductor substrate 11 is continued until the thickness of the through hole can be formed in the semiconductor substrate 11.

Here, in the circuit layer 12 of the wafer field 2, an integrated circuit is formed, but the circuit layer 12 of the dicing line 3 forms the test circuit element 13. Next, the thickness of the layer 14 is, for example, about 50 μm. The support substrate 15 is, for example, a tantalum substrate or a glass substrate.

Next, in the wafer field 2, the semiconductor substrate 11 is penetrated in the thickness direction from the back side of the semiconductor substrate 11 to reach the integrated circuit. The through holes up to this are formed by photolithography and etching. First, for example, a hafnium oxide film, a tantalum nitride film, and a hafnium oxide film are formed on the back surface of the semiconductor substrate 11 as an insulating layer (not shown). Then, after the photoresist 41 is applied onto the back surface of the semiconductor substrate 11, exposure and development are performed, and a circular opening portion 22 such as a circular opening 22 that penetrates the photoresist 41 in the thickness direction and reaches the back surface of the semiconductor substrate 11 is formed. Photoresist 41 in the field of wafers (Fig. 4A, Fig. 4B).

The positioning at the time of exposure of the photoresist 41 is performed by using the positioning mark 11a formed in advance in the semiconductor substrate 11 at the time of formation of the integrated circuit. In the plan view of Figs. 3A and 4A, the positioning mark 11a is illustrated for easy understanding, but the positioning mark 11a is invisible to the naked eye. Therefore, the position of the exposure position (the position of the mask) at the time of exposure of the photoresist 41 is, for example, an infrared microscope (Infrared Microscope) is used to inspect the back surface of the semiconductor substrate 11 to observe the positioning mark 11a, which is based on the positioning mark 11a.

In the formation of the opening 22, the first mark opening portion 33 and the second mark opening portion 34 formed by the through holes extending through the photoresist 41 in the thickness direction and reaching the back surface of the semiconductor substrate 11 are the openings. 22 is simultaneously formed in the dicing line 3 by exposure and development (Fig. 4A, Fig. 4C). Thereby, a mask pattern (resist pattern) required for etching the back side of the semiconductor substrate 11 is formed.

The first mark opening portion 33 is a positioning mark for positioning of an exposure position (position of the mask) at the time of exposure of the photoresist 42 to be described later. The first mark opening portion 33 is formed, for example, on a semiconductor base A plurality of intersection areas of the cutting lines 3 intersecting in the direction of the faces of the plates 11. Further, the position at which the first mark opening portion 33 in the dicing line 3 is formed is not limited to the intersection area of the above. The shape of the first mark opening portion 33 is not particularly limited as long as it can be positioned at the time of exposure of the photoresist 42. The size of the first mark opening portion 33 in the surface direction of the semiconductor substrate 11 is not particularly limited as long as it can be positioned during exposure of the photoresist 42. However, it is set to, for example, 30 to 40 μm from the viewpoint of positioning accuracy. .

The second mark opening portion 34 is an induction mark required for detecting the first mark opening portion 33 when the photoresist 42 is exposed. When the photoresist 42 is exposed to light, a normal microscope is used without using infrared rays, and positioning is performed based on the first mark opening portion 33. When the first mark opening portion 33 is detected, the coordinate position at which the first mark opening portion 33 is formed is set to a microscope, and the first mark opening portion 33 is found around the coordinate position. However, in order to prevent the occurrence of cracks on the dicing line 3 at the time of dicing or the influence on the characteristics of the semiconductor wafer, the first mark opening portion 33 is required to be the minimum necessary number of positions. Therefore, it is difficult to detect the first mark opening portion 33 on the back surface of the semiconductor substrate 11, and it takes time to detect the first mark opening portion 33.

Then, in the present embodiment, the second mark opening portion 34 is formed in the cutting line 3 in the peripheral region of each of the first mark opening portions 33 in the surface direction of the semiconductor substrate 11. When the photoresist 42 is exposed, even if the first marker opening portion 33 itself cannot be directly detected, the periphery of the second marker opening portion 34 that has been detected can be easily searched for, and the measurement can be easily detected in a short time. 1 marks the opening portion 33. Also, by opening the second mark When the number of formations 34 is increased, the second mark opening portion 34 can be more easily detected. As a result, the exposure processing can be performed efficiently, and the productivity of the semiconductor integrated circuit wafer 1 can be improved.

The second mark opening portion 34 is formed in plural numbers in the cutting line 3 around the first mark opening portion 33 in the surface direction of the semiconductor substrate 11. The shape of the second mark opening portion 34 may be measured as long as it can be exposed during exposure of the photoresist 42, and is, for example, circular. The size of the second mark opening portion 34 in the surface direction of the semiconductor substrate 11 may be measured at the time of exposure of the photoresist 42 and may be, for example, about 10 μm. Further, the size of the second mark opening portion 34 is set to be smaller than the size of the first mark opening portion 33 in order to eliminate the occurrence of cracks on the dicing line 3 at the time of dicing or the influence on the characteristics of the semiconductor wafer. . Further, the size of the second mark opening portion 34 is such a size that the opening portion can be surely formed in the etching of the semiconductor substrate 11 in which the photoresist 41 is used as an etching mask.

Then, at least one of the shape and the size of the second mark opening portion 34 is formed under the condition different from the first mark opening portion 33. When the second mark opening portion 34 has the same shape and the same size as the first mark opening portion 33, the first mark opening portion 33 is in the same state as the first mark opening portion 33 in the vicinity of the formation area of the first mark opening portion 33. There is a possibility of occurrence of cracking at the time of exposure and cracking on the dicing line 3 at the time of dicing or adverse effects on the characteristics of the semiconductor wafer.

The second mark opening portion 34 is formed in plural along the extending direction of the dicing line 3, for example, at a predetermined pitch. The formation pitch of the second mark opening portion 34 is, for example, sandwiched between the first mark opening portions 33. The two fields of the opposing cutting line 3 are set to the same pitch (Fig. 4A, Fig. 4C). Further, the pitch of the second mark opening portion 34 may be set to be different in the two fields of the cutting line 3 that faces the first mark opening portion 33 as shown in Figs. 8A and 8B. spacing. 8A and 8B are views showing examples of formation of the second mark opening portion 34 in the dicing line 3. Fig. 8B is an enlarged view of an essential part of Fig. 8A.

The formation pitch of the second mark opening portion 34 in the two fields of the cutting line 3 that faces the first mark opening portion 33 is different, and the second mark opening portion 34 is formed based on the detected The pitch can indicate the direction in which the first mark opening portion 33 exists. For example, in the example of FIG. 8B, when the pitch of the second mark opening portion 34 that has been detected is 100 μm, it is understood that the first mark is in the direction in which the cutting line 3 exists in the second mark opening portion 34. The opening portion 33 is located in the left direction. When the pitch of the second mark opening portion 34 that has been detected is 60 μm, it is understood that the first mark opening portion 33 is located on the right in the extending direction of the cut line 3 in which the second mark opening portion 34 exists. direction. Thereby, after the second mark opening portion 34 is detected, the first mark opening portion 33 can be easily detected in a short time.

When the first mark opening portion 33 is formed in the intersection region of the intersecting cutting lines 3, the second mark opening portion 34 may be formed in the extending direction along the cutting line 3 and centered on the intersection point area. In the direction. Thereby, the second mark opening portion 34 can be more easily detected, and the first mark opening portion 33 can be easily detected in a short time. Further, it is also possible to form the pitch of the second mark opening portion 34 in the cut line 3 in the four directions. Different from each other. Thereby, the second mark opening portion 34 can be more easily detected, and the first mark opening portion 33 can be easily detected in a short time.

Next, a mask pattern (resistance pattern) is used as an etching mask, and an anisotropic dry etching such as reactive ion etching (RIE) is performed from the back surface of the semiconductor substrate 11 toward the circuit layer 12. Thereby, the through hole 23 that penetrates the semiconductor substrate 11 in the thickness direction from the back surface side of the semiconductor substrate 11 and reaches the integrated circuit is formed in the wafer region 2 (FIGS. 5A and 5B). The etching of the semiconductor substrate 11 is performed by, for example, using the uppermost layer of the circuit layer 12 as an etching stopper.

In addition, the through hole that penetrates the semiconductor substrate 11 in the thickness direction from the back surface side of the semiconductor substrate 11 and reaches the test circuit element 13 by the etching corresponds to the through hole 35 of the first mark opening portion 33 and corresponds to The through hole 36 of the second mark opening portion 34 is formed in the dicing line 3 (Figs. 5A and 5C). Thereafter, the through hole 23, the through hole 35, the inner circumferential surface of the through hole 36, and the back surface of the semiconductor substrate 11 are covered with an oxide film. Further, the illustration of the oxide film is omitted.

Next, the oxide film of the bottom portion of the through hole 23 and the through hole 35 and the through hole 36 is removed by etching so that the upper surface of the uppermost layer of the circuit layer 12 is exposed. Then, the through hole 23, the inner peripheral surface of the through hole 35 and the through hole 36, and the back side of the semiconductor substrate 11 are covered with a barrier metal. In addition, the illustration of the barrier metal is omitted. The barrier metal is formed by sputtering by a film such as titanium nitride or nickel nitride. Further, the barrier metal is capable of suppressing the through hole 23 and the through hole as long as it is The material in which the metal filled in the through hole 36 and the metal filled in the through hole 36 are diffused toward the semiconductor substrate 11 may be formed of any material other than the above materials.

Thereafter, the photoresist 42 is applied to the back side of the semiconductor substrate 11 which is coated on the back side by the barrier metal. Thereafter, exposure and development are performed, and a circular opening portion 24 that penetrates the photoresist 42 in the thickness direction and reaches the back surface of the semiconductor substrate 11 is formed in the wafer region 2 of the photoresist 42 (FIGS. 6A and 6B). At this time, in order to form an opening 24 having a larger opening area than the through hole 23 at the opening position of the back surface side of the semiconductor substrate 11 in the through hole 23, the photoresist 42 is patterned. Thereby, a photoresist pattern having an opening portion 24 in which the field of the through-hole 23 is exposed is formed in the surface direction of the semiconductor substrate 11.

In the same manner, the circular opening portion 37 that penetrates the photoresist 42 in the thickness direction and reaches the back surface of the semiconductor substrate 11 is formed in the cutting line 3 of the photoresist 42 simultaneously with the opening portion 24. (Fig. 6A, Fig. 6C). At this time, in order to form an opening 37 having an opening area larger than the through hole 36 at the opening position on the back side of the semiconductor substrate 11 in the through hole 36, the photoresist 42 is patterned. Thereby, a photoresist pattern having an opening portion 37 in which the region of the inner through-hole 36 is exposed is formed in the surface direction of the semiconductor substrate 11. Further, the through hole 35 is filled with the photoresist 42.

The positioning at the time of exposure of the photoresist 42 is performed using the first mark opening portion 33. The position of the exposure position (the position of the mask) at the time of exposure of the resist 42 is such that the first mark opening portion 33 is observed by a normal microscope that does not use infrared rays, and the position of the first mark opening portion 33 is It. As described above, the second mark opening portion 34 is formed in the peripheral region of each of the first mark opening portions 33. Therefore, even if the first mark opening portion 33 itself cannot be directly detected, the first mark opening portion 33 can be easily detected in a short time by exploring the periphery of the second mark opening portion 34 that has been detected.

Next, the conductive member is filled in the through hole 23 and the opening 24 of the photoresist 42, and the via hole 21 connected to the integrated circuit is formed in the wafer region 2. Further, by filling the inside of the through hole 36 and the opening 37 of the photoresist 42 with a conductive member, the test through hole 32 connected to the test circuit element 13 is formed at the same time as the through hole 21 at the cutting line. 3. The conductive member is, for example, nickel. These vias are formed, for example, by sputtering or electroplating. Further, in these through holes, the conductive member filled in the opening portion of the photoresist 42 is a bump portion (FIGS. 7A to 7C).

Thereafter, the barrier metal under the photoresist 42 and the photoresist 42 is peeled off, and then the support substrate 15 and the adhesion layer 14 are peeled off. Thereby, the semiconductor integrated circuit wafer 1 shown in FIGS. 2A to 2C is formed.

The semiconductor integrated circuit wafer 1 is diced and diced in each wafer area after the implementation of the electrical characteristic test. The semiconductor wafer which has been singulated is packaged by a resin or the like after being laminated, and becomes a product. Here, the singulation of the wafer field 2 is performed by cutting the semiconductor integrated circuit wafer 1 along the dicing line 3. At this time, most of the cutting line 3 disappears. Further, the opening portion 31 and the test through hole 32 also disappear.

Next, details of the configuration example of the circuit layer 12 of the wafer field 2 will be described. FIG. 9 is a cross-sectional view of an essential part of the wafer field 2 of the semiconductor integrated circuit wafer 1. The wafer field 2 includes an integrated circuit 16 and a via hole 21 which are provided on the surface side of the semiconductor substrate 11. As the semiconductor substrate 11, for example, a germanium wafer or the like is used. The through hole 21 penetrates the semiconductor substrate 11 in the thickness direction and is connected to the integrated circuit 16.

The integrated circuit 16 is provided inside the interlayer insulating film 51 formed on the surface of the semiconductor substrate 11. The interlayer insulating film 51 is formed of an insulating material such as yttrium oxide. The integrated circuit 16 is, for example, an LSI (Large Scale Integration) including a NAND type semiconductor memory and multilayer wiring. Further, in Fig. 9, portions of the multilayer wiring in the integrated circuit 16 are selectively exemplified.

Further, on the surface of the integrated circuit 16, a passivation film 61 and a protective film 62 are laminated. The passivation film 61 is formed of, for example, hafnium oxide or tantalum nitride. The protective film 62 is formed of a resin such as PET (polyethylene terephthalate) or polyimine.

At a predetermined position on the surface of the protective film 62, an upper electrode pad 64 is provided. The upper electrode pad 64 is formed of, for example, gold. The upper electrode pad 64 and the integrated circuit 16 electrically and physically connect a portion of the protective film 62, the passivation film 61, and the interlayer insulating film 51 by penetrating the upper electrode 63 of the semiconductor substrate 11 in the thickness direction. . The upper electrode 63 is formed of, for example, nickel.

On the back surface of the semiconductor substrate 11, for example, a hafnium oxide film 71, a tantalum nitride film 72, and a hafnium oxide film 73 are laminated. Through hole 21, These films and the semiconductor substrate 11 are provided to penetrate in the thickness direction. The end portion of the through hole 21 that is exposed to the back side of the semiconductor substrate 11 is such that when the semiconductor wafer in which the wafer region 2 is diced is laminated in multiple layers, the upper electrode pad of the semiconductor wafer is opposed to the opposite side. 64 obtains the bump portion 21a required for conduction. A barrier metal 74 is provided between the outer peripheral surface of the through hole 21 and the semiconductor substrate 11, and between the end portion (the bump portion 21a) of the through hole 21 exposed to the back side of the semiconductor substrate 11 and the yttrium oxide film 73. .

Further, in the dicing line 3 of the circuit layer 12, for example, the test circuit element 13 is replaced by the integrated circuit 16 in Fig. 9, and the test through hole 32 is provided instead of the through hole 21. The peripheral structure of the test through hole 32 and the connection structure of the test through hole 32 and the test circuit element 13 are the same as those of the above-described through hole 21.

The through hole 32 for testing is provided so as to penetrate the semiconductor substrate 11 in the thickness direction. The through hole 32 for testing is to test the electrical characteristics of the daisy chain connection of the semiconductor integrated circuit wafer 1 by the test circuit element 13, and also has the semiconductor integrated circuit wafer as the lower layer. The function of the through electrode (TSV) in which the test circuit element 13 included in the test circuit element 13 and the test circuit element 13 included in the upper semiconductor integrated circuit wafer 1 are electrically connected.

Next, a method of forming the circuit layer 12 will be described. 10A and 10B are cross-sectional views for explaining the method of forming the circuit layer 12 in the wafer region 2. First, in the field of the wafer region 2 on the surface side of the semiconductor substrate 11, the integrated circuit 16 is formed (FIG. 10A). E.g, When the multilayer wiring of the integrated circuit 16 is formed, a ruthenium oxide film is formed on the surface of the semiconductor substrate 11, and the concave portion required for forming the contact portion 16a in the yttrium oxide film is formed by photolithography and etching in the concave portion. The polycrystalline germanium is filled in. Thereafter, a nickel layer is formed on the polycrystalline silicon, and nickel bismuth is formed by heating engineering to form the contact portion 16a.

In addition, the material of the contact portion 16a is not limited to the nickel ruthenium, and may be a material that can function as an etch stop when the semiconductor substrate 11 is etched as described above. For example, tungsten or the like may be used. Any metal, or any metal halide.

Thereafter, the ruthenium oxide film formation process is repeated, the yttrium oxide film is patterned by photolithography and etching, and the concave portion of the wiring pattern formed by patterning is covered by the barrier metal. Engineering to cover and fill conductive components.

Thereby, the interface between the interlayer insulating film 51 and the interlayer insulating film 51 is the first wiring layer 16b, the second wiring layer 16c, and the third wiring layer 16d which are covered by the barrier metal 16e. form. By performing such a process, the integrated circuit 16 is formed in the wafer field 2. Further, by performing such a process, the circuit board 12 for the dicing line 3, the test circuit element 13 and the integrated circuit 16 are simultaneously formed by the same process.

Here, for example, tungsten is used for the first wiring layer 16b. For example, copper is used for the second wiring layer 16c. For example, aluminum is used for the third wiring layer 16d. In addition, a conductive member other than the above-described metal may be used for the first interconnect layer 16b, the second interconnect layer 16c, and the third interconnect layer 16d.

Further, for example, titanium nitride or nickel nitride is used for the barrier metal 16e. In addition, the barrier metal 16e may be any material that can suppress the diffusion of the conductive member from the first wiring layer 16b, the second wiring layer 16c, and the third wiring layer 16d to the interlayer insulating film 51, and may be used other than the above materials. Any material.

Further, at any point in time when the integrated circuit 16 is formed, the above-described complex positioning marks 11a (not shown) are formed in the semiconductor substrate 11. Thereafter, on the upper surface of the interlayer insulating film 51, a passivation film 61 using, for example, hafnium oxide or tantalum nitride is formed.

Next, on the upper surface of the passivation film 61, a protective film 62 is formed by a resin such as PET or polyimide. Thereafter, through holes are formed in the wafer field 2 and the dicing line 3 in the same process. In other words, in the wafer field 2, a through hole is formed in which the protective film 62, the passivation film 61, and one of the interlayer insulating films 51 are penetrated to reach the integrated circuit 16. In addition, the dicing line 3 is formed, and a part of the protective film 62, the passivation film 61, and the interlayer insulating film 51 is penetrated to reach the through hole of the test circuit element 13.

Next, the upper electrode 63 is formed, for example, by filling nickel into the through hole. Further, the upper electrode 63 may be a conductive member, and a metal other than nickel may be used.

Next, on the exposed surface above the upper electrode 63, the upper electrode pad 64 is formed using, for example, gold (Fig. 10B). Further, the upper electrode pad 64 may be a conductive member, and a metal other than gold may be used. By the above engineering, the semiconductor guided with the circuit layer 12 is obtained. Body substrate 11.

Next, an electrical characteristic test for indirectly investigating the electrical characteristics of the integrated circuit formed in the wafer field 2 and the electrical characteristics of the TSV will be described. The electrical characteristic test is an indirect investigation of the completion state of the integrated circuit and the TSV. In the electrical characteristic test, a device called a probe is used, and the test probe 81 is connected to the bump portion 32a of the test through hole 32 as shown, for example, in FIG. Fig. 11 is a schematic diagram for explaining the method of electrical characteristic test.

When the TSV connected to the integrated circuit is formed in the wafer region 2, the semiconductor substrate 11 is thinned to the extent that the through hole can be formed. Moreover, in order to transport the thinned semiconductor substrate 11 in a manufacturing process, the support substrate 15 is adhered to the surface of the semiconductor substrate 11 via the adhesive layer 14. Therefore, the electrical property test cannot be performed from the surface side of the semiconductor substrate 11.

Further, for example, in the manufacture of a semiconductor memory such as a NAND type, in order to secure the yield, the TEG field is housed in the dicing line. Then, in the case of a NAND type semiconductor memory having TSV, it is preferable to house the TEG field in the dicing line. However, if the electrode pad for TEG is placed in the cutting line, the pattern of the TEG cannot be accommodated in the cutting line.

On the other hand, in the semiconductor integrated circuit wafer 1 according to the embodiment, the test circuit element 13 is formed on the cut line 3 on the surface side of the semiconductor substrate 11. Further, the TSV connected to the test circuit element 13, that is, the test through hole 32, is on the back side of the semiconductor substrate 11 Pull out. The test through hole 32 has a bump portion 32a that protrudes from the back surface of the semiconductor substrate 11 and is exposed. The test through hole 32 is formed by using the second mark opening portion 34 which is an inducing mark of the first mark opening portion 33 as described above. Thereby, in the semiconductor integrated circuit wafer 1, the members necessary for the electrical characteristic test can be housed in the dicing line 3. Moreover, the electrical characteristic test can be performed from the back side of the semiconductor integrated circuit wafer 1. Therefore, in the semiconductor integrated circuit wafer 1, it can be ensured without lowering the yield, and the electrical characteristics of the integrated circuit and the electrical characteristics of the TSV can be evaluated from the back side.

In the same manner as the integrated circuit 16, by forming the upper electrode 63 and the upper electrode pad 64 connected to the test circuit element 13, the semiconductor integrated circuit wafer 1 can be stacked in multiple layers to perform the test circuit element 13 Testing of the electrical characteristics of the daisy chain connection.

Further, when the semiconductor integrated circuit wafer 1 is transported without being cut, the test via hole 32 can be used to perform the electrical characteristic test at an arbitrary timing.

According to the embodiment, the second mark opening portion 34 is formed in the peripheral region of each of the first mark opening portions 33. As a result, the first mark opening portion 33 can be easily detected in a short time by exploring the periphery of the second mark opening portion 34 that has been detected, and the workability of the exposure processing can be improved, and such an effect can be obtained.

Further, according to the embodiment, the test circuit element 13 is formed on the cut line 3 on the surface side of the semiconductor substrate 11. Further, the test through hole 32 connected to the test circuit component 13 is attached to the cutting line 3 The back side of the semiconductor substrate 11 is pulled out. As a result, it is possible to obtain an effect that the semiconductor integrated circuit wafer 1 can be realized by performing the evaluation of the electrical characteristics of the integrated circuit and the electrical characteristics of the TSV from the back side without lowering the yield.

The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention can be implemented in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. These embodiments and their modifications are encompassed by the scope of the invention, and the scope of the invention, and the scope of the invention as defined in the appended claims.

1‧‧‧Semiconductor integrated circuit wafer

2‧‧‧ Wafer field

3‧‧‧ cutting line

Claims (26)

A method of manufacturing a semiconductor device, characterized in that a through-hole is formed in a plurality of wafer fields in which an integrated circuit is formed on one surface side of a semiconductor substrate, and a semiconductor substrate is inserted in a thickness direction to reach a pre-recorded circuit; In the semiconductor substrate, a first mark opening portion and a second mark opening portion that penetrates the front semiconductor substrate in the thickness direction and are disposed in a peripheral region of the first mark opening portion are formed in the dicing line that separates the surface of the pre-recorded wafer; The first mark opening portion is detected based on the position of the second mark opening portion, and the light lithography method is performed by positioning the exposure position according to the position of the first mark opening portion, so as to have the inner package The photoresist pattern of the first opening in which the back surface of the semiconductor substrate is exposed is formed on the back surface of the semiconductor substrate, and the conductive material is filled in the through hole in the front surface, and the photoresist pattern is removed. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is attached to the support substrate on one surface side before the formation of the front through hole and the first mark opening portion and the front mark second mark opening portion. The back side of the front is thinned. The method of manufacturing a semiconductor device according to claim 1, wherein A TEG is formed in the preceding cutting line on the one side of the front side, and a second opening in which the second mark opening portion of the inner package is exposed on the back surface of the front semiconductor substrate is formed in the pre-recorded photoresist pattern; The conductive material is filled in the second opening of the front part and the front part to be connected to the front TEG. The method of manufacturing a semiconductor device according to claim 1, wherein the pre-recorded semiconductor substrate is cut along the preceding dicing line to singulate the surface of the pre-recorded wafer, and the second mark opening portion and the second opening are preceded by The conductive material buried in the part is removed. The method of manufacturing a semiconductor device according to claim 1, wherein the size of the second mark opening portion in the surface direction of the semiconductor substrate is smaller than the size of the first mark opening portion. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the shape and the size of the second mark opening portion in the surface direction of the semiconductor substrate is different from the first mark opening portion. The method of manufacturing a semiconductor device according to claim 1, wherein the second mark opening portion is formed in plural at a predetermined pitch. A method of manufacturing a semiconductor device according to claim 1, wherein In the middle, the second mark opening portion is formed in two fields in which the first mark opening portion is opposed to the preceding cutting line. In the method of manufacturing a semiconductor device according to the eighth aspect of the invention, the second mark opening portion is formed in a plurality of fields that face each other with the first mark opening portion interposed therebetween. The method of manufacturing a semiconductor device according to the eighth aspect of the invention, wherein the second mark opening portion is formed at a different pitch in each of two fields facing the first mark opening portion. The method of manufacturing a semiconductor device according to claim 1, wherein the first mark opening portion is formed in an intersection region in which two preceding cutting lines intersect in a surface direction of the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 11, wherein the second mark opening portion is formed in a four-direction front cut line centering on the intersection point area. The method of manufacturing a semiconductor device according to claim 1, wherein the second mark opening portion is formed in a central region in the width direction of the preceding cutting line. A method of manufacturing a semiconductor device according to claim 1, wherein In the front, the front side of the wafer area is formed in the front side of the wafer side, and the first mark opening portion and the front mark second mark opening portion are simultaneously formed. A semiconductor integrated circuit wafer characterized by comprising: a plurality of wafers in which an integrated circuit is provided on one side of a semiconductor substrate; and a dicing line is provided in a pre-recorded semiconductor substrate to separate a field of a plurality of pre-recorded wafers; And the TEG is a front cut line provided on one surface side of the semiconductor substrate; and the first through electrode is exposed on the back side of the front semiconductor substrate in the front cut line and is in the thickness direction from the back side of the front semiconductor substrate The pre-recorded semiconductor substrate is connected to the front surface of the TEG; and the second through-electrode is exposed on the back side of the semiconductor substrate in the pre-recorded wafer field, and the semiconductor substrate is connected in the thickness direction from the back side of the front semiconductor substrate. The pre-recorded integrated circuit is provided with a circuit pattern required for indirect inspection of the electrical characteristics of the second through electrode. The semiconductor integrated circuit wafer according to claim 15, wherein the pre-recorded TEG is provided with a circuit pattern required for indirectly checking the electrical characteristics of the pre-recorded circuit. The semiconductor integrated circuit wafer according to claim 15, wherein The first through electrode is formed in the center of the width direction of the preceding cutting line. The semiconductor integrated circuit wafer according to claim 15, wherein the first through electrode is provided on the surface on the back side of the semiconductor substrate, and has a bump portion. A semiconductor integrated circuit wafer characterized by comprising: a plurality of wafers in which an integrated circuit is provided on one side of a semiconductor substrate; and a dicing line is provided in a pre-recorded semiconductor substrate to separate a plurality of pre-recorded wafer regions; 1 mark, which is provided in the preceding cutting line; and a second mark provided in the preceding cutting line as the through hole, the front through hole being exposed on the back side of the front semiconductor substrate in the preceding cutting line and the semiconductor substrate from the front In the front side, the semiconductor substrate is penetrated in the thickness direction in the front side; at least one of the shape and the size of the second mark in the surface direction of the front semiconductor substrate is different from the first mark. The semiconductor integrated circuit wafer according to claim 19, wherein the second mark is formed at a predetermined pitch. The semiconductor integrated circuit wafer according to claim 19, wherein The second mark is formed in two fields in which the first mark is placed on the preceding cut line. The semiconductor integrated circuit wafer according to claim 21, wherein the plurality of pre-recorded second marks are formed in two fields facing each other with the first mark interposed therebetween. The semiconductor integrated circuit wafer according to claim 21, wherein the plurality of pre-recorded second marks are formed at different pitches in the two fields opposed to each other with the first mark interposed therebetween. The semiconductor integrated circuit wafer according to claim 19, wherein the first mark is formed in an intersection region in which two preceding cutting lines intersect in a surface direction of the semiconductor substrate. The semiconductor integrated circuit wafer according to claim 24, wherein the second mark is formed in a four-direction front cut line centering on a previous intersection area. The semiconductor integrated circuit wafer according to claim 19, wherein the second mark is formed in a central region in the width direction of the preceding cut line.