TWI577132B - Shifter register circuit - Google Patents

Description

Shift register circuit

The invention relates to a shift temporary storage circuit, in particular to a shift temporary storage circuit for outputting a signal via an output of a recharging module.

With the development of technology, system integration and lower manufacturing costs are the development trend of the electronics industry. In the prior art, the touch system for providing user touch sensing and the display system for providing image display are basically two systems that operate independently, but the display touch device is booming and the user is smart body type. Under the increasingly thin and light requirements, current display touch devices tend to use in-cell display touch panels integrated with touch systems and display systems.

In other words, the in-cell touch display panel switches the execution display mode and the touch mode in a time-lapse manner in a single screen period to sequentially drive the pixel unit in the display mode to make the screen change and touch. The touch sensing unit is sequentially driven in the control mode to sense the touch action on the display panel. When the display mode is switched to the touch mode, the shift register circuit that generates the pixel unit drive signal will stay at a certain level of the shift register until the end of the touch mode, and then the stage shift register Continue to generate drive signals.

However, when the display touch device switches back to the display mode, the shift register of the shift register continues to generate the drive signal, and the voltage of the shift register may have been drained to a lower level when the touch mode is executed. The voltage level affects the drive capability of the shift register and then the drive signal. In addition, in the touch mode, although the switching element of the shift register output driving signal is not turned on, the switching element is prone to be long when the voltage of the switching element control terminal is not discharged to a low voltage for driving capacity considerations. The influence of the voltage stress of the time, and the problem of the aging of the switch may also cause a problem of a decrease in the driving ability after a long period of use.

The present invention provides a shift temporary storage circuit for solving the problem that the driving ability of the shift register is lowered when the display touch device is switched back to the display mode in the prior art.

The shift temporary storage circuit disclosed in the present invention has a multi-stage shift register, wherein at least one stage shift register has a driving module, a recharging module, a pull-up module and a main pull-down module. The driving module is electrically connected to the first node at least, and provides a working signal to the first node according to the first driving signal. The recharging module is electrically connected to the first node and the second node, and has at least a power storage unit, a first switch and a control unit. One end of the power storage unit is electrically connected to the first node, and the other end of the power storage unit is electrically connected to the third node. The control unit is electrically connected to the first indication signal terminal at least, and the control unit provides a recharge signal to the first switch, and adjusts the voltage of the third node according to the voltage of the first node. The first switch provides a recharge signal to the second node according to the voltage of the third node. The pull-up module is configured to turn on the first clock signal end and the output node according to the voltage of the second node. The main pull-down module is configured to turn on the output node and the reference voltage end according to the voltage of the second clock signal end.

According to the shift temporary storage circuit disclosed in the present invention, the working signal of the shift register of the current stage is stored in the first node by the setting of the recharging module, and is stored in advance until switching back to the display mode. The voltage at the first node is output to the second node, and the voltage of the second node is further increased by the recharging signal, thereby improving the driving capability when the shift register continues to output the driving signal.

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a shift temporary storage circuit according to an embodiment of the present invention. As shown in FIG. 1, the shift temporary storage circuit 10 has a multi-stage shift register, and each stage The shift register is configured to output a driving signal, such as a gate driving signal for driving the pixel circuit or other suitable driving signal, which is not limited in this embodiment. In one embodiment, each stage of the shift register circuit 10 shifts the drive signal outputted by the shift register of the previous stage as the drive signal of the current stage, or may be the previous two or the first four stages. The driving signal outputted by the shift register is used as the driving signal of the current stage, which is not limited in this embodiment. In addition, in another embodiment, the shift register circuit 10 is applied to, for example, an in-cell display touch device, that is, the in-cell display touch device switches between time-division and continuous execution in one picture period. Display mode and touch mode.

In a specific example, in one picture period, the in-line display touch device first outputs a driving signal from the first 20 stages of the shift register to drive the first 20 columns of pixel units. Then, the in-cell display touch device switches to the touch mode to sense the touch action on the panel. After the touch mode performs a preset time or other suitable timing, the in-line display touch device switches to the display mode, and the shift register of the 21st to 40th stages outputs a drive signal to drive the drive. 20 columns of pixel units, followed by switching of the inline display driver and so on.

In this specific example, each stage of the shift register of the in-cell display touch device may be the same circuit, or a part of the shift register may be different from the circuits of other shift registers. For example, when the in-cell display touch device is suspended in the 21st and 41st stage shift registers to switch the touch mode, the circuits of the 21st, 41st stage shift register and other first to The circuits of the 20th and 22nd to 40th shift registers are different. A shift register which can be exemplified in the prior art, which is used in the shift register of each stage of the shift register circuit 10 or in a shift register of a partial stage, this embodiment No restrictions.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a circuit of a shift register according to an embodiment of the present invention. As shown in FIG. 2, the shift register 20 has a driving module 21 and a recharging module 22 The pull-up module 23 and the main pull-down module 24 are provided. The driving module 21 is electrically connected to the first node N1 at least, and provides a working signal to the first node N1 according to the first driving signal. The recharging module 23 is electrically connected to the first node N1 and the second node N2. The recharging module 23 has a power storage unit 221, a first switch 222, and a control unit 223. The power storage unit is, for example, a capacitor, and one end is electrically connected to the first node N1, and the other end is electrically connected to the third node N3. The first switch 222 has a control end, a first end and a second end. The control end of the first switch 222 is electrically connected to the third node N3. The first end of the first switch 222 is electrically connected to the control unit 223. The first switch 222 The second end is electrically connected to the second node N2. The control unit 223 is electrically connected to the first indication signal end, the control unit 223 provides a recharge signal to the first switch 222, and adjusts the voltage of the third node N3 according to the voltage of the first node N1. The first switch 222 provides a recharge signal to the second node N2 according to the voltage of the third node N3. The pull-up module 23 is configured to turn on the first clock signal terminal CK and the output node out according to the voltage of the second node N2. The main pull-down module 24 is configured to turn on the output node out and the first reference voltage terminal VSS according to the voltage of the second clock signal terminal XCK.

Referring to FIG. 3A, FIG. 3A is a schematic circuit diagram of a shift register according to a first embodiment of the present invention. As shown in FIG. 3A, the shift register 30 has a driving module 31 and is recharged. The module 32, the pull-up module 33, the main pull-down module 34, the pull-down control module 35, the auxiliary pull-down module 36, the first pull-down module 37 and the second pull-down module 38. The driving module 31 is electrically connected to the first node N1 and the second node N2, and has a first driving unit 311 and a second driving unit 312. The first driving unit 311 has a switch 311a and a switch 311b, and the second driving unit 312 has a switch. 312a and switch 312b.

The first end of the switch 311a is electrically connected to the first selection signal terminal U2D, the second end of the switch 311a is electrically connected to the first node N1, and the control end of the switch 311a is electrically connected to the output node of the previous stage shift register. The switch 311a turns on the first selection signal terminal U2D and the first node N1 according to the driving signal G(n-1) outputted by the previous stage shift register. The first end of the switch 311b is electrically connected to the second selection signal terminal D2U, the second end of the switch 311b is electrically connected to the first node N1, and the control end of the switch 311b is electrically connected to the output node of the next stage shift register. The switch 311b turns on the second selection signal terminal D2U and the first node N1 according to the driving signal G(n+1) outputted by the next-stage shift register.

The first selection signal terminal U2D and the second selection signal terminal D2U respectively provide a first selection signal and a second selection signal. The first selection signal and the second selection signal are respectively at different voltage levels, for example, the voltage level of the first selection signal. It is quasi-high voltage, and the voltage level of the second selection signal is low voltage. In this embodiment, when the voltage level of the driving signal G(n-1) causes the switch 311a to be turned on, the first selection signal is supplied to the first node N1 as the working signal of the shift register 30. When the voltage level of the driving signal G(n+1) causes the switch 311b to be turned on, the second selection signal is supplied to the first node N1. In one embodiment, when the second selection signal is supplied to the first node N1, that is, the voltage of the first node N1 is reset, so that the voltage of the first node N1 is pulled down to the low voltage level.

Similarly, the switch 312a and the switch 312b are substantially the same as the switch 311a and the switch 311b, respectively, but the switch 312a and the second end of the switch 312b are electrically connected to the second node N2. When the voltage level of the driving signal G(n-1) causes the switch 312a to be turned on, the first selection signal is supplied to the second node N2 as the working signal of the shift register 30. When the voltage level of the driving signal G(n+1) turns on the switch 312b, the second selection signal is supplied to the second node N2, so that the voltage level of the second node N2 is substantially equal to the voltage level of the second selection signal. quasi. In other words, the driving module 31 causes the first node N1 and the second node N2 to be provided with a working signal according to the driving signal G(n-1).

The recharging module 32 is electrically connected to the first node N1 and the second node N2. The recharging module 32 has a power storage unit 321, a first switch 322, and a second switch 323. One end of the power storage unit is electrically connected to the first node N1, and the other end is electrically connected to the third node N3. The first switch 322 has a control end, a first end and a second end. The control end and the first end of the first switch 322 are electrically connected to the third node N3, and the second end of the first switch 322 is electrically connected to the second node N2. . The second switch 323 is, for example, the control unit 223 described in the previous embodiment. The second switch 323 has a control end, a first end and a second end. The first end of the second switch 323 is electrically connected to the first indication signal end TP, and the second end of the second switch 323 is electrically connected to the third node N3. The control end of the second switch 323 is electrically connected to the first node. The second switch 323 turns on the first indication signal terminal TP and the third node N3 according to the voltage of the first node N1 to provide a recharging signal to the first switch 322. The first end of the first switch 322 and the control end are connected to form a diode connection. The first switch 322 is turned on when the voltage of the third node N3 is greater than the cut-in voltage of the first switch 322 to provide the voltage of the third node N3 to the second node N2.

The pull-up module 33 has a control end, a first end and a second end. The first end of the pull-up module 33 is electrically connected to the first clock signal end CK, the second end of the pull-up module 33 is electrically connected to the output node out, and the control end of the pull-up module 33 is electrically connected to the second node. N2. The pull-up module 33 turns on the first clock signal terminal CK and the output node out according to the voltage of the second node N2 to provide the first clock signal on the first clock signal terminal CK to the output node out, so that the output The node out outputs the drive signal G(n) of the shift register 30 of the present stage.

The main pull-down module 34 is, for example, a transistor switch having a first end, a second end, and a control end. The first end of the main pull-down module 34 is electrically connected to the output node out, the second end of the main pull-down module 34 is electrically connected to the first reference voltage end VSS, and the control end of the main pull-down module 34 is electrically connected to the second clock. Signal terminal XCK. The main pull-down module 34 turns on the output node out and the first reference voltage terminal VSS according to the voltage on the second clock signal terminal XCK to provide the voltage level of the first reference voltage terminal VSS to the output node out.

The pull-down control module 35 has a capacitor 351 and a switch 352. One end of the capacitor 351 is electrically connected to the first clock signal terminal CK, and the other end is electrically connected to the switch 352. The first end of the switch 352 is electrically connected to the capacitor 351, the second end of the switch 352 is electrically connected to the first reference voltage terminal VSS, and the control end of the switch 352 is electrically connected to the second node N2. For convenience of display, the control terminal of the switch 352 in the figure is represented by the received signal Q(n). In fact, the signal Q(n) refers to the voltage of the second node N2. The switch 352 is turned on according to the voltage of the second node N2. The pull-down control module 35 outputs the pull-down control signal P(n) according to the voltage of the second node N2 and the voltage of the first clock signal terminal CK.

The auxiliary pull-down module 36 has a switch 361 and a switch 362. The first end of the switch 361 is electrically connected to the second node N2, the second end of the switch 361 is electrically connected to the first reference voltage terminal VSS, and the control end of the switch 361 is electrically connected to the pull-down control module 35, according to the pull-down control module. The output pull-down control signal P(n) of the 35 turns on the second node N2 and the first reference voltage terminal VSS. The first end of the switch 362 is electrically connected to the output node out, the second end of the switch 362 is electrically connected to the first reference voltage terminal VSS, and the control end of the switch 362 is electrically connected to the pull-down control module 35, according to the pull-down control module 35. The output pull-down control signal P(n) turns on the output node out and the first reference voltage terminal VSS.

The first pull-down module 37 is, for example, a transistor switch having a first end, a second end, and a control end. The first end of the first pull-down module 37 is electrically connected to the second node N2, and the second end of the first pull-down module 37 is electrically connected to the first reference voltage terminal VSS, and the first pull-down module 37 controls the electrical end. The first control signal end Reset is connected to turn on the second node N2 and the first reference voltage terminal VSS according to the first control signal of the first control signal end Reset. The second pull-down module 38 is, for example, a transistor switch having a first end, a second end, and a control end. The first end of the second pull-down module 38 is electrically connected to the first node N1, the second end of the second pull-down module 38 is electrically connected to the second node N2, and the control end of the second pull-down module 38 is electrically connected to the pull-down control. The module 35 turns on the first node N1 and the second node N2 according to the pull-down control signal P(n) output by the pull-down control module 35.

Next, please refer to FIG. 3B, which is a voltage timing diagram of the shift register according to the embodiment of FIG. 3A. As shown in FIG. 3B, at the time point t1, the output node of the previous stage shift register outputs the driving signal G(n-1), and the voltage of the second clock signal terminal XCK is at the high voltage level, and the switch 311a The switch 312a is turned on, and the first selection signal of the first selection signal terminal U2D is provided to the first node N1 and the second node N2. The second switch 323 is turned on, and the first indication signal of the first indication signal terminal TP is provided to the third node N3. The power storage unit 321 is charged with the voltage of the first node N1, and the voltage of the first node N1 is boosted to the voltage level of the first selection signal minus the threshold voltage of the switch 311a. Moreover, the pull-up module 33 is turned on, and the first clock signal on the first clock signal terminal CK is supplied to the output node out. The capacitor cap is charged with the voltage of the second node N2, and the voltage of the second node N2 is boosted to the voltage level of the first selection signal minus the threshold voltage of the switch 312a.

At time t2, the voltage of the first control signal terminal rises, the first pull-down module 37 turns on the second node N2 and the first reference voltage terminal VSS, the voltage of the second node N2 decreases, and the pull-up module 33 does not. Turn on. The period in which the voltage of the first control signal end rises rises between the time point t2 and the time point t3, for example, a stage in which the touch control device switches to execute the touch mode.

At time t3, the voltage of the first control signal terminal Reset decreases, and the voltage of the first indicator signal terminal TP rises. The voltage on the first indication signal terminal TP is, for example, a signal at the end of the touch mode, and can also be used as a recharge signal of the shift register 30, so that the shift register 30 can be based on the first indication signal terminal TP. The voltage continues to operate. When the voltage on the first indicator signal terminal TP rises, the voltage of the third node N3 is boosted, and the power storage unit 321 couples the first node N1 according to the voltage of the third node N3, so that the voltage of the first node N1 rises. . At this time, the first switch 322 is turned on, the voltage of the third node N3 is turned on to the second node N2, and the pull-up module 33 is turned on according to the voltage of the second node N2.

At time t4, the voltage of the first clock signal terminal CK rises, the output node out is supplied with the voltage of the first clock signal terminal CK, and the voltage level of the second node N2 is made more by the coupling of the capacitance cap. To improve, the output node out outputs a drive signal G(n).

At time t5, the voltage of the first clock signal terminal CK decreases, the voltage of the second clock signal terminal XCK rises, and the next stage shift register is also driven by the driving signal G output by the shift register 30 ( n), output drive signal G (n + 1). At this time, the main pull-down module 34 turns on the second node N2 and the first reference voltage terminal VSS, so that the voltage of the second node N2 falls, and the switch 352 is turned off. The switch 311b of the first driving unit 311 and the switch 312b of the second driving unit 312 are turned on to provide the voltage of the second selection signal terminal D2U to the first node N1 and the second node N2 to reset the first node N1 and the second node. The voltage at node N2.

At time t6, the voltage of the first clock signal terminal CK rises, and the pull-down control module 35 outputs the pull-down control signal P(n). The switch 361 and the switch 362 in the auxiliary pull-down module 36 turn on the second node N2 and the first reference voltage terminal VSS according to the pull-down control switch P(n), and turn on the output node out and the first reference voltage terminal VSS. The second pull-down module 38 also turns on the first node N1 and the second node N2 according to the pull-down control switch P(n), so that the voltage of the first node N1, the second node N2 and the output node out and the first reference voltage terminal VSS The voltages are essentially the same.

In this embodiment, in the touch mode phase between the time point t2 and the time point t3, the first pull-down module 37 is turned on to lower the voltage of the second node N2, so that the voltage of the control terminal of the pull-up module 33 is released. At the low voltage level, the control terminal of the pull-up module 33 is prevented from being at a high voltage level for a long time, and the problem that the driving voltage is lowered due to the rise of the threshold voltage of the pull-up module 33 is avoided.

4A, FIG. 4A is a schematic circuit diagram of a shift register according to a second embodiment of the present invention. As shown in FIG. 4A, the shift register 40 has a driving module 41. The recharging module 42 , the pull-up module 43 , the main pull-down module 44 , the pull-down control module 45 , the auxiliary pull-down module 46 , and the first pull-down module 47 . The driving module 41 is electrically connected to the first node N1 and the second node N2, and has a first driving unit 411 and a second driving unit 412. The first driving unit 411 has a switch 411a and a switch 411b, and the second driving unit 412 has a switch. 412a and switch 412b.

The first end of the switch 411a is electrically connected to the second reference voltage terminal VDD, the second end of the switch 411a is electrically connected to the first node N1, and the control end of the switch 411a is electrically connected to the output node of the previous stage shift register. The switch 411a turns on the second reference voltage terminal VDD and the first node N1 according to the driving signal G(n-1) outputted by the shift register of the previous stage. The first end of the switch 411b is electrically connected to the first control signal end Reset, the second end of the switch 411b is electrically connected to the first node N1, and the control end of the switch 411b is electrically connected to the first clock signal end CK. The switch 411b turns on the first control signal end Reset and the first node N1 according to the first clock signal output by the first clock signal terminal CK.

The first end of the switch 412a is electrically connected to the second reference voltage terminal VDD, the second end of the switch 412a is electrically connected to the second node N2, and the control end of the switch 412a is electrically connected to the output node of the previous stage shift register. The switch 412a turns on the second reference voltage terminal VDD and the second node N2 according to the driving signal G(n-1) outputted by the shift register of the previous stage. The first end of the switch 412b is electrically connected to the first reference voltage terminal VSS, the second end of the switch 412b is electrically connected to the second node N2, and the control end of the switch 412b is electrically connected to the output node of the next-stage shift register. The switch 412b turns on the first control signal end Reset and the second node N2 according to the driving signal G(n+1) outputted by the next stage shift register.

Recharging module 42, pull-up module 43, main pull-down module 44, pull-down control module 45, auxiliary pull-down module 46 and first pull-down module 47 and the recharging module 32 of the previous embodiment, The pull module 33, the main pull-down module 34, the pull-down control module 35, the auxiliary pull-down module 36, and the first pull-down module 37 are substantially the same and will not be described again.

Next, please refer to FIG. 4B. FIG. 4B is a voltage timing diagram of the shift register according to the embodiment of FIG. 4A. As shown in FIG. 4B, at the time point t1, the output node of the previous stage shift register outputs the driving signal G(n-1), and the voltage of the second clock signal terminal XCK is at the high voltage level, and the switch 411a The switch 412a is turned on, and the voltage of the second reference voltage terminal VDD is supplied to the first node N1 and the second node N2. At this time, the second switch 423 causes the third node N3 to be turned on with the first indication signal terminal TP, the power storage unit 421 is charged with the voltage of the first node N1, and the voltage of the first node N1 is boosted to the second reference voltage terminal VDD. The voltage is subtracted from the threshold voltage of the switch 411a. Moreover, the pull-up module 43 is turned on so that the output node out is turned on with the first clock signal terminal CK, the capacitor cap is charged by the voltage of the second node N2, and the voltage of the second node N2 is boosted to the second reference voltage terminal VDD. The voltage is subtracted from the threshold voltage of switch 412a.

At time t2, the voltage of the first control signal end rises, the first pull-down module 47 causes the second node N2 to be turned on with the first reference voltage terminal VSS, and the voltage of the second node N2 falls, and the pull-up module 43 The non-conducting is used to reduce the voltage stress of the pull-up module 43 on the control end when the output node out and the first clock signal end CK are not turned on.

At time t3, the voltage of the first control signal terminal Reset decreases, the voltage of the first indicator signal terminal TP rises, the voltage of the third node N3 is boosted, and the power storage unit 421 is coupled first according to the voltage of the third node N3. The node N1 causes the voltage of the first node N1 to rise more. At this time, the first switch 422 is turned on, the voltage of the third node N3 is turned on to the second node N2, and the pull-up module 43 is turned on according to the voltage of the second node N2.

At time t4, the voltage of the first clock signal terminal CK rises, the output node out is supplied with the voltage of the first clock signal terminal CK, and the voltage level of the second node N2 is made more by the coupling of the capacitance cap. To improve, the output node out outputs a drive signal G(n). When the voltage of the first clock signal terminal CK rises, the switch 411b in the first driving unit 411 is turned on, and the voltage of the first node N1 is pulled down to the voltage level of the first control signal terminal Reset.

At time t5, the voltage of the first clock signal terminal CK decreases, the voltage of the second clock signal terminal XCK rises, and the next stage shift register also depends on the driving signal G output by the shift register 40 ( n), output drive signal G (n + 1). At this time, the main pull-down module 44 turns on the second node N2 and the first reference voltage terminal VSS, so that the voltage of the second node N2 falls, and the switch 452 is turned off. The switch 412b in the second driving unit 412 turns on the first reference voltage terminal VSS and the second node according to the driving signal G(n+1), so that the voltage of the second node N2 is pulled down to the voltage level of the first reference voltage terminal VSS. .

At time t6, the voltage of the first clock signal terminal CK rises, and the pull-down control module 45 outputs the pull-down control signal P(n). The switch 461 and the switch 462 in the auxiliary pull-down module 46 turn on the second node N2 and the first reference voltage terminal VSS according to the pull-down control switch P(n), and turn on the output node out and the first reference voltage terminal VSS, so that the second The voltages of the node N2 and the output node out are pulled down to the voltage level of the first reference voltage terminal VSS. In this embodiment, pulling down the voltage of the second node N2 again at the time point t6 can prevent the voltage of the second node N2 from being increased by the voltage of other circuit nodes. In other embodiments, the setting of the switch 461 in the auxiliary pull-down module 46 may also be omitted, which is not limited in this embodiment.

Referring to FIG. 5A, FIG. 5A is a schematic circuit diagram of a shift register according to a third embodiment of the present invention. As shown in FIG. 5A, the shift register 50 has a driving module 51 and is recharged. The module 52, the pull-up module 53, the main pull-down module 54, the pull-down control module 55, the auxiliary pull-down module 56, the first pull-down module 57 and the second pull-down module 58. The driving module 51 is electrically connected to the first node N1 and has a switch 51a and a switch 51b.

The first end of the switch 51a is electrically connected to the first selection signal terminal U2D, the second end of the switch 51a is electrically connected to the first node N1, and the control end of the switch 51a is electrically connected to the output node of the previous stage shift register. The switch 51a turns on the first selection signal terminal U2D and the first node N1 according to the driving signal G(n-1) outputted by the previous stage shift register. The first end of the switch 51b is electrically connected to the second selection signal terminal D2U, the second end of the switch 51b is electrically connected to the first node N1, and the control end of the switch 51b is electrically connected to the output node of the next stage shift register. The switch 51b turns on the second selection signal terminal D2U and the first node N1 according to the driving signal G(n+1) outputted by the shift register of the next stage.

The first selection signal terminal U2D and the second selection signal terminal D2U respectively provide a first selection signal and a second selection signal. The first selection signal and the second selection signal are respectively at different voltage levels, for example, the voltage level of the first selection signal. It is quasi-high voltage, and the voltage level of the second selection signal is low voltage. In this embodiment, when the voltage level of the driving signal G(n-1) causes the switch 51a to be turned on, the first selection signal is supplied to the first node N1 as the working signal of the shift register 50. When the voltage level of the driving signal G(n+1) causes the switch 51b to be turned on, the second selection signal is supplied to the first node N1.

The recharging module 52, the pull-up module 53, the main pull-down module 54, the pull-down control module 55, the auxiliary pull-down module 56, the first pull-down module 57, and the second pull-down module 58 are the same as those of the previous embodiment. The recharging module 32, the pull-up module 33, the main pull-down module 34, the pull-down control module 35, the auxiliary pull-down module 36, the first pull-down module 37, and the second pull-down module 38 are substantially the same, no longer Repeat them.

Next, please refer to FIG. 5B, which is a voltage timing diagram of the shift register according to the embodiment of FIG. 5A. As shown in FIG. 5B, at the time point t1, the output node of the previous stage shift register outputs the driving signal G(n-1), and the voltage of the second clock signal terminal XCK is at the high voltage level, and the switch 51a Turning on, the first selection signal of the first selection signal terminal U2D is provided to the first node N1. At this time, the second switch 523 turns on the third node N3 and the first indication signal terminal TP, the power storage unit 521 is charged by the voltage of the first node N1, and the voltage of the first node N1 is raised to the voltage level of the first selection signal. The threshold voltage of the switch 51a is subtracted.

At time t2, the voltage of the first indicator signal terminal TP rises, the voltage of the third node N3 is boosted, and the power storage unit 521 couples the first node N1 according to the voltage of the third node N3, so that the voltage of the first node N1 is More rising. At this time, the first switch 522 is turned on, the voltage of the third node N3 is turned on to the second node N2, and the pull-up module 53 is turned on according to the voltage of the second node N2. At time t3, the voltage of the first clock signal terminal CK rises, the output node out is supplied with the voltage of the first clock signal terminal CK, and the voltage level of the second node N2 is made more by the coupling of the capacitance cap. To improve, the output node out outputs a drive signal G(n).

At time t4, the voltage of the first clock signal terminal CK decreases, the voltage of the second clock signal terminal XCK rises, and the next stage shift register also depends on the driving signal G output by the shift register 50 ( n), output drive signal G (n + 1). At this time, the main pull-down module 54 turns on the second node N2 and the first reference voltage terminal VSS, so that the voltage of the second node N2 falls, and the switch 552 is turned off. The switch 51b of the first driving unit 511 and the switch 512b of the second driving unit 512 are turned on, and the voltage of the second selection signal terminal D2U is supplied to the first node N1 and the second node N2 to reset the first node N1 and the second node. The voltage at node N2.

At time t5, the voltage of the first clock signal terminal CK rises, and the pull-down control module 55 outputs the pull-down control signal P(n). The switch 561 and the switch 562 in the auxiliary pull-down module 56 turn on the second node N2 and the first reference voltage terminal VSS according to the pull-down control switch P(n), and turn on the output node out and the first reference voltage terminal VSS. The second pull-down module 58 also turns on the first node N1 and the second node N2 according to the pull-down control switch P(n), so that the voltage of the first node N1, the second node N2 and the output node out and the first reference voltage terminal VSS The voltages are essentially the same.

In the embodiment, the shift register 50 does not electrically connect the driving module 51 to the second node N2, thereby practically shifting the temporary storage circuit in the display mode of the display touch device. The shift register in the middle sequentially outputs the driving signal until the shift register 50 of the current stage receives the driving signal G(n-1) outputted by the shift register of the previous stage, and the shift register is temporarily stored. The device 50 will not output the driving signal G(n) first, and the display touch device switches to execute the touch mode until the touch mode of the touch device ends, and when the display mode is switched to the display mode, the shift register 50 of the present stage Then, according to the voltage on the first indication signal terminal TP, the output driving signal G(n) is continuously executed.

In other words, the shift register 50 shown in FIG. 5A is matched with a processor, a timing controller or another chip of the display touch device, and is disposed at a specific level in the shift register circuit, and the shift register is temporarily stored. The remaining stages other than the specific stage in the circuit are configured with a shift register such as that of FIG. 3A, FIG. 4A or other embodiments, which is not limited in this embodiment.

Referring to FIG. 6 , FIG. 6 is a schematic circuit diagram of a shift register according to a fourth embodiment of the present invention. As shown in FIG. 6 , the shift register 60 has a driving module 61 and is recharged. The module 62, the pull-up module 63, the main pull-down module 64, the pull-down control module 65, the auxiliary pull-down module 66, the first pull-down module 67 and the second pull-down module 68. The driving module 61 is electrically connected to the first node N1 and the second node N2, and has a first driving unit 611 and a second driving unit 612. The second driving unit 612 has a switch 612a and a switch 612b.

The first driving unit 611 is, for example, a transistor switch having a first end, a second end, and a control end. The first end of the first driving unit 611 is electrically connected to the second reference voltage terminal VDD, and the second end of the first driving unit 611 is electrically connected to the first node N1, and the control end of the first driving unit 611 is electrically connected to the first stage. The output node of the bit buffer. The first driving unit 611 turns on the second reference voltage terminal VDD and the first node N1 according to the driving signal G(n-1) outputted by the shift register of the previous stage.

In the second driving unit 612, the first end of the switch 612a is electrically connected to the first selection signal terminal U2D, the second end of the switch 612a is electrically connected to the second node N2, and the control end of the switch 612a is electrically connected to the previous stage. The output node of the scratchpad. The switch 612a turns on the first selection signal terminal U2D and the second node N2 according to the driving signal G(n-1) outputted by the previous stage shift register. The first end of the switch 612b is electrically connected to the second selection signal terminal D2U, the second end of the switch 612b is electrically connected to the second node N2, and the control end of the switch 612b is electrically connected to the output node of the next stage shift register. The switch 612b turns on the second selection signal terminal D2U and the second node N2 according to the driving signal G(n+1) outputted by the next-stage shift register.

When the voltage level of the driving signal G(n-1) causes the first driving unit 611 to be turned on, the first reference voltage is supplied to the first node N1 as the working signal of the shift register 60. Furthermore, when the voltage level of the driving signal G(n-1) causes the switch 612a to be turned on, the first selection signal is supplied to the second node N2. When the voltage level of the driving signal G(n+1) turns on the switch 612a, the second selection signal is supplied to the second node N2, so that the voltage of the second node N2 is pulled down to the low voltage level.

Recharging module 62, pull-up module 63, main pull-down module 64, pull-down control module 65, auxiliary pull-down module 66 and first pull-down module 67 and the recharging module 32 of the foregoing embodiment, pull-up The module 33, the main pull-down module 34, the pull-down control module 35, the auxiliary pull-down module 36, and the first pull-down module 37 are substantially the same and will not be described again.

In addition to the foregoing embodiment, the second pull-down module 68 has a switch 681 and a switch 682. The first end of the switch 681 is electrically connected to the first node N1, and the second end of the switch 681 is electrically connected to the switch 682. The control end of the switch 681 is electrically connected to the first clock signal terminal CK. The first end of the switch 682 is electrically connected to the switch 681, the second end of the switch 682 is electrically connected to the first reference voltage terminal VSS, and the control end of the switch 682 is electrically connected to the first clock signal terminal CK. The second pull-down module 68 is configured to turn on the first node N1 and the first reference voltage terminal VSS according to the voltage of the first clock signal terminal CK.

The voltage timing diagram of shift register 60 is substantially the same as the voltage timing diagram of shift register 40. Those of ordinary skill in the art should understand the operation of shift register 60 from FIG. 4B. This will not be repeated here.

Referring to FIG. 7A, FIG. 7A is a schematic circuit diagram of a shift register according to a fifth embodiment of the present invention. As shown in FIG. 7A, the shift register 70 has a driving module 71 and is recharged. The module 72, the pull-up module 73, the main pull-down module 74, the pull-down control module 75, the auxiliary pull-down module 76, the first pull-down module 77 and the second pull-down module 78. The driving module 71 is, for example, a transistor switch having a first end, a second end, and a control end. The first end of the driving module 71 is electrically connected to the second reference voltage terminal VDD, and the second end of the driving module 71 is electrically connected to the first node N1, and the control end of the driving module 71 is electrically connected to the previous stage shifting temporary storage. The output node of the device. The driving module 71 turns on the second reference voltage terminal VDD and the first node N1 according to the driving signal G(n-1) outputted by the shift register of the previous stage.

The recharging module 72, the pull-up module 73, the main pull-down module 74, the pull-down control module 75, and the auxiliary pull-down module 76 are the recharging module 32, the pull-up module 33, and the main pull-down module of the foregoing embodiment. 34. The pull-down control module 35 and the auxiliary pull-down module 36 are substantially the same and will not be described again. In addition, the first end of the first pull-down module 77 is electrically connected to the second node N2, and the second end of the first pull-down module 77 is electrically connected to the first reference voltage terminal VSS. The control terminal of a pull-down module 77 is electrically connected to the output node of the next-stage shift register. The first pull-down module 77 turns on the second node N2 and the first reference voltage terminal VSS according to the driving signal G(n+1) outputted by the shift register of the next stage.

The second pull-down module 78 has a switch 781 and a switch 782. The first end of the switch 781 is electrically connected to the first node N1, the second end of the switch 781 is electrically connected to the switch 782, and the control end of the switch 781 is electrically connected to the first clock signal terminal CK. The first end of the switch 782 is electrically connected to the switch 781. The second end of the switch 782 is electrically connected to the first reference voltage terminal VSS, and the control end of the switch 782 is electrically connected to the first clock signal terminal CK. The second pull-down module 78 is configured to turn on the first node N1 and the first reference voltage terminal VSS according to the voltage of the first clock signal terminal CK.

Next, please refer to FIG. 7B, which is a voltage timing diagram of the shift register according to the embodiment of FIG. 7A. As shown in FIG. 7B, at time t1, the output node of the previous stage shift register outputs the driving signal G(n-1), and the voltage of the second clock signal terminal XCK is at the high voltage level, the driving mode. The group 71 is turned on, and the voltage of the second reference voltage terminal VDD is supplied to the first node N1. At this time, the second switch 723 turns on the third node N3 and the first indication signal terminal TP, the third node N3 is provided with the first indication signal of the first indication signal terminal TP, and the storage unit 721 is charged by the voltage of the first node N1. The voltage of the first node N1 is boosted to the voltage level of the first selection signal minus the threshold voltage of the driving module 71.

At time t2, the voltage of the first indicator signal terminal TP rises, the voltage of the third node N3 is boosted, and the power storage unit 721 couples the first node N1 according to the voltage of the third node N3, so that the voltage of the first node N1 is More rising. At this time, the first switch 722 is turned on, the voltage of the third node N3 is turned on to the second node N2, and the pull-up module 73 is turned on according to the voltage of the second node N2. At time t3, the voltage of the first clock signal terminal CK rises, the output node out is supplied with the voltage of the first clock signal terminal CK, and the voltage level of the second node N2 is made more by the coupling of the capacitance cap. To improve, the output node out outputs a drive signal G(n).

When the voltage of the first clock signal terminal CK rises, the switch 781 and the switch 782 in the second pull-down module 78 are turned on, and the first node N1 is supplied with the voltage of the first reference voltage terminal VSS. Next, at time t4, the voltage of the first clock signal terminal CK decreases, the voltage of the second clock signal terminal XCK rises, and the next stage shift register is also driven by the driving signal output by the shift register 70. G(n), output drive signal G(n+1). At this time, the main pull-down module 74 and the first pull-down module 77 respectively turn on the second node N2 and the first reference voltage terminal VSS according to the voltage of the second clock signal terminal XCK and the driving signal G(n+1). The voltage of the second node N2 is lowered.

At time t5, the voltage of the first clock signal terminal CK rises, and the pull-down control module 75 outputs the pull-down control signal P(n). The switch 761 and the switch 762 in the auxiliary pull-down module 76 turn on the second node N2 and the first reference voltage terminal VSS according to the pull-down control switch P(n), and turn on the output node out and the first reference voltage terminal VSS, so that the first The voltages of the node N1, the second node N2, and the output node out are substantially the same as the voltages of the first reference voltage terminal VSS.

In this embodiment, the driving module 71 of the shift register 70 is not electrically connected to the second node N2. In practice, for example, in the display mode of the display touch device, when the shift register in the shift register circuit sequentially outputs the drive signal until the shift register 70 of the present stage receives the shift of the previous stage. When the drive signal G(n-1) is output by the register, the shift register 70 of the stage suspends the output of the drive signal G(n), and the display touch device is switched to the touch mode until the end of the touch mode. . The stage shift register 70 continues to execute the output drive signal G(n) when the voltage on the first indication signal terminal TP rises.

In other words, the shift register 50 shown in FIG. 5A is configured to cooperate with a processor, a timing controller or another wafer of the display touch device, and is disposed at a specific level in the shift register circuit, and is shifted. The remaining stages other than the specific stage in the temporary storage circuit are configured with a shift register such as that of FIG. 3A, FIG. 4A, FIG. 6, or other embodiments, which is not limited in this embodiment.

Referring to FIG. 8A, FIG. 8A is a schematic circuit diagram of a shift register according to a sixth embodiment of the present invention. As shown in FIG. 8A, the shift register 80 has a driving module 81 and is recharged. The module 82, the pull-up module 83, the main pull-down module 84, the pull-down control module 85, the auxiliary pull-down module 86 and the second pull-down module 87, wherein the driving module 81, the pull-up module 83, and the main pull-down module The group 84, the pull-down control module 85 and the auxiliary pull-down module 86 are substantially the same as the drive module 31, the pull-up module 33, the main pull-down module 34, the pull-down control module 35 and the auxiliary pull-down module 36 of the above-mentioned lost example. The same, no longer repeat them.

Different from the foregoing embodiment, the recharging module 82 has a power storage unit 821, a first switch 822, and a control unit 823. The control unit has a second switch 823a and a third switch 823b. One end of the power storage unit is electrically connected to the first node N1, and the other end is electrically connected to the third node N3. The first switch 822 has a control end, a first end and a second end. The control end of the first switch 822 is electrically connected to the third node N3. The first end of the first switch 822 is electrically connected to the second switch 823a. The first switch The second end of the 822 is electrically connected to the second node N2. The second switch 823a has a control end, a first end and a second end. The first end of the second switch 823a is electrically connected to the first indication signal end TP, and the second end of the second switch 823a is electrically connected to the first switch 822. The control end of the second switch 823a is electrically connected to the first node N1. The third switch 823b has a control end, a first end and a second end. The first end of the third switch 823b is electrically connected to the second indication signal terminal Bi, and the second end of the third switch 823b is electrically connected to the third node N3. The control end of the third switch 823b is electrically connected to the first node N1.

The second switch 823a is turned on according to the voltage of the first node N1, and provides the second indication signal of the second indication signal terminal TP to the first switch 822, and provides the recharging signal to the first switch by the second indication signal. The third switch 823b turns on the second indication signal terminal Bi and the third node N3 according to the voltage of the first node N1, and adjusts the voltage of the third node N3 by the voltage of the second indication signal terminal Bi. When the second switch 823a and the third switch 823b are turned on according to the voltage of the first node N1, and the first switch 822 is turned on according to the voltage of the second indication signal terminal Bi, the first indication signal on the first indication signal terminal TP is provided. Go to the second node N2 to adjust the voltage of the second node N2.

The second pull-down module 87 is, for example, a transistor switch having a first end, a second end, and a control end. The first end of the second pull-down module 87 is electrically connected to the first node N1, the second end of the second pull-down module 87 is electrically connected to the first reference voltage terminal VSS, and the control end of the second pull-down module 87 is electrically connected. The pull-down control module 85 turns on the first node N1 and the first reference voltage terminal VSS according to the pull-down control signal P(n) outputted by the pull-down control module 85.

Next, please refer to FIG. 8B. FIG. 8B is a voltage timing diagram of the shift register according to the embodiment of FIG. 8A. As shown in FIG. 8B, at time t1, the output node of the previous stage shift register outputs the driving signal G(n-1), and the voltage of the second clock signal terminal XCK is at the high voltage level, and the switch 811a The switch 812a is turned on, and the first selection signal of the first selection signal terminal U2D is provided to the first node N1 and the second node N2. At this time, the second switch 823a and the third switch 823b are turned on, the third node N3 is supplied with the voltage of the second indication signal terminal Bi, and the first end of the first switch 822 is supplied with the voltage of the first indication signal terminal TP. The first switch 822 is not turned on, the power storage unit 821 is charged with the voltage of the first node N1, and the voltage of the first node N1 is boosted to the voltage level of the first selection signal minus the threshold voltage of the switch 811a. The pull-up module 83 turns on the output node out and the first clock signal terminal CK, the capacitor cap is charged by the voltage of the second node N2, and the voltage of the second node N2 is boosted to the voltage of the first selection signal minus the threshold of the switch 812a. Voltage.

At time t2, the voltage of the second indication signal terminal Bi rises, the first switch 822 is turned on, and the voltage of the first node N1 is coupled to the higher voltage level by the storage unit 821. The second switch 823a turns on the first indication signal terminal TP and the first end of the first switch 822, and the second node N2 is provided with the voltage of the first indication signal terminal TP. At this time, by the low voltage of the first indication signal terminal TP, the voltage of the second node N2 is discharged to the low voltage level, and the pull-up module 83 is not turned on.

At time t3, the voltage of the second indication signal terminal Bi decreases, the voltage of the third node decreases, the first switch 822 does not conduct, and the voltage of the first node N1 is not coupled by the storage unit 821, and is lowered to a lower level. Voltage level. At time t4, the voltage of the second indication signal terminal Bi rises, and the voltage of the first indication signal terminal TP rises. The third node N3 is supplied with the voltage of the second indication signal terminal Bi to raise the voltage level, the first switch 822 is turned on, and the voltage of the first node N1 is coupled to the higher voltage level by the storage unit 821. The second switch 823a turns on the first indication signal terminal TP and the first end of the first switch 822, and the second node N2 is provided with the voltage of the first indication signal terminal TP. At this time, by the high voltage of the first indication signal terminal TP, the voltage of the second node N2 is raised to a high voltage level, and the pull-up module 83 is turned on.

At time t5, the voltage of the first clock signal terminal CK rises, the output node out is supplied with the voltage of the first clock signal terminal CK, and the voltage of the second node N2 is boosted by the coupling of the capacitance cap, and the pull-up module 83 The first clock signal terminal CK and the output node out are turned on, so that the voltage of the output node out rises, and the shift register 80 outputs the driving signal G(n).

At time t6, the voltage of the first clock signal terminal CK decreases, the voltage of the second clock signal terminal XCK rises, and the next stage shift register is also driven by the driving signal G output by the shift register 80 ( n), output drive signal G (n + 1). At this time, the main pull-down module 84 turns on the second node N2 and the first reference voltage terminal VSS, so that the voltage of the second node N2 drops, and the switch 852 is turned off. The switch 811b of the first driving unit 811 and the switch 812b of the second driving unit 812 are turned on to provide the voltage of the second selection signal terminal D2U to the first node N1 and the second node N2, so that the first node N1 and the second node N2 The voltage drops.

At time t7, the voltage of the first clock signal terminal CK rises, and the pull-down control module 85 outputs the pull-down control signal P(n). The switch 861 and the switch 862 in the auxiliary pull-down module 86 turn on the second node N2 and the first reference voltage terminal VSS according to the pull-down control switch P(n), and turn on the output node out and the first reference voltage terminal VSS. The second pull-down module 87 also turns on the first node N1 and the first reference voltage terminal VSS according to the pull-down control switch P(n), so that the voltages of the first node N1, the second node N2, and the output node out are at the first reference voltage. The voltage at terminal VSS is reset.

In this embodiment, the stage shift register 80 does not output the drive signal G(n) by the voltages of the first indicator signal terminal TP and the second indicator signal terminal Bi. In practice, when the voltage of the second indication signal terminal Bi received by the shift register 80 of the present stage increases, and the first indication signal terminal TP decreases, that is, at the time point t3, the display device is displayed in the display mode. Switching to the touch mode until the time point t4, the touch mode of the display touch device ends, the voltages of the first indicator signal terminal TP and the second indicator signal terminal Bi rise, and the display touch device switches back to the display mode, by the level The shift register 80 continues to output the drive signal G(n).

In one embodiment, when the driving ability of the first switch 822, the second switch 823a, and the third switch 823b to lower the voltage of the second node N2 is higher than the driving capability for lowering the voltage of the second node N2, the first indicator signal end The time when the voltage of the TP and the second indicator signal terminal bi is the same as the high voltage, and the time length that the voltage of the first indication signal terminal TP is lower than the voltage of the second indication signal terminal Bi is high voltage can be designed. The first switch 822, the second switch 823a, and the third switch 823b cause the voltage of the second node N2 to rise for a longer period of time than the voltage for lowering the voltage of the second node N2.

In summary, the embodiment of the present invention provides a shift temporary storage circuit, wherein the working signal of the shift register of the current stage is stored in the first node by the recharging module until the display touch device switches to the display mode. And outputting the voltage stored in the first node to the second node, and providing a recharging signal to the first switch by using the voltage of the first indicator signal terminal or the second indicator signal terminal, so that the voltage of the second node is further In order to improve, the driving ability of the shift register to continue to output the driving signal is further improved. In addition, in the embodiment, when the touch device is switched to the touch mode, the voltage of the control terminal of the pull-up module is released to a low voltage level, and the length of the pull-up module is reduced. The time is affected by the bias stress, and there is a problem of switching aging, which causes a problem of a decrease in driving ability.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

10‧‧‧Shift register circuit
20, 30, 40, 50, 60, 70, 80‧‧‧ shift register
21, 31, 41, 51, 61, 71, 81‧‧‧ drive modules
311, 411, 611, 811‧‧‧ first drive unit
311a, 311b, 312a, 312b‧‧ ‧ switch
411a, 411b, 412a, 412b‧‧‧ switch
51a, 51b‧‧ ‧ switch
612a, 612b‧‧ ‧ switch
811a, 811b, 812a, 812b‧‧‧ switch
312, 412, 612, 811‧‧‧ second drive unit
22, 32, 42, 52, 62, 72, 82‧‧‧ Recharge Module
221, 321, 421, 521, 621, 721, 821‧‧‧ power storage units
222, 322, 422, 522, 622, 722, 822‧‧‧ first switch
223, 823‧‧‧Control unit
323, 423, 523, 623, 723, 823a‧‧‧ second switch
823b‧‧‧third switch
23, 33, 43, 53, 63, 73, 83‧‧‧ pull-up modules
24, 34, 44, 54, 64, 74, 84‧‧‧ main pull-down modules
35, 45, 55, 65, 75, 85‧‧‧ pull-down control module
351, 451, 551, 651, 751, 851‧‧ ‧ capacitor
352, 452, 552, 652, 752, 852‧ ‧ switches
36, 46, 56, 66, 76, 86‧‧‧Auxiliary pull-down modules
361, 461, 561, 661, 761, 861‧‧ ‧ switch
362, 462, 562, 662, 762, 862‧‧ ‧ switch
37, 47, 57, 67, 77‧‧‧ first pull-down module
38, 58, 68, 78, 87‧‧‧ second pull-down module
781, 782‧‧ ‧ switch
CK‧‧‧ first clock signal end
XCK‧‧‧second clock signal end
VSS‧‧‧First reference voltage terminal
VDD‧‧‧first reference voltage terminal
U2D‧‧‧First choice signal end
D2U‧‧‧Second selection signal end
TP‧‧‧first indication signal end
Bi‧‧‧second indication signal end
Cap‧‧‧ Capacitance
Out‧‧‧output node
N1‧‧‧ first node
N2‧‧‧ second node
N3‧‧‧ third node
G(1)～G(n)‧‧‧ drive signals
P(n)‧‧‧ pulldown control signal
T1~t7‧‧‧ time point
Q(n)‧‧‧ signal

FIG. 1 is a schematic diagram of a shift register circuit according to an embodiment of the invention. 2 is a circuit diagram of a shift register according to an embodiment of the invention. FIG. 3A is a schematic circuit diagram of a shift register according to a first embodiment of the present invention. FIG. 3B is a voltage timing diagram of the shift register according to the embodiment of FIG. 3A. 4A is a circuit diagram of a shift register according to a second embodiment of the present invention. 4B is a voltage timing diagram of the shift register according to the embodiment of FIG. 4A. FIG. 5A is a schematic circuit diagram of a shift register according to a third embodiment of the present invention. FIG. 5B is a voltage timing diagram of the shift register according to the embodiment of FIG. 5A. FIG. 6 is a schematic circuit diagram of a shift register according to a fourth embodiment of the present invention. FIG. 7A is a schematic circuit diagram of a shift register according to a fifth embodiment of the present invention. FIG. 7B is a voltage timing diagram of the shift register according to the embodiment of FIG. 7A. FIG. 8A is a schematic circuit diagram of a shift register according to a sixth embodiment of the present invention. FIG. 8B is a voltage timing diagram of the shift register according to the embodiment of FIG. 8A.

20‧‧‧Shift register

21‧‧‧Drive Module

22‧‧‧Recharge module

221‧‧‧Power storage unit

222‧‧‧First switch

223‧‧‧Control unit

23‧‧‧ Pull-up module

24‧‧‧Main drop-down module

CK‧‧‧ first clock signal end

XCK‧‧‧second clock signal end

VSS‧‧‧reference voltage terminal

Out‧‧‧output node

N1‧‧‧ first node

N2‧‧‧ second node

N3‧‧‧ third node

Q(n)‧‧‧ signal

Claims (16)

A shift register circuit includes a multi-stage shift register, wherein at least one of the shift registers includes: a driving module, at least electrically connected to a first node, and provided according to a first driving signal a working signal to the first node; a recharging module electrically connected to the first node and a second node, having at least one power storage unit, a first switch and a control unit, and one end of the power storage unit is electrically Connected to the first node, the other end of the power storage unit is electrically connected to a third node, the control unit is electrically connected to at least a first indication signal end, and the control unit provides a recharge signal to the first switch, and The voltage of the third node is adjusted according to the voltage of the first node, the first switch provides the recharging signal to the second node according to the voltage of the third node; and a pull-up module is configured according to the second The voltage of the node turns on a first clock signal end and an output node; and a main pull-down module is configured to turn on the output node and a reference voltage end according to the voltage of the second clock signal end. The shift temporary storage circuit of claim 1, wherein the control unit has a second switch, and the second switch turns on the first indication signal end and the first switch according to the voltage of the first node, when the first When the two switches are turned on, the control unit provides the recharging signal to the first switch by the voltage of the first indicator signal end. The shift register circuit of claim 2, wherein the second switch further turns on the first indicator signal end and the third node according to the voltage of the first node to adjust the voltage of the third node. The shift register circuit of claim 3, wherein when the second switch is turned on and the voltage of the first indicator signal terminal is a low voltage level, the power storage unit is charged by the voltage of the first node, when the first When the second switch is turned on and the voltage of the first indication signal terminal is a high voltage level, the first switch is turned on, and the recharging signal is provided to the second node. The shift register circuit of claim 3, wherein the first end of the first switch and the control end are electrically connected to the third node, and the second end of the first switch is electrically connected to the second node, The first end of the second switch is electrically connected to the first indicator signal end, and the second end of the second switch is electrically connected to the third node, and the control end of the second switch is electrically connected to the first node. The shift register circuit of claim 3, wherein the shift register further comprises a first pull-down module, wherein the first pull-down module turns on the second node according to a first control signal Reference voltage terminal. The shift register circuit of claim 2, wherein the control unit further has a third switch, wherein the third switch turns on a second indication signal end and the third node according to the voltage of the first node, The voltage at the second indication signal terminal adjusts the voltage of the third node. The shift register circuit of claim 7, wherein the first switch is turned on when the second switch and the third switch are turned on, and the voltage of the second indicator signal is at a high voltage level, The voltage at the signal terminal is adjusted to adjust the voltage of the second node. The shift temporary storage circuit of claim 8, wherein the voltage of the second node rises when the voltage of the first indication signal terminal is a high voltage level, and when the voltage of the first indication signal terminal is a low voltage level The voltage of the two nodes is decreased, and the voltage of the first indication signal terminal and the voltage of the second indication signal terminal are both high voltage levels, and the voltage of the first indication signal terminal is a high voltage level and the second indication signal end is The time at which the voltage is at a high voltage level. The shift register circuit of claim 7, wherein the first end of the first switch is electrically connected to the second end of the second switch, and the second end of the first switch is electrically connected to the second node, The control end of the first switch is electrically connected to the third node, the first end of the second switch is electrically connected to the first indication signal end, and the control end of the second switch is electrically connected to the first node, the first The first end of the third switch is electrically connected to the second indicator signal end, and the second end of the third switch is electrically connected to the third node, and the control end of the third switch is electrically connected to the first node. The shift register circuit of claim 1, wherein the shift register further comprises a pull-down control module and an auxiliary pull-down module, and the auxiliary pull-down module is controlled according to the pull-down control generated by the pull-down control module. The signal turns on the reference voltage terminal and the second node, and turns on the reference voltage terminal and the output node. The shift register circuit of claim 11, wherein the shift register further comprises a second pull-down module, and the second pull-down module turns on the first node and the second node according to the pull-down control signal . The shift register circuit of claim 1, wherein the shift register further comprises a second pull-down module, wherein the second pull-down module turns on the first node and the reference voltage according to a second control signal end. The shifting temporary storage circuit of claim 1, wherein the driving module has a first driving unit and a second driving unit, and the first driving unit provides the working signal to the first according to the first driving signal. And the second driving unit provides the working signal to the second node according to the first driving signal. The shift register circuit of claim 14, wherein the first driving unit further resets the voltage of the first node according to a second driving signal, and the second driving unit further resets the voltage according to the second driving signal. The voltage of the first node. The shift register circuit of claim 14, wherein the first driving unit further resets the voltage of the first node according to the voltage of the first clock signal end, and the second driving unit is further configured according to a second driving signal. Reset the voltage of the first node.