TWI576855B - Memory control apparatus and memory control test method thereof - Google Patents

Description

Memory control device and memory control test method thereof

The present invention relates to a control device, and more particularly to a memory control device and a memory control test method thereof.

In the manufacturing process of the memory, process-related errors caused by dust particles on the wafer or mask, scratching, and pinholes in the gate oxide layer often cause the memory to be affected, resulting in improper opening or short circuit. A number of methods or hardware have been developed to test whether memory is functioning properly. As the integrated circuit technology changes with each passing day, the memory function becomes more and more complicated, and thus the control circuit of the memory is also complicated.

Regarding the testing of memory, the Built-in self-test (BIST) technology of memory has been developed, and conventionally, it can be implemented using a state machine. The test on the memory control circuit generally only performs the suspend and resume instructions on the memory control circuit at a fixed frequency. However, this method cannot completely test all control operations of the memory control circuit. Therefore, the quality of the memory device cannot be effectively controlled, and the probability of the memory device malfunctioning at the client is further reduced.

The invention provides a memory control device and a memory control test method thereof, which can more completely test the memory control operation of the memory control device.

The memory control device of the present invention includes a state machine unit, N logic circuits, a control unit, and a recovery control unit. The state machine unit has N state machine circuits, and the N state machine circuits are used to sequentially perform their corresponding memory control operations, where N is a positive integer. The N logic circuits are respectively coupled to the corresponding state machine circuits, and respectively output the suspended signals according to the status bit signals and the flag signals outputted by the respective state machine circuits to the corresponding state machine circuits to suspend the corresponding state machine circuits. Memory control operation. The control unit is coupled to the logic circuit to receive the recovery signal, and the receiving of the response recovery signal sequentially outputs the flag signal to the logic circuit to sequentially suspend the memory control operation of the state machine circuit. The recovery control unit is coupled to the logic circuit, generates a ready signal according to the suspension signal, delays the ready signal to generate a recovery signal to the state machine unit and the control unit, restores the state machine circuit to perform the memory control operation, and causes the control unit to output the flag Standard signal.

In an embodiment of the invention, the control unit includes a shift register. The shift register is coupled to the logic circuit and the recovery control unit, and outputs a flag signal according to the recovery signal and the input signal. The shift register includes N+1 shift circuits, and the N+1 shift circuits shift the input signal according to the recovery signal to generate a flag signal.

In an embodiment of the invention, each of the logic circuits performs a sum operation according to a status bit signal output by the corresponding state machine circuit and a flag signal output by the corresponding displacement circuit to generate a suspension signal to the corresponding state machine circuit.

In an embodiment of the invention, each of the logic circuits includes a gate, and the input end is coupled to the corresponding state machine circuit and the corresponding displacement circuit, and the state bit signal and the corresponding displacement circuit according to the corresponding state machine circuit output. The output flag signal generates an abort signal to the corresponding state machine circuit.

In an embodiment of the invention, wherein the N+1th shift circuit outputs a flag signal, the memory control device passes the memory control test.

In an embodiment of the invention, the state machine circuit described above has different memory control operating times.

The invention further provides a memory control test method for a memory control device, wherein the memory control device comprises a state machine unit having N state machine circuits, wherein N is a positive integer, and the memory control test method of the memory control device comprises The following steps. A control unit is provided, and the control unit receives the recovery signal and outputs the flag signal in sequence in response to the reception of the recovery signal. N logic circuits are provided, and the N logic circuits respectively output the suspension signal to the corresponding state machine circuit according to the status bit signal output by each state machine circuit and the flag signal to suspend the memory control operation of the corresponding state machine circuit. A ready signal is generated based on the abort signal. The ready signal is delayed to generate a recovery signal to the state machine unit and the control unit to restore the state machine circuit to perform a memory control operation and to cause the control unit to output a flag signal. Determine if each state machine circuit has been aborted. If each state machine circuit has been suspended, the memory control device passes the memory control test.

In an embodiment of the invention, the memory control test method of the memory control device includes: providing a shift register, and outputting a flag signal according to the recovery signal and the input signal, wherein the shift register comprises N+ A displacement circuit that shifts the input signal to generate a recovery signal.

In an embodiment of the invention, each logic circuit performs a sum operation according to a status bit signal output by the corresponding state machine circuit and a flag signal output by the corresponding displacement circuit to generate a suspension signal to the corresponding state machine circuit.

In an embodiment of the present invention, the memory control test method of the memory control device includes: providing a plurality of gates, and each gate and the corresponding state circuit circuit output state bit signal and corresponding displacement circuit output The flag signal generates abort signal to the corresponding state machine circuit.

In an embodiment of the invention, wherein the N+1th shift circuit outputs a flag signal, the memory control device passes the memory control test.

In an embodiment of the invention, the state machine circuit described above has different memory control operating times.

Based on the above, the control unit of the embodiment of the present invention sequentially outputs the flag signal to the logic circuit in response to the reception of the recovery signal, so that the logic circuit sequentially issues the suspension signal to suspend the corresponding state machine circuit, wherein the recovery signal is the recovery control unit. By generating the delay ready signal, it is possible to test whether the memory control operations of the various state machine circuits can operate normally, thereby improving the quality of the memory control device.

The above described features and advantages of the invention will be apparent from the following description.

1 is a schematic diagram of a memory control device according to an embodiment of the present invention. Please refer to FIG. 1. The memory control device 100 includes a state machine unit 102 (which includes N state machine circuits ST1 to STN), N logic circuits LOC1 LOLOCN, a control unit 104, and a recovery control unit 106, where N is a positive integer. The logic circuits LOC1 LOLOCN are respectively coupled to their corresponding state machine circuits ST1~STN and the control unit 104, and the recovery control unit 106 is coupled to the logic circuits LOC1 LOLOCN, the state machine unit 102, and the control unit 104 (the picture cleaning is not maintained, Therefore, it is not shown).

The state machine circuits ST1~STN are respectively configured to perform their corresponding memory control operations. For example, when the memory control device 100 is configured to execute a write command, the state machine circuits ST1 STSTN can be used, for example, to verify respectively. a memory control operation, a voltage pump, a write, a discharge, a charge, etc., wherein a state machine circuit that performs different memory control operations may have Different memories control the operation time, and the memory control operations performed by the respective state machine circuits ST1 to STN may differ depending on the instructions executed by the memory control device (for example, executing an erase command). The control unit 104 can sequentially send the flag signal to the respective logic circuits LOC1 LOLOCN in response to the reception of the recovery signal Re1, and the logic circuits LOC1 LO LOCN are respectively used to output the status bit signals according to the corresponding state machine circuit and The flag signal from control unit 104 generates a suspend signal to the corresponding state machine circuit to suspend the memory control operation of the corresponding state machine circuits ST1~STN. In addition, the recovery control unit 106 can generate a ready signal according to the suspension signal when any of the logic circuits LOC1 LOLON outputs the suspension signal, and delay the ready signal to generate the recovery signal Re1 to the state machine unit 102 and the control unit 104. The recovery state machine circuits ST1 to STN perform a memory control operation and cause the control unit 104 to continue outputting the flag signal to the next logic circuit.

For example, control unit 104 may first issue a flag signal to state machine circuit ST1 (assuming its corresponding memory control operation is "start") to initiate state machine unit 102 to begin performing a memory control operation. The logic circuit LOC1 corresponding to the state machine circuit ST1 can output the suspension signal to the state machine circuit ST1 according to the state bit signal of the state machine circuit ST1 and the flag signal sent from the control unit 104 to suspend the memory control operation of the state machine circuit ST1. . After the recovery control unit 106 receives the suspension signal output by the logic circuit LOC1, it can generate a ready signal, and delay the ready signal generation recovery signal Re1 to the state machine circuit ST1 and the control unit 104 to restore the state machine unit 102 to the memory. The body control operation is performed, and the control unit 104 continues to issue a flag signal to the next state machine circuit (state machine circuit ST2). At this time, since the logic circuit LOC1 of the corresponding state machine circuit ST1 does not receive the flag signal sent from the control unit 104, the state machine circuit ST1 is not suspended, and the test of the state machine circuit ST2 can be continued.

Similarly, the logic circuit LOC2 can output a suspension signal to the state machine circuit ST2 according to the status bit signal of the state machine circuit ST2 and the flag signal sent from the control unit 104 to suspend the memory control operation of the state machine circuit ST2 (which can for example For the "verify" operation). If the control unit 104 can smoothly restore the state machine unit 102 and cause the next state machine circuit (state machine circuit ST2) to perform its corresponding memory control operation, the representative state machine circuit ST1 can smoothly recover from the suspended state. The circuit representing the state machine circuit ST1 can be normally executed, that is, it passes the test. By analogy, the control unit 104 can sequentially output the flag signal to the logic circuits LOC3~LOCN to sequentially suspend the state machine circuits ST3~STN, and the recovery control unit 106 according to the logic signals LOC3~LOCN. The recovery signal Re1 is generated to restart the state machine unit 102 to sequentially test whether the state machine circuits ST3 to STN can resume from the suspended state and normally perform the memory control operation. If each of the state machine circuits ST1 to STN can resume from the suspended state and normally perform the memory control operation, that is, the memory control device 100 passes the test. If any of the state machine circuits cannot resume from the suspended state during the test and the memory control operation is normally performed, for example, after a predetermined period of time, the recovery cannot be resumed from the suspended state, the memory control device 100 is not represented. Passed the test.

Since the time required to perform different memory control operations is not the same, the conventional technique does not fully test the memory control circuit by issuing a test method of abort and resume commands on a fixed frequency path. Compared with the prior art, the present embodiment sequentially suspends and resumes the memory control operations of the state machine circuits ST1 to STN, and can more completely test whether the circuit for performing the memory control operation in the memory control device 100 has The defect can effectively improve the quality of the control of the memory control device 100.

2 is a schematic diagram of a memory control device according to an embodiment of the present invention. Please refer to FIG. 2. In the memory control device 200 of the embodiment, the control unit 104 can be implemented, for example, by the shift register 202, which is coupled to the logic circuits LOC1 LOLOCN and the recovery control unit 106, and the shift register 202 can be restored according to the recovery. The signal Re1 and the input signal output a flag signal, wherein the flag signal is an input signal that is logically operated and delayed. In detail, the shift register 202 may include N+1 shift circuits SR1~SRN+1, and the shift circuits SR1~SRN+1 may shift the input signal according to the resume signal Re1 to generate a flag signal. Further, each time the shift register 202 receives the resume signal Re1, the shift circuits SR1~SRN+1 perform a shift operation on the input signals to sequentially output the flag signals to the logic circuits LOC1~LOCN. The memory control operation of the state machine circuits ST1 to STN corresponding to the logic circuits LOC1 to LOCN is suspended. The logic circuits LOC1 LOLOCN can be used to perform and operate according to the status bit signal output by the corresponding state machine circuit and the flag signal output by the corresponding displacement circuit to generate a suspension signal to the corresponding state machine circuits ST1 STSTN. In this embodiment, the logic circuits LOC1 LO LOCN can be implemented, for example, and the gates. However, in other embodiments, the logic circuits LOC1 LO LOCN can also be implemented by using different logic gates, for example, or The gate is implemented, or it is implemented with a gate and a gate. The input end of the gate can be coupled to the corresponding state machine circuit and the corresponding displacement circuit, so that the state bit signal outputted by the corresponding state machine circuits ST1~STN and the corresponding displacement circuit SR1~SRN can be respectively outputted according to the flag. The signal generates an abort signal to the corresponding state machine circuits ST1~STN. When the N+1th shift circuit SRN+1 outputs the flag signal, it means that all the state machine circuits ST1~STN have been tested for suspension and recovery, and the memory control operation can be performed normally, representing the memory. The control device 100 passes the test.

3 is a schematic diagram of a memory control test method of a memory control device according to an embodiment of the present invention. Please refer to FIG. 3. As can be seen from the above embodiments, the memory control test method of the memory control device may include the following steps. First, a control unit is provided. The control unit is configured to receive the recovery signal and output the flag signal in sequence in response to the reception of the recovery signal (step S302). Next, N logic circuits are provided, and the N logic circuits respectively output the suspension signal to the corresponding state machine circuit according to the status bit signal output by each state machine circuit and the flag signal to suspend the memory control operation of the corresponding state machine circuit. (Step S304). Where N is a positive integer, the state machine circuit can have different memory control operation time, and the logic circuit can perform and operate according to the state bit signal output by the corresponding state machine circuit and the flag signal output by the corresponding displacement circuit, Abort signal is generated to the corresponding state machine circuit. Then, a ready signal is generated according to the suspension signal (step S306), and the ready signal is further delayed to generate a recovery signal to the state machine unit and the control unit to restore the state machine circuit to perform the memory control operation, and cause the control unit to output the flag signal (step S308). Finally, it is judged whether or not each state machine circuit has been suspended (step S310). If each state machine circuit has been suspended, the memory control device passes the memory control test (step S312). Conversely, if each state machine circuit has not been suspended yet, return to step S302 to continue the test of the memory control device. In addition, if any of the state machine circuits cannot resume from the suspended state during the test and the memory control operation is normally performed, for example, after a predetermined period of time, the recovery cannot be resumed from the suspended state, the memory control device is not represented. Passed the test.

4 is a schematic diagram of a memory control test method of a memory control device according to another embodiment of the present invention, please refer to FIG. 4. In this embodiment, the control unit of the embodiment of FIG. 3 can be implemented, for example, by a shift register, and the logic circuit can be implemented, for example, and a gate. However, in other embodiments, the logic circuit is also This can be implemented, for example, with a different logic gate, for example with a sluice gate, or with a sluice gate and a brake. In this embodiment, the memory control test method of the memory control device may include the following steps. First, a shift register is provided. The shift register outputs a flag signal according to the recovery signal and the input signal, wherein the shift register comprises N+1 shift circuits, and the input signal is shifted to generate a resume signal (step S402). Then, a plurality of gates are provided, and each gate generates a suspension signal to the corresponding state machine circuit according to the state bit signal output by the corresponding state machine circuit and the flag signal output by the corresponding displacement circuit (step S404). Then, proceeding to step S406, a ready signal is generated in accordance with the suspension signal. Thereafter, the ready signal is delayed to generate a recovery signal to the state machine unit and the shift register to restore the state machine circuit to perform a memory control operation, and to cause the shift register to output a flag signal (step S408). Finally, it is judged whether the N+1th shift circuit outputs a flag signal (step S410), and if the N+1th shift circuit outputs a flag signal, the memory control device passes the memory control test (step S412). Conversely, if the N+1th shift circuit does not output the flag signal, the process returns to step S402 to continue the test of the memory control device.

In summary, the control unit of the embodiment of the present invention sequentially outputs the flag signal to the logic circuit in response to receiving the recovery signal, so that the logic circuit sequentially issues the suspension signal to suspend the corresponding state machine circuit, wherein the recovery signal is recovered. The control unit is generated by a delay ready signal. In this way, the memory control operation of each state machine circuit can be suspended and restored sequentially, and the circuit for performing the memory control operation in the memory control device can be more completely tested for defects, thereby effectively improving the memory control device. Control quality.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100,200‧‧‧ memory control device
102‧‧‧ state machine unit
104‧‧‧Control unit
106‧‧‧Recovery control unit
LOC1~LOCN‧‧‧ logic circuit
Re1‧‧‧Recovery signal
ST1~STN‧‧‧ state machine circuit
SR1~SRN+1‧‧‧displacement circuit
Steps of memory control test method for S302~S312, S402~S412‧‧‧ memory control device

1 is a schematic diagram of a memory control device in accordance with an embodiment of the present invention. 2 is a schematic diagram of a memory control device in accordance with an embodiment of the present invention. 3 is a schematic diagram of a memory control test method of a memory control device according to an embodiment of the invention. 4 is a schematic diagram of a memory control test method of a memory control device according to another embodiment of the present invention.

100‧‧‧ memory control device

102‧‧‧ state machine unit

ST1~STN‧‧‧ state machine circuit

LOC1~LOCN‧‧‧ logic circuit

104‧‧‧Control unit

106‧‧‧Recovery control unit

Re1‧‧‧Recovery signal

Claims (12)

A memory control device includes: a state machine unit having N state machine circuits for sequentially performing their corresponding memory control operations, wherein N is a positive integer; N logic circuits, respectively Coupling the corresponding state machine circuits, and respectively outputting a suspend signal to the corresponding state machine circuit according to the state bit signal outputted by each state machine circuit and a flag signal to suspend the corresponding state machine circuit a memory control operation; a control unit coupled to the logic circuits, receiving a recovery signal, and receiving the recovery signal to sequentially output the flag signal to the logic circuits to sequentially suspend the state machine circuits a memory control operation; and a recovery control unit coupled to the state machine unit, the logic circuits, and the control unit, generating a ready signal according to the suspension signal, delaying the ready signal to generate the recovery signal to The state machine unit and the control unit restore the state machine circuits to perform a memory control operation, and cause the control unit to output Flag signals. The memory control device of claim 1, wherein the control unit comprises: a shift register coupled to the logic circuit and the recovery control unit, and outputting the signal according to the recovery signal and an input signal The flag signal, the shift register includes: N+1 shift circuits, and the shift circuits shift the input signal according to the resume signal to generate the flag signal. The memory control device of claim 2, wherein each of the logic circuits performs an AND operation according to a status bit signal output by the corresponding state machine circuit and a flag signal output by the corresponding displacement circuit to generate the The signal is aborted to the corresponding state machine circuit. The memory control device of claim 3, wherein each of the logic circuits comprises: a gate, the input end of which is coupled to the corresponding state machine circuit and the corresponding displacement circuit, according to the output of the corresponding state machine circuit The status bit signal and the flag signal output by the corresponding displacement circuit generate the abort signal to the corresponding state machine circuit. The memory control device according to claim 2, wherein if the N+1th shift circuit outputs the flag signal, the memory control device passes the memory control test. The memory control device of claim 1, wherein the state machine circuits have different memory control operation times. A memory control test method for a memory control device, wherein the memory control device includes a state machine unit having N state machine circuits, wherein N is a positive integer, and the memory control test method of the memory control device includes: providing a control unit, the control unit receives a recovery signal, and sequentially outputs a flag signal in response to the reception of the recovery signal; and provides N logic circuits, respectively, according to status bit outputs of each state machine circuit output The signal and the flag signal output a stop signal to the corresponding state machine circuit to suspend the memory control operation of the corresponding state machine circuit; generate a ready signal according to the stop signal; delay the ready signal to generate the recovery Signaling to the state machine unit and the control unit to restore the state machine circuits to perform a memory control operation, and causing the control unit to output the flag signal; determining whether each state machine circuit has been suspended; Each of the state machine circuits has been suspended, and the memory control device passes the memory control test . The memory control test method of the memory control device of claim 7, comprising: providing a shift register, and outputting the flag signal according to the resume signal and an input signal, wherein the shift is temporarily The memory includes N+1 shift circuits that shift the input signal to generate the recovered signal. The memory control test method of the memory control device according to claim 8, comprising: each of the logic circuits is executed according to a status bit signal output by the corresponding state machine circuit and a flag signal output by the corresponding displacement circuit An operation is performed to generate the abort signal to the corresponding state machine circuit. The memory control test method of the memory control device according to claim 9, comprising: providing a plurality of gates, each of the gates according to a state machine signal output by the corresponding state machine circuit and a corresponding displacement circuit The output flag signal generates the abort signal to the corresponding state machine circuit. The memory control test method of the memory control device according to claim 8, wherein the memory control device passes the memory control test if the N+1th shift circuit outputs the flag signal. The memory control test method of the memory control device according to claim 7, wherein the state machine circuits have different memory control operation times.