TWI576843B - Memory device and method for manufacturing the same - Google Patents

Description

Memory device and method of manufacturing same

The present invention relates to a memory device, and more particularly to a unipolar resistive random-access memory (ReRAM) device.

As a candidate for the next generation of nonvolatile memory applications, resistive random access memory has attracted a lot of attention due to its simple metal-insulator-metal structure. Excellent scalability, fast switching speed, low voltage operation and good compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) technology. Two common electrical group switching modes of resistive random access memory include bipolar operation and unipolar operation.

However, bipolar operation may result in area consumption. In addition, general resistive random access memory includes planar metal Metal-Oxide-Semiconductor (MOS) selectors may also cause regional consumption.

Therefore, unipolar operation is more attractive because it is ideally integrated into a one-diode-one-resistor (1D1R) array with a 4F ² memory cell size for high density applications. A variety of unipolar resistive random access memory materials have been investigated, such as tungsten oxide (WO _x ), hafnium oxide (HfO ₂ ), and tantalum oxide (Ta ₂ O _x ). Silicide based materials have also attracted attention due to their good compatibility with complementary metal oxide semiconductor technology.

The present invention relates to a memory device having a PVD titanium nitride/tungsten/oxide/polysilicon oxide (PVD TiN/WSi _x O _y /W-silicide/polysilicide) structure and a method of fabricating the same. Furthermore, the memory device of the present invention can include more vertical diodes as a selector than planar metal oxide semiconductor selectors.

According to the present invention, a memory device is provided having an array region and a peripheral region. The memory device includes a substrate, an isolation layer, a first doped region, a second doped region, a metal deuterated layer, and a metal deuterated oxide layer. The isolation layer is formed on the substrate. The first doped region is formed on the isolation layer in the array region. The second doped region is formed on the first doped region. A metal deuteration layer is formed on the second doped region. A metal deuterated oxide layer is formed on the metal deuterated layer.

According to the present invention, a method of manufacturing a memory device is provided Including the following steps. A substrate is provided. A polysilicon layer is deposited on the substrate. A photoresist layer is formed on the polysilicon layer to define an array region and a peripheral region. A first doped region is formed at the bottom of the polysilicon layer in the array region. A second doped region and an undoped region are formed in the array region, a second doped region is located on top of the polysilicon layer, and an undoped region is located between the first doped region and the second doped region. A metal deuterated layer is deposited on the polycrystalline layer. The metal deuteration layer in the patterned array region, the first doped region and the undoped region of the polysilicon layer are formed to form a plurality of holes. A spacer is formed in the hole. A metal deuterated oxide layer is formed on the metal deuteration layer in the array region.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

100‧‧‧ memory device

11‧‧‧Substrate

13‧‧‧Mat oxide layer

14‧‧‧ gate oxide layer

15‧‧‧layer of tantalum nitride

17‧‧‧Isolation

19a‧‧‧P well

19b‧‧‧N Well

21‧‧‧Polysilicon layer

21a‧‧‧First doped region

21b‧‧‧Second doped region

21c‧‧‧Undoped areas

23‧‧‧Metalized layer

25, 27‧‧‧ holes

29‧‧‧ spacers

31a‧‧‧First doped polysilicon

31b‧‧‧Second doped polysilicon

33‧‧‧Dielectric layer

35‧‧‧First contact plug

37‧‧‧Shielding layer

39‧‧‧Perforation

41‧‧‧Metal deuterated oxide layer

43‧‧‧Second contact plug

45‧‧‧metal wire

91‧‧‧ photoresist layer

A1‧‧‧Array area

A2‧‧‧ surrounding area

S1, D1‧‧‧ first electrode

S11‧‧‧First Extension

D11‧‧‧Second extension

S2, D2‧‧‧ second electrode

S21‧‧‧ Third Extension

D21‧‧‧4th extension

1 is a cross-sectional view of a memory device in accordance with an embodiment of the present invention.

2A to 2M are views showing a manufacturing embodiment of the memory device in accordance with the present invention.

Figure 3 is a schematic diagram showing the memory device in a subsequent step.

Figure 4 is a graph showing the comparison of the initial resistance of a nitrided tungsten oxide resistive random access memory having a top electrode of PVD titanium nitride and CVD titanium nitride.

Figure 5 is a graph showing the R-V characteristics of a unipolar deuterated tungsten oxide resistive random access memory.

Figure 6 is a diagram showing a transient I-t diagram of a SET/RESET pulse to a monopolar tungsten resistive random access memory device.

Figure 7 is a graph showing the forming voltage of a unipolar deuterated tungsten oxide resistive random access memory as a function of the shaped pulse width.

Figure 8 is a graph showing the cycle characteristics of a unipolar deuterated tungsten oxide resistive random access memory.

Figure 9 shows the data retention capability of the RESET and SET states for one hour at 250 °C.

Embodiments of the present invention will be described in detail below with reference to the drawings. The same reference numerals are used to designate the same or similar parts. It is to be noted that the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to the scale of the actual products, and thus are not intended to limit the scope of the present invention.

1 is a cross-sectional view of a memory device 100 in accordance with an embodiment of the present invention. In this embodiment, the memory device 100 can have an array area A1 and a peripheral area A2. As shown in FIG. 1, the memory device 100 can include a substrate 11, an isolation layer 17, a first doped region 21a, a second doped region 21b, a metal deuteration layer 23, and a metal deuterated oxide layer 41. The isolation layer 17 is formed in the substrate 11, the first doped region 21a is formed on the isolation region 17 in the array region A1, the second doped region 21b is formed on the first doped region 21a, and the metal deuterated layer 23 is formed on On the second doped region 21b, a metal deuterated oxide layer 41 is formed on the metal deuterated layer 23.

In the present embodiment, the first doped region 21a is opposite to the conductive type of the second doped region 21b. For example, the first doped region 21a may be a P-type doped region, and the second doped region 21b may be an N-type doped region. However, the invention is not limited thereto. In another reality In an embodiment, the first doped region 21a may be an N-type doped region, and the second doped region 21b may be a P-type doped region. Other components depicted in Figure 1 will be described in the following description.

2A through 2M illustrate a manufacturing embodiment of a memory device 100 in accordance with the present invention. As shown in Fig. 2A, a substrate 11 is provided. Then, a pad oxide 13 and a tantalum nitride layer 15 are sequentially deposited on the substrate 11. An isolation layer 17 is formed in the substrate 11, the pad oxide layer 13, and the tantalum nitride layer 15. In this embodiment, the isolation layer 17 can be a shallow trench isolation (STI) or a local oxidation of silicon (LOCOS) isolation layer.

As shown in FIG. 2B, the tantalum nitride layer 15 is removed, and a P well 19a and an N well 19b are formed in the substrate 11. The N well 19b is adjacent to the P well 19a. In the present embodiment, the P well 19a and the N well 19b may be formed by ion implantation, and a portion of the isolation layer 17 may be disposed between the P well 19a and the N well 19b.

As shown in FIG. 2C, the pad oxide layer 13 is replaced by the gate oxide layer 14, and the gate oxide layer 14 is deposited on the P well 19a and the N well 19b. Next, a polysilicon layer 21 is deposited on the substrate 11, and a photoresist layer 91 is formed on the polysilicon layer 21 to define an array region A1 and a peripheral region A2. That is, the polysilicon layer 21 is formed on the isolation layer 17 in the array region A1, and is formed on the gate oxide layer 14 and the isolation layer 17 in the peripheral region A2.

As shown in FIG. 2D, in the array region A1, a first doped region 21a is formed on the bottom of the polysilicon layer 21, and a second doped region 21b is formed on the top of the polysilicon layer 21 while forming an undoped region. 21c is between the first doped region 21a and the second doped region 21b. That is, the second doped region 21b is formed on the first doped region 21a, and is not doped The impurity region 21c is separated from the first doping region 21a.

Here, the thickness of the first doping region 21a may be between 50 and 1000 Å, and the thickness of the second doping region 21b may be between 50 and 1000 Å. However, the invention is not limited thereto. The thickness of the first doped region 21a and the second doped region 21b may be determined according to the requirements of the memory device.

In an embodiment, the first doped region 21a may be P-type, and the conductive type of the second doped region 21b may be N-type. However, the invention is not limited thereto. In another embodiment, the first doped region 21a may be N-type, and the conductive type of the second doped region 21b may be P-type. The conductivity type of the first doped region 21a and the second doped region 21b depends on the mode of operation of the memory device.

In the embodiment of the present invention, the first doped region 21a, the undoped region 21c and the second doped region 21b can serve as a vertical diode.

In addition, the first doped region 21a and the second doped region 21b may be formed by ion implantation. Since the ion implantation is performed in the array area A1 and is separated from the peripheral area A2, the elements in the peripheral area A2 are not affected.

As shown in FIG. 2E, the photoresist layer 91 is removed. Next, a metal deuteration layer 23 is formed on the polysilicon layer 21 in the peripheral region A2 and on the second doping region 21b of the polysilicon layer 21 in the array region A1. In the present embodiment, the metal deuteration layer 23 may include tungsten tungsten, which can reduce the word line resistance.

As shown in FIG. 2F, a portion of the polysilicon layer 21 and the metal germanium layer 23 in the peripheral region A2 are patterned to form a plurality of holes 25. The etching process is stopped on the top surface of the gate oxide layer 14 and the surface of the isolation layer 17.

As shown in FIG. 2G, a portion of the metal deuterated layer 23, the undoped region 21c of the polysilicon layer 21, and the second doped region 21b in the patterned array region A1 are patterned to form a plurality of holes 27. The etching process is stopped at the top surface of the first doped region 21a of the polysilicon layer 21. In some embodiments, the etching processes of the 2F and 2G patterns can be performed simultaneously.

As shown in Fig. 2H, spacers 29 are formed in the holes 25, 27, and the spacers 29 seal the holes 27. That is, in the array area A1, the spacers 29 may be formed between the two metal deuterated layers 23. Next, two first electrodes S1 and D1 are formed in the P well 19a, and two second electrodes S2 and D2 are formed in the N well 19b. In the present embodiment, the first electrodes S1 and D1 and the second electrodes S2 and D2 are identical. For example, the first electrodes S1 and D1 and the second electrodes S2 and D2 can function as a source or a drain.

Further, a first doped polysilicon layer 31a is formed on the gate oxide layer 14 on the P well 19a, and a second doped polysilicon layer 31b is formed on the gate oxide layer 14 on the N well 19b. In this embodiment, the first doped polysilicon layer 31a can be formed by ion implantation of the polysilicon layer 31 on the P well 19a, and the second doped polysilicon layer 31b can be implanted on the N well 19b by ions. The polysilicon layer 31 is formed. That is, in the peripheral region A2, the metal deuterated layer 23 may be formed on the first doped polysilicon layer 31a and the second doped polysilicon layer 31b. Therefore, a dual-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) (PMOS and NMOS) can be formed in the peripheral region A2.

In some embodiments, a first extension S11, a second extension D11, a third extension S21, and a fourth extension D21 can be formed. The first extension S11 is formed in the P well 19a and is connected to the first electrode S1. The second extension D11 is formed in the P well 19a and connected to the first electric Extreme D1. The third extension S21 is formed in the N well 19b and is connected to the second electrode S2. The fourth extension portion D21 is formed in the N well 19b and is connected to the second electrode D2. Here, the first extension portion S11, the second extension portion D11, the third extension portion S21 and the fourth extension portion D21 may be a source/drain extension or a lightly doped drain (LDD).

As shown in FIG. 2I, a dielectric layer (inter-layer dielectric, ILD) 33 is formed on the isolation layer 17. In the present embodiment, in the peripheral region A2, the holes 25 are sealed by the dielectric layer 33, and the dielectric layer 33 may be formed on the surfaces of the spacers 29 and the metal deuterated layer 23. Next, a chemical mechanical polishing (CMP) can be performed on the dielectric layer 33.

As shown in FIG. 2J, a plurality of first contact plugs 35 are formed in the peripheral region A2 through the dielectric layer 33. In addition, the contact plug 35 can respectively connect the metal deuteration layer 23, the first electrode S1, the second electrode S2, the first electrode D1 and the second electrode D2 in the peripheral region A2.

In the present embodiment, the first contact plug 35 may include a CVD titanium nitride layer and tungsten (W). In some embodiments, the first contact plug 35 can further include a PVD titanium layer. Here, the CVD titanium nitride layer may be defined as a layer including titanium nitride, which is formed by chemical vapor deposition (CVD), and the PVD titanium layer may be defined as a layer including titanium. It is formed by physical vapor deposition (PVD).

As shown in FIG. 2K, a cap layer 37 is formed on the dielectric layer 33 to protect the first contact plug 35 in the peripheral region A2. In an embodiment, the shielding layer 37 may include tantalum nitride (SiN).

As shown in Fig. 2L, a plurality of through holes 39 are formed in the array area A1. Here, the through holes 39 can be formed by an etching process, and the metal germanium layer 23 in the array area A1 is exposed. Top surface.

As shown in FIG. 2M, a metal deuterated oxide layer 41 is formed on the metal deuterated layer 23 in the array region A1. In the present embodiment, the metal deuterated oxide layer 41 can be formed by rapid thermal oxidation (RTO) or plasma oxidation. For example, the metal deuteration layer 23 may be a tungsten oxide silicide (WSi _x ) layer, and the top of the tungsten germanium oxide layer may be converted into a tungsten oxide silicon oxide (WSi _x O _y ) layer.

Next, a plurality of second contact plugs 43 are formed in the array area A1 to seal the through holes 39, and the shielding layer 37 is removed, thus forming the memory device 100 as shown in Fig. 1. Further, a chemical mechanical polishing (CMP) can be performed. In the present embodiment, the second contact plug 43 can be connected to the metal deuterated oxide layer 41 in the array area A1.

In the present embodiment, the second contact plug 43 may include a PVD titanium nitride layer, a CVD titanium nitride layer and tungsten (W). Here, the PVD titanium nitride layer may be defined as a layer including titanium nitride, which is formed by physical vapor deposition (PVD), and the CVD titanium nitride layer may be defined as a layer including titanium nitride. It is formed by chemical vapor deposition (CVD).

Chemical vapor deposition (CVD) utilizes selected precursors to form C-inserted titanium nitride to deposit a titanium nitride layer, while physical vapor deposition (PVD) utilizes only titanium and nitrogen. A pure titanium nitride layer is formed. For CVD titanium nitride, hydrogen and nitrogen plasma treatment are required to decompose the precursor Tetra-dimethyl-amido-titanium (TDMAT) into Ti(C)N and by-products. This chemical reaction and plasma treatment result in impure titanium nitride, affecting the interface between the electrode and the transient film and the quality of the metal deuterated oxide (eg, WSi _x O _y ). On the other hand, the source of the PVD titanium nitride layer does not include excess elements, forms a strong interface and maintains a good metal deuterated oxide layer bond.

FIG. 3 is a schematic diagram showing the memory device 100 in a subsequent step. As shown in FIG. 3, a metal wire 45 may be formed to electrically connect the first contact plug 35 and the second contact plug 43.

Figure 4 is a graph showing the comparison of the initial resistance of a nitrided tungsten oxide resistive random access memory having a top electrode of PVD titanium nitride and CVD titanium nitride, respectively. As shown in Figure 4, the PVD titanium nitride process has been selected to have an improvement of more than 1000 times. In addition, the PVD titanium nitride layer can have a higher initial resistance, and these results demonstrate that the PVD titanium nitride layer can achieve a more robust metal oxide layer or a better titanium nitride/desalination tungsten oxide interface.

Figure 5 is a graph showing the R-V characteristics of a unipolar deuterated tungsten oxide resistive random access memory. A forming pulse is applied to obtain a first forming operation. The forming operation requires a higher operating voltage than RESET and SET (with a 50 ns pulse width). At the beginning, the new device requires a large voltage to establish a conductive path from top to bottom. Subsequent RESET and SET programs destroy and regenerate the local regions of filament, respectively. The forming process can be expected to require a voltage greater than the RESET/SET switching behavior. After forming, the tungsten-tellurium resistive random access memory can be switched to the unipolar mode by applying a negative pulse to SET and RESET. The operating voltages that are less than 3V for both SET and RESET show a switching window that is greater than 100 times.

Figure 6 is a diagram showing a transient I-t diagram of a SET/RESET pulse to a monopolar tungsten resistive random access memory device. From the transient I-t diagram of the oscilloscope, the tungsten-tellurium resistive random access memory device has a good switching at a pulse time of 50 ns. The SET and RESET currents are 400μA and 700μA, respectively, to achieve a SET (about 100Kohms) to RESET (about 1Mohms) resistance window.

Figure 7 shows the formation of a unipolar deuterated tungsten oxide resistive random access memory. The voltage is a function of the shaped pulse width. Figure 7 shows that as the shaping pulse width increases, the forming voltage exhibits a decreasing tendency. The forming operation is performed only once, so a longer forming pulse does not affect the operating speed of the main device. A 1 μs shaping pulse reduces the forming voltage to less than 3 V, as if it were not shaped.

Figure 8 is a graph showing the cycle characteristics of a unipolar deuterated tungsten oxide resistive random access memory. As shown in Fig. 8, the endurance of more than 100 can show a resistance window of about 10 times (for example, a switching window of 100 K? - 1 M?).

Figure 9 shows the data retention capability of the RESET and SET states for one hour at 250 °C. Figure 9 shows that a good window can be maintained after baking at a high temperature, demonstrating that the resistive random access memory has good data retention.

As described above for the embodiments of the present invention, monopolar metal deuterated oxide (e.g., WSi _x O _y ) resistive random access memory has been proposed and fabricated. The initial resistance is greatly improved by PVD titanium nitride, providing a new direction to optimize device performance. Good unipolar performance can show fast switching speed, good data storage and 10 times switching window.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory device

11‧‧‧Substrate

14‧‧‧ gate oxide layer

17‧‧‧Isolation

19a‧‧‧P well

19b‧‧‧N Well

21‧‧‧Polysilicon layer

21a‧‧‧First doped region

21b‧‧‧Second doped region

21c‧‧‧Undoped areas

23‧‧‧Metalized layer

41‧‧‧Metal deuterated oxide layer

43‧‧‧Second contact plug

A1‧‧‧Array area

A2‧‧‧ surrounding area

Claims (8)

A memory device having an array region and a peripheral region, the memory device comprising: a substrate; an isolation layer formed on the substrate; a first doped region formed on the isolation layer in the array region; a second doped region is formed on the first doped region; a metal deuterated layer is formed on the second doped region; a metal deuterated oxide layer is formed on the metal deuterated layer; a P well, Formed on the substrate; and an N well adjacent to the P well, wherein the P well and the N well are formed in the peripheral zone, and the isolation layer is formed between the P well and the N well. The memory device of claim 1, further comprising: two first electrodes formed on the P well; a first gate oxide layer formed on the P well; and two second electrodes formed And the second gate oxide layer is formed on the N well. The memory device of claim 2, further comprising: a first extension connecting one of the first electrodes; a second extension portion connecting the other of the first electrodes; a third extension portion connecting one of the second electrodes; and a fourth extension portion connecting the other of the second electrodes. The memory device of claim 2, further comprising: a first doped polysilicon layer formed on the first gate oxide layer; and a second doped polysilicon layer formed on the second gate And a plurality of the metal deuterated layers are formed on the first doped polysilicon layer and the second doped polysilicon layer. The memory device of claim 4, further comprising: a plurality of first contact plugs respectively connected to the metal deuteration layers, the first electrodes, and the second portions in the peripheral region The electrode, wherein the first contact plugs comprise a CVD titanium nitride layer and tungsten. The memory device of claim 1, further comprising: a second contact plug connected to the metal deuterated oxide layer in the array region, wherein the second contact plug comprises a PVD nitrogen Titanium layer, a CVD titanium nitride layer and tungsten. A method of manufacturing a memory device, comprising: providing a substrate; Depositing a polysilicon layer on the substrate; forming a P well and an N well in the substrate; forming a photoresist layer on the polysilicon layer to define an array region and a peripheral region, wherein the P well and the N well Forming in the peripheral region; forming a first doped region at the bottom of the polysilicon layer in the array region; forming a second doped region and an undoped region in the array region, the second doping a impurity region is located on top of the polysilicon layer, the undoped region is located between the first doped region and the second doped region; a metal deuteration layer is deposited on the polysilicon layer; and the pattern is patterned in the array region a metal deuteration layer, the first doped region and the undoped region of the polysilicon layer to form a plurality of holes; forming spacers in the holes; forming two first electrodes in the P well; forming two a second electrode is in the N well; and a metal deuterated oxide layer is formed on the metal deuteration layer in the array region. The manufacturing method of claim 7, further comprising: forming a plurality of first contact plugs, wherein the first contact plugs connect the first electrodes and the second ones in the peripheral area An electrode, wherein the first contact plugs comprise a CVD titanium nitride layer and tungsten; and a plurality of second contact plugs are formed, and the second contact plugs are connected to the array region to connect the metal deuterated oxide a layer, wherein the second contact plugs comprise a PVD nitride A titanium layer, a CVD titanium nitride layer and tungsten.