TWI576843B - Memory device and method for manufacturing the same - Google Patents
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Description
本發明是有關於一種記憶體裝置,且特別是有關於一種單極(unipolar)電阻式隨機存取記憶體(resistive random-access memory,ReRAM)裝置。 The present invention relates to a memory device, and more particularly to a unipolar resistive random-access memory (ReRAM) device.
作為次世代非易失性記憶體(nonvolatile memory)應用的一候選,電阻式隨機存取記憶體吸引了大量的關注,這是由於其簡單的金屬-絕緣體-金屬(metal-insulator-metal)結構、出色的可擴充性(scalability)、快速的開關速度(switching speed)、低電壓操作以及與互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor,CMOS)技術良好的相容性。電阻式隨機存取記憶體的兩種常用電組開關模式包括雙極(bipolar)操作與單極(unipolar)操作。 As a candidate for the next generation of nonvolatile memory applications, resistive random access memory has attracted a lot of attention due to its simple metal-insulator-metal structure. Excellent scalability, fast switching speed, low voltage operation and good compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) technology. Two common electrical group switching modes of resistive random access memory include bipolar operation and unipolar operation.
然而,雙極操作可能造成區域消耗(area consumption)。此外,一般電阻式隨機存取記憶體包括平面金屬 氧化物半導體(Metal-Oxide-Semiconductor,MOS)選擇器,也可能造成區域消耗。 However, bipolar operation may result in area consumption. In addition, general resistive random access memory includes planar metal Metal-Oxide-Semiconductor (MOS) selectors may also cause regional consumption.
因此,單極操作更具有吸引力,因為其可理想地以4F2記憶胞尺寸集成在一二極體一電阻(one-diode-one-resistor,1D1R)陣列中,作為高密度應用。多種單極電阻式隨機存取記憶體材料已被研究,例如氧化鎢(WOx)、二氧化鉿(HfO2)及氧化鉭(Ta2Ox)。矽基底(silicide based)材料也因其與互補式金屬氧化物半導體技術良好的相容性而引起注意。 Therefore, unipolar operation is more attractive because it is ideally integrated into a one-diode-one-resistor (1D1R) array with a 4F 2 memory cell size for high density applications. A variety of unipolar resistive random access memory materials have been investigated, such as tungsten oxide (WO x ), hafnium oxide (HfO 2 ), and tantalum oxide (Ta 2 O x ). Silicide based materials have also attracted attention due to their good compatibility with complementary metal oxide semiconductor technology.
本發明係有關於一種具有PVD氮化鈦/鎢矽化氧化物/矽化鎢/多晶矽(PVD TiN/WSixOy/W-silicide/polysilicide)結構的記憶體裝置與其製造方法。此外,本發明之記憶體裝置可包括相較於平面金屬氧化物半導體選擇器更多的垂直二極體(vertical diodes),作為選擇器。 The present invention relates to a memory device having a PVD titanium nitride/tungsten/oxide/polysilicon oxide (PVD TiN/WSi x O y /W-silicide/polysilicide) structure and a method of fabricating the same. Furthermore, the memory device of the present invention can include more vertical diodes as a selector than planar metal oxide semiconductor selectors.
根據本發明,提出一種記憶體裝置,具有一陣列區與一周邊區。記憶體裝置包括一基板、一隔離層、一第一摻雜區域、一第二摻雜區域、一金屬矽化層以及一金屬矽化氧化層。隔離層形成於基板。第一摻雜區域形成於陣列區內的隔離層上。第二摻雜區域形成於第一摻雜區域上。金屬矽化層形成於第二摻雜區域上。金屬矽化氧化層形成於金屬矽化層上。 According to the present invention, a memory device is provided having an array region and a peripheral region. The memory device includes a substrate, an isolation layer, a first doped region, a second doped region, a metal deuterated layer, and a metal deuterated oxide layer. The isolation layer is formed on the substrate. The first doped region is formed on the isolation layer in the array region. The second doped region is formed on the first doped region. A metal deuteration layer is formed on the second doped region. A metal deuterated oxide layer is formed on the metal deuterated layer.
根據本發明,提出一種記憶體裝置的製造方法,包 括以下步驟。提供一基板。沉積一多晶矽層於基板上。形成一光阻層於多晶矽層上,以定義一陣列區與一周邊區。形成一第一摻雜區域於陣列區內之多晶矽層的底部。形成一第二摻雜區域與一未摻雜區域於陣列區內,第二摻雜區域位於多晶矽層的頂部,未摻雜區域位於第一摻雜區與第二摻雜區域之間。沉積一金屬矽化層於多晶矽層上。圖案化陣列區內的金屬矽化層、多晶矽層之第一摻雜區域與未摻雜區域,以形成複數個孔洞。形成間隔物於孔洞內。形成一金屬矽化氧化層於陣列區內的金屬矽化層上。 According to the present invention, a method of manufacturing a memory device is provided Including the following steps. A substrate is provided. A polysilicon layer is deposited on the substrate. A photoresist layer is formed on the polysilicon layer to define an array region and a peripheral region. A first doped region is formed at the bottom of the polysilicon layer in the array region. A second doped region and an undoped region are formed in the array region, a second doped region is located on top of the polysilicon layer, and an undoped region is located between the first doped region and the second doped region. A metal deuterated layer is deposited on the polycrystalline layer. The metal deuteration layer in the patterned array region, the first doped region and the undoped region of the polysilicon layer are formed to form a plurality of holes. A spacer is formed in the hole. A metal deuterated oxide layer is formed on the metal deuteration layer in the array region.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下: In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
100‧‧‧記憶體裝置 100‧‧‧ memory device
11‧‧‧基板 11‧‧‧Substrate
13‧‧‧墊氧化層 13‧‧‧Mat oxide layer
14‧‧‧閘極氧化層 14‧‧‧ gate oxide layer
15‧‧‧氮化矽層 15‧‧‧layer of tantalum nitride
17‧‧‧隔離層 17‧‧‧Isolation
19a‧‧‧P井 19a‧‧‧P well
19b‧‧‧N井 19b‧‧‧N Well
21‧‧‧多晶矽層 21‧‧‧Polysilicon layer
21a‧‧‧第一摻雜區域 21a‧‧‧First doped region
21b‧‧‧第二摻雜區域 21b‧‧‧Second doped region
21c‧‧‧未摻雜區域 21c‧‧‧Undoped areas
23‧‧‧金屬矽化層 23‧‧‧Metalized layer
25、27‧‧‧孔洞 25, 27‧‧‧ holes
29‧‧‧間隔物 29‧‧‧ spacers
31a‧‧‧第一摻雜多晶矽 31a‧‧‧First doped polysilicon
31b‧‧‧第二摻雜多晶矽 31b‧‧‧Second doped polysilicon
33‧‧‧介電層 33‧‧‧Dielectric layer
35‧‧‧第一接點插塞 35‧‧‧First contact plug
37‧‧‧遮蔽層 37‧‧‧Shielding layer
39‧‧‧穿孔 39‧‧‧Perforation
41‧‧‧金屬矽化氧化層 41‧‧‧Metal deuterated oxide layer
43‧‧‧第二接點插塞 43‧‧‧Second contact plug
45‧‧‧金屬線 45‧‧‧metal wire
91‧‧‧光阻層 91‧‧‧ photoresist layer
A1‧‧‧陣列區 A1‧‧‧Array area
A2‧‧‧周邊區 A2‧‧‧ surrounding area
S1、D1‧‧‧第一電極 S1, D1‧‧‧ first electrode
S11‧‧‧第一延伸部 S11‧‧‧First Extension
D11‧‧‧第二延伸部 D11‧‧‧Second extension
S2、D2‧‧‧第二電極 S2, D2‧‧‧ second electrode
S21‧‧‧第三延伸部 S21‧‧‧ Third Extension
D21‧‧‧第四延伸部 D21‧‧‧4th extension
第1圖繪示依據本發明實施例之記憶體裝置的剖面圖。 1 is a cross-sectional view of a memory device in accordance with an embodiment of the present invention.
第2A至2M圖繪示依據本發明之記憶體裝置的一製造實施例。 2A to 2M are views showing a manufacturing embodiment of the memory device in accordance with the present invention.
第3圖繪示記憶體裝置在後續步驟中的示意圖。 Figure 3 is a schematic diagram showing the memory device in a subsequent step.
第4圖繪示分別具有頂電極為PVD氮化鈦與CVD氮化鈦之氮化氧化鎢電阻式隨機存取記憶體之起始電阻的比較。 Figure 4 is a graph showing the comparison of the initial resistance of a nitrided tungsten oxide resistive random access memory having a top electrode of PVD titanium nitride and CVD titanium nitride.
第5圖繪示單極矽化氧化鎢電阻式隨機存取記憶體的R-V特性圖。 Figure 5 is a graph showing the R-V characteristics of a unipolar deuterated tungsten oxide resistive random access memory.
第6圖繪示提供SET/RESET脈衝至單極鎢電阻式隨機存取記憶體裝置的瞬態(transient)I-t圖。 Figure 6 is a diagram showing a transient I-t diagram of a SET/RESET pulse to a monopolar tungsten resistive random access memory device.
第7圖繪示單極矽化氧化鎢電阻式隨機存取記憶體之成形電壓作為成形脈衝寬度的函數。 Figure 7 is a graph showing the forming voltage of a unipolar deuterated tungsten oxide resistive random access memory as a function of the shaped pulse width.
第8圖繪示單極矽化氧化鎢電阻式隨機存取記憶體的循環特性。 Figure 8 is a graph showing the cycle characteristics of a unipolar deuterated tungsten oxide resistive random access memory.
第9圖繪示在250℃持續一小時,RESET與SET狀態的資料保存能力。 Figure 9 shows the data retention capability of the RESET and SET states for one hour at 250 °C.
以下係參照所附圖式詳細敘述本發明之實施例。圖式中相同的標號係用以標示相同或類似之部分。需注意的是,圖式係已簡化以利清楚說明實施例之內容,圖式上的尺寸比例並非按照實際產品等比例繪製,因此並非作為限縮本發明保護範圍之用。 Embodiments of the present invention will be described in detail below with reference to the drawings. The same reference numerals are used to designate the same or similar parts. It is to be noted that the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to the scale of the actual products, and thus are not intended to limit the scope of the present invention.
第1圖繪示依據本發明實施例之記憶體裝置100的剖面圖。在本實施例中,記憶體裝置100可具有一陣列區A1與一周邊區A2。如第1圖所示,記憶體裝置100可包括一基板11、一隔離層17、一第一摻雜區域21a、一第二摻雜區域21b、一金屬矽化層23以及一金屬矽化氧化層41,隔離層17形成於基板11內,第一摻雜區域21a形成於陣列區A1內的隔離區17上,第二摻雜區域21b形成於第一摻雜區域21a上,金屬矽化層23形成於第二摻雜區域21b上,金屬矽化氧化層41形成於金屬矽化層23上。 1 is a cross-sectional view of a memory device 100 in accordance with an embodiment of the present invention. In this embodiment, the memory device 100 can have an array area A1 and a peripheral area A2. As shown in FIG. 1, the memory device 100 can include a substrate 11, an isolation layer 17, a first doped region 21a, a second doped region 21b, a metal deuteration layer 23, and a metal deuterated oxide layer 41. The isolation layer 17 is formed in the substrate 11, the first doped region 21a is formed on the isolation region 17 in the array region A1, the second doped region 21b is formed on the first doped region 21a, and the metal deuterated layer 23 is formed on On the second doped region 21b, a metal deuterated oxide layer 41 is formed on the metal deuterated layer 23.
在本實施例中,第一摻雜區域21a與第二摻雜區域21b的導電型相反。舉例來說,第一摻雜區域21a可為一P型摻雜區域,而第二摻雜區域21b可為一N型摻雜區域。然而,本發明並未限定於此。在另一實 施例中,第一摻雜區域21a可為一N型摻雜區域,而第二摻雜區域21b可為一P型摻雜區域。第1圖中所繪示的其他元件將於後方描述中介紹。 In the present embodiment, the first doped region 21a is opposite to the conductive type of the second doped region 21b. For example, the first doped region 21a may be a P-type doped region, and the second doped region 21b may be an N-type doped region. However, the invention is not limited thereto. In another reality In an embodiment, the first doped region 21a may be an N-type doped region, and the second doped region 21b may be a P-type doped region. Other components depicted in Figure 1 will be described in the following description.
第2A至2M圖繪示依據本發明之記憶體裝置100的一製造實施例。如第2A圖所示,提供一基板11。接著依序沉積一墊氧化層(pad oxide)13與一氮化矽層15於基板11上。形成一隔離層17於基板11、墊氧化層13與氮化矽層15內。在本實施例中,隔離層17可為一淺溝渠隔絕層(shallow trench isolation,STI)或一矽局部氧化(local oxidation of silicon,LOCOS)隔離層。 2A through 2M illustrate a manufacturing embodiment of a memory device 100 in accordance with the present invention. As shown in Fig. 2A, a substrate 11 is provided. Then, a pad oxide 13 and a tantalum nitride layer 15 are sequentially deposited on the substrate 11. An isolation layer 17 is formed in the substrate 11, the pad oxide layer 13, and the tantalum nitride layer 15. In this embodiment, the isolation layer 17 can be a shallow trench isolation (STI) or a local oxidation of silicon (LOCOS) isolation layer.
如第2B圖所示,移除氮化矽層15,且形成一P井19a與一N井19b於基板11中。N井19b係相鄰於P井19a。在本實施例中,P井19a與N井19b可以離子佈植(ion implantation)形成,且部分隔離層17可設置於P井19a與N井19b之間。 As shown in FIG. 2B, the tantalum nitride layer 15 is removed, and a P well 19a and an N well 19b are formed in the substrate 11. The N well 19b is adjacent to the P well 19a. In the present embodiment, the P well 19a and the N well 19b may be formed by ion implantation, and a portion of the isolation layer 17 may be disposed between the P well 19a and the N well 19b.
如第2C圖所示,墊氧化層13係被閘極氧化層14所取代,且閘極氧化層14沉積於P井19a與N井19b上。接著,沉積一多晶矽層21於基板11上,並形成一光阻層(photoresist layer)91於多晶矽層21上,以定義一陣列區A1與一周邊區A2。也就是說,多晶矽層21係形成於陣列區A1內的隔離層17上,且形成於周邊區A2內的閘極氧化層14與隔離層17上。 As shown in FIG. 2C, the pad oxide layer 13 is replaced by the gate oxide layer 14, and the gate oxide layer 14 is deposited on the P well 19a and the N well 19b. Next, a polysilicon layer 21 is deposited on the substrate 11, and a photoresist layer 91 is formed on the polysilicon layer 21 to define an array region A1 and a peripheral region A2. That is, the polysilicon layer 21 is formed on the isolation layer 17 in the array region A1, and is formed on the gate oxide layer 14 and the isolation layer 17 in the peripheral region A2.
如第2D圖所示,在陣列區A1中,形成一第一摻雜區域21a於多晶矽層21的底部,形成一第二摻雜區域21b於多晶矽層21的頂部,同時形成一未摻雜區域21c於第一摻雜區域21a與第二摻雜區域21b之間。也就是說,第二摻雜區域21b係形成於第一摻雜區域21a上,且藉由未摻 雜區域21c與第一摻雜區域21a分離。 As shown in FIG. 2D, in the array region A1, a first doped region 21a is formed on the bottom of the polysilicon layer 21, and a second doped region 21b is formed on the top of the polysilicon layer 21 while forming an undoped region. 21c is between the first doped region 21a and the second doped region 21b. That is, the second doped region 21b is formed on the first doped region 21a, and is not doped The impurity region 21c is separated from the first doping region 21a.
在此,第一摻雜區域21a的厚度可介於50與1000Å,而第二摻雜區域21b的厚度可介於50與1000Å。然而,本發明並未限定於此。第一摻雜區域21a與第二摻雜區域21b的厚度可依據記憶體裝置的需求決定。 Here, the thickness of the first doping region 21a may be between 50 and 1000 Å, and the thickness of the second doping region 21b may be between 50 and 1000 Å. However, the invention is not limited thereto. The thickness of the first doped region 21a and the second doped region 21b may be determined according to the requirements of the memory device.
在一實施例中,第一摻雜區域21a可為P型,而第二摻雜區域21b的導電型可為N型。然而,本發明並未限定於。在另一實施例中,第一摻雜區域21a可為N型,而第二摻雜區域21b的導電型可為P型。第一摻雜區域21a與第二摻雜區域21b的導電型係取決於記憶體裝置的操作方式。 In an embodiment, the first doped region 21a may be P-type, and the conductive type of the second doped region 21b may be N-type. However, the invention is not limited thereto. In another embodiment, the first doped region 21a may be N-type, and the conductive type of the second doped region 21b may be P-type. The conductivity type of the first doped region 21a and the second doped region 21b depends on the mode of operation of the memory device.
在本發明實施例中,第一摻雜區域21a、未摻雜區域21c與第二摻雜區域21b可作為一垂直二極體(vertical diode)。 In the embodiment of the present invention, the first doped region 21a, the undoped region 21c and the second doped region 21b can serve as a vertical diode.
此外,第一摻雜區域21a與第二摻雜區域21b可藉由離子佈植形成。由於離子佈植係於陣列區A1內執行,且與周邊區A2分離,因此,不會影響到周邊區A2內的元件。 In addition, the first doped region 21a and the second doped region 21b may be formed by ion implantation. Since the ion implantation is performed in the array area A1 and is separated from the peripheral area A2, the elements in the peripheral area A2 are not affected.
如第2E圖所示,移除光阻層91。接著,形成一金屬矽化層23於周邊區A2內的多晶矽層21上以及陣列區A1內的多晶矽層21之第二摻雜區域21b上。在本實施例中,金屬矽化層23可包括矽化鎢(tungsten silicide),可降低字元線阻值(word line resistance)。 As shown in FIG. 2E, the photoresist layer 91 is removed. Next, a metal deuteration layer 23 is formed on the polysilicon layer 21 in the peripheral region A2 and on the second doping region 21b of the polysilicon layer 21 in the array region A1. In the present embodiment, the metal deuteration layer 23 may include tungsten tungsten, which can reduce the word line resistance.
如第2F圖所示,圖案化周邊區A2內的部分多晶矽層21與金屬矽化層23,以形成複數孔洞25。蝕刻製程係停止於閘極氧化層14的頂面以及隔離層17的表面。 As shown in FIG. 2F, a portion of the polysilicon layer 21 and the metal germanium layer 23 in the peripheral region A2 are patterned to form a plurality of holes 25. The etching process is stopped on the top surface of the gate oxide layer 14 and the surface of the isolation layer 17.
如第2G圖所示,圖案化陣列區A1內的部分金屬矽化層23、多晶矽層21之未摻雜區域21c與第二摻雜區域21b,以形成複數孔洞27。蝕刻製程係停止於多晶矽層21之第一摻雜區域21a的頂面。在某些實施例中,第2F與2G圖的蝕刻製程可同時執行。 As shown in FIG. 2G, a portion of the metal deuterated layer 23, the undoped region 21c of the polysilicon layer 21, and the second doped region 21b in the patterned array region A1 are patterned to form a plurality of holes 27. The etching process is stopped at the top surface of the first doped region 21a of the polysilicon layer 21. In some embodiments, the etching processes of the 2F and 2G patterns can be performed simultaneously.
如第2H圖所示,形成間隔物29於孔洞25、27內,且間隔物29係密封孔洞27。也就是說,於陣列區A1內,間隔物29可形成於兩個金屬矽化層23之間。接著,形成兩個第一電極S1與D1於P井19a中,形成兩個第二電極S2與D2於N井19b中。在本實施例中,第一電極S1與D1及第二電極S2與D2係為相同(identical)。舉例來說,第一電極S1與D1及第二電極S2與D2可作為源極或汲極。 As shown in Fig. 2H, spacers 29 are formed in the holes 25, 27, and the spacers 29 seal the holes 27. That is, in the array area A1, the spacers 29 may be formed between the two metal deuterated layers 23. Next, two first electrodes S1 and D1 are formed in the P well 19a, and two second electrodes S2 and D2 are formed in the N well 19b. In the present embodiment, the first electrodes S1 and D1 and the second electrodes S2 and D2 are identical. For example, the first electrodes S1 and D1 and the second electrodes S2 and D2 can function as a source or a drain.
此外,形成一第一摻雜多晶矽層31a於P井19a上的閘極氧化層14上,且形成一第二摻雜多晶矽層31b於N井19b上的閘極氧化層14上。在本實施例中,第一摻雜多晶矽層31a可藉由離子佈植於P井19a上的多晶矽層31所形成,第二摻雜多晶矽層31b可藉由離子佈植於N井19b上的多晶矽層31所形成。也就是說,於周邊區A2內,金屬矽化層23可形成於第一摻雜多晶矽層31a與第二摻雜多晶矽層31b上。因此,可於周邊區A2內形成一雙閘極(dual-gate)金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)(PMOS與NMOS)。 Further, a first doped polysilicon layer 31a is formed on the gate oxide layer 14 on the P well 19a, and a second doped polysilicon layer 31b is formed on the gate oxide layer 14 on the N well 19b. In this embodiment, the first doped polysilicon layer 31a can be formed by ion implantation of the polysilicon layer 31 on the P well 19a, and the second doped polysilicon layer 31b can be implanted on the N well 19b by ions. The polysilicon layer 31 is formed. That is, in the peripheral region A2, the metal deuterated layer 23 may be formed on the first doped polysilicon layer 31a and the second doped polysilicon layer 31b. Therefore, a dual-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) (PMOS and NMOS) can be formed in the peripheral region A2.
在某些實施例中,可形成一第一延伸部S11、一第二延伸部D11、一第三延伸部S21及一第四延伸部D21。第一延伸部S11形成於P井19a,且連接第一電極S1。第二延伸部D11形成於P井19a,且連接第一電 極D1。第三延伸部S21形成於N井19b,且連接第二電極S2。第四延伸部D21形成於N井19b,且連接第二電極D2。在此,第一延伸部S11、第二延伸部D11、第三延伸部S21與第四延伸部D21可為源極/汲極延伸部或輕度摻雜汲極(lightly doped drain,LDD)。 In some embodiments, a first extension S11, a second extension D11, a third extension S21, and a fourth extension D21 can be formed. The first extension S11 is formed in the P well 19a and is connected to the first electrode S1. The second extension D11 is formed in the P well 19a and connected to the first electric Extreme D1. The third extension S21 is formed in the N well 19b and is connected to the second electrode S2. The fourth extension portion D21 is formed in the N well 19b and is connected to the second electrode D2. Here, the first extension portion S11, the second extension portion D11, the third extension portion S21 and the fourth extension portion D21 may be a source/drain extension or a lightly doped drain (LDD).
如第2I圖所示,形成一介電層(層間介電層,inter-layer dielectric,ILD)33於隔離層17上。在本實施例中,於周邊區A2內,孔洞25被介電層33所密封,且介電層33可形成於間隔物29與金屬矽化層23的表面。接著,可於介電層33上執行一化學機械研磨(chemical mechanical polishing/planarization,CMP)。 As shown in FIG. 2I, a dielectric layer (inter-layer dielectric, ILD) 33 is formed on the isolation layer 17. In the present embodiment, in the peripheral region A2, the holes 25 are sealed by the dielectric layer 33, and the dielectric layer 33 may be formed on the surfaces of the spacers 29 and the metal deuterated layer 23. Next, a chemical mechanical polishing (CMP) can be performed on the dielectric layer 33.
如第2J圖所示,於周邊區A2內形成複數個第一接點插塞35穿過介電層33。此外,接點插塞35於周邊區A2內可分別連接金屬矽化層23、第一電極S1、第二電極S2、第一電極D1及第二電極D2。 As shown in FIG. 2J, a plurality of first contact plugs 35 are formed in the peripheral region A2 through the dielectric layer 33. In addition, the contact plug 35 can respectively connect the metal deuteration layer 23, the first electrode S1, the second electrode S2, the first electrode D1 and the second electrode D2 in the peripheral region A2.
在本實施例中,第一接點插塞35可包括一CVD氮化鈦層與鎢(W)。在某些實施例中,第一接點插塞35可更包括一PVD鈦層。在此,CVD氮化鈦層可定義為包括氮化鈦的一層,此層係以化學氣相沉積(chemical vapor deposition,CVD)所形成,而PVD鈦層可定義為包括鈦的一層,此層係以物理氣相沉積(physical vapor deposition,PVD)所形成。 In the present embodiment, the first contact plug 35 may include a CVD titanium nitride layer and tungsten (W). In some embodiments, the first contact plug 35 can further include a PVD titanium layer. Here, the CVD titanium nitride layer may be defined as a layer including titanium nitride, which is formed by chemical vapor deposition (CVD), and the PVD titanium layer may be defined as a layer including titanium. It is formed by physical vapor deposition (PVD).
如第2K圖所示,形成一遮蔽層(cap layer)37於介電層33上,以保護周邊區A2內的第一接點插塞35。在一實施例中,遮蔽層37可包括氮化矽(SiN)。 As shown in FIG. 2K, a cap layer 37 is formed on the dielectric layer 33 to protect the first contact plug 35 in the peripheral region A2. In an embodiment, the shielding layer 37 may include tantalum nitride (SiN).
如第2L圖所示,於陣列區A1內形成複數穿孔39。在此,穿孔39可透過一蝕刻製程所形成,並裸露陣列區A1內之金屬矽化層23的 頂面。 As shown in Fig. 2L, a plurality of through holes 39 are formed in the array area A1. Here, the through holes 39 can be formed by an etching process, and the metal germanium layer 23 in the array area A1 is exposed. Top surface.
如第2M圖所示,於陣列區A1內形成一金屬矽化氧化層41於金屬矽化層23上。在本實施例中,金屬矽化氧化層41可以快速熱氧化(rapid thermal oxidation,RTO)或電漿氧化(plasma oxidation)所形成。舉例來說,金屬矽化層23可為矽化鎢(tungsten silicide,WSix)層,而矽化鎢層的頂部可被轉換為氮化氧化鎢(tungsten silicide oxide,WSixOy)層。 As shown in FIG. 2M, a metal deuterated oxide layer 41 is formed on the metal deuterated layer 23 in the array region A1. In the present embodiment, the metal deuterated oxide layer 41 can be formed by rapid thermal oxidation (RTO) or plasma oxidation. For example, the metal deuteration layer 23 may be a tungsten oxide silicide (WSi x ) layer, and the top of the tungsten germanium oxide layer may be converted into a tungsten oxide silicon oxide (WSi x O y ) layer.
接著,於陣列區A1形成複數個第二接點插塞43以密封穿孔39,並移除遮蔽層37,如此便形成了如第1圖所示之記憶體裝置100。此外,可執行一化學機械研磨(CMP)。在本實施例中,第二接點插塞43可連接陣列區A1內的金屬矽化氧化層41。 Next, a plurality of second contact plugs 43 are formed in the array area A1 to seal the through holes 39, and the shielding layer 37 is removed, thus forming the memory device 100 as shown in Fig. 1. Further, a chemical mechanical polishing (CMP) can be performed. In the present embodiment, the second contact plug 43 can be connected to the metal deuterated oxide layer 41 in the array area A1.
在本實施例中,第二接點插塞43可包括一PVD氮化鈦層、一CVD氮化鈦層與鎢(W)。在此,PVD氮化鈦層可定義為包括氮化鈦的一層,此層係以物理氣相沉積(PVD)所形成,而CVD氮化鈦層可定義為包括氮化鈦的一層,此層係以化學氣相沉積(CVD)所形成。 In the present embodiment, the second contact plug 43 may include a PVD titanium nitride layer, a CVD titanium nitride layer and tungsten (W). Here, the PVD titanium nitride layer may be defined as a layer including titanium nitride, which is formed by physical vapor deposition (PVD), and the CVD titanium nitride layer may be defined as a layer including titanium nitride. It is formed by chemical vapor deposition (CVD).
化學氣相沉積(CVD)利用選定的前驅物(precursor),形成碳插入(C-inserted)的氮化鈦,以沉積氮化鈦層;而物理氣相沉積(PVD)僅利用鈦與氮氣,形成純的氮化鈦層。對CVD氮化鈦而言,需要氫氣與氮氣電漿處理,以分解前驅物四二甲基氨基鈦(Tetra-dimethyl-amido-titanium,TDMAT)為Ti(C)N與副產物。此化學反應與電漿處理造成不純的氮化鈦,影響電極與瞬態層(transient film)的介面以及金屬矽化氧化物(例如:WSixOy)的品質。另一方面,PVD氮化鈦層的來源不包括多餘的元素,可形成強壯的介面且維持良好的金屬矽化氧化層結合。 Chemical vapor deposition (CVD) utilizes selected precursors to form C-inserted titanium nitride to deposit a titanium nitride layer, while physical vapor deposition (PVD) utilizes only titanium and nitrogen. A pure titanium nitride layer is formed. For CVD titanium nitride, hydrogen and nitrogen plasma treatment are required to decompose the precursor Tetra-dimethyl-amido-titanium (TDMAT) into Ti(C)N and by-products. This chemical reaction and plasma treatment result in impure titanium nitride, affecting the interface between the electrode and the transient film and the quality of the metal deuterated oxide (eg, WSi x O y ). On the other hand, the source of the PVD titanium nitride layer does not include excess elements, forms a strong interface and maintains a good metal deuterated oxide layer bond.
第3圖繪示記憶體裝置100在後續步驟中的示意圖。如第3圖所示,可形成金屬線45以電性連接第一接點插塞35與第二接點插塞43。 FIG. 3 is a schematic diagram showing the memory device 100 in a subsequent step. As shown in FIG. 3, a metal wire 45 may be formed to electrically connect the first contact plug 35 and the second contact plug 43.
第4圖繪示分別具有頂電極為PVD氮化鈦與CVD氮化鈦之氮化氧化鎢電阻式隨機存取記憶體之起始電阻(initial resistance)的比較。如第4圖所示,選擇PVD氮化鈦製程具有超過1000倍的改善。此外,PVD氮化鈦層可具有更高的起始電阻,這些結果證明PVD氮化鈦層可達到更強健的金屬氧化層或更佳的氮化鈦/淡化氧化鎢介面。 Figure 4 is a graph showing the comparison of the initial resistance of a nitrided tungsten oxide resistive random access memory having a top electrode of PVD titanium nitride and CVD titanium nitride, respectively. As shown in Figure 4, the PVD titanium nitride process has been selected to have an improvement of more than 1000 times. In addition, the PVD titanium nitride layer can have a higher initial resistance, and these results demonstrate that the PVD titanium nitride layer can achieve a more robust metal oxide layer or a better titanium nitride/desalination tungsten oxide interface.
第5圖繪示單極矽化氧化鎢電阻式隨機存取記憶體的R-V特性圖。施加負成形脈衝(forming pulse)以得到第一成形操作。成形操作需要比RESET與SET(介於50ns脈衝寬度(pulse width))更高的操作電壓。在初始時,新的裝置需要大電壓以從頂部至底部建立導電路徑。隨後的RESET與SET程序分別破壞與再生細絲的局部區域(local regions of filament)。可預期成形程序需要比RESET/SET切換行為更大的電壓。在成形後,矽化鎢電阻式隨機存取記憶體可於SET與RESET施加負脈衝切換為單極模式。於SET與RESET皆小於3V的操作電壓顯示出大於100倍的電阻切換窗口(switching window)。 Figure 5 is a graph showing the R-V characteristics of a unipolar deuterated tungsten oxide resistive random access memory. A forming pulse is applied to obtain a first forming operation. The forming operation requires a higher operating voltage than RESET and SET (with a 50 ns pulse width). At the beginning, the new device requires a large voltage to establish a conductive path from top to bottom. Subsequent RESET and SET programs destroy and regenerate the local regions of filament, respectively. The forming process can be expected to require a voltage greater than the RESET/SET switching behavior. After forming, the tungsten-tellurium resistive random access memory can be switched to the unipolar mode by applying a negative pulse to SET and RESET. The operating voltages that are less than 3V for both SET and RESET show a switching window that is greater than 100 times.
第6圖繪示提供SET/RESET脈衝至單極鎢電阻式隨機存取記憶體裝置的瞬態(transient)I-t圖。從示波器的瞬態I-t圖顯示,矽化鎢電阻式隨機存取記憶體裝置於脈衝時間50ns有良好的切換。SET與RESET電流分別為400μA與700μA,以達成SET(約100Kohms)至RESET(約1Mohms)電阻窗口(resistance window)。 Figure 6 is a diagram showing a transient I-t diagram of a SET/RESET pulse to a monopolar tungsten resistive random access memory device. From the transient I-t diagram of the oscilloscope, the tungsten-tellurium resistive random access memory device has a good switching at a pulse time of 50 ns. The SET and RESET currents are 400μA and 700μA, respectively, to achieve a SET (about 100Kohms) to RESET (about 1Mohms) resistance window.
第7圖繪示單極矽化氧化鎢電阻式隨機存取記憶體之成形 電壓作為成形脈衝寬度的函數。第7圖顯示當成形脈衝寬度增加時,成形電壓呈現一降低的趨勢。成形操作僅進行一次,因此較長的成形脈衝不會影響主要裝置操作速度。1μs成形脈衝可減少成形電壓至小於3V,如同沒有成形般的操作。 Figure 7 shows the formation of a unipolar deuterated tungsten oxide resistive random access memory. The voltage is a function of the shaped pulse width. Figure 7 shows that as the shaping pulse width increases, the forming voltage exhibits a decreasing tendency. The forming operation is performed only once, so a longer forming pulse does not affect the operating speed of the main device. A 1 μs shaping pulse reduces the forming voltage to less than 3 V, as if it were not shaped.
第8圖繪示單極矽化氧化鎢電阻式隨機存取記憶體的循環特性。如第8圖所示,循環耐久性(endurance)大於100可顯示大約10倍的電阻窗口(例如切換窗口100KΩ-1MΩ)。 Figure 8 is a graph showing the cycle characteristics of a unipolar deuterated tungsten oxide resistive random access memory. As shown in Fig. 8, the endurance of more than 100 can show a resistance window of about 10 times (for example, a switching window of 100 K? - 1 M?).
第9圖繪示在250℃持續一小時,RESET與SET狀態的資料保存能力。第9圖顯示在高溫烘烤後可維持良好的窗口,證明電阻式隨機存取記憶體具有良好的資料保存性。 Figure 9 shows the data retention capability of the RESET and SET states for one hour at 250 °C. Figure 9 shows that a good window can be maintained after baking at a high temperature, demonstrating that the resistive random access memory has good data retention.
如上所述之本發明實施例,已率先提出並製造單極金屬矽化氧化(例如:WSixOy)電阻式隨機存取記憶體。起始電阻藉由PVD氮化鈦產生極大進步,提供了最佳化裝置表現的新方向。好的單極表現可表現出快速切換速度、良好的資料包存以及10倍的切換窗口。 As described above for the embodiments of the present invention, monopolar metal deuterated oxide (e.g., WSi x O y ) resistive random access memory has been proposed and fabricated. The initial resistance is greatly improved by PVD titanium nitride, providing a new direction to optimize device performance. Good unipolar performance can show fast switching speed, good data storage and 10 times switching window.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
100‧‧‧記憶體裝置 100‧‧‧ memory device
11‧‧‧基板 11‧‧‧Substrate
14‧‧‧閘極氧化層 14‧‧‧ gate oxide layer
17‧‧‧隔離層 17‧‧‧Isolation
19a‧‧‧P井 19a‧‧‧P well
19b‧‧‧N井 19b‧‧‧N Well
21‧‧‧多晶矽層 21‧‧‧Polysilicon layer
21a‧‧‧第一摻雜區域 21a‧‧‧First doped region
21b‧‧‧第二摻雜區域 21b‧‧‧Second doped region
21c‧‧‧未摻雜區域 21c‧‧‧Undoped areas
23‧‧‧金屬矽化層 23‧‧‧Metalized layer
41‧‧‧金屬矽化氧化層 41‧‧‧Metal deuterated oxide layer
43‧‧‧第二接點插塞 43‧‧‧Second contact plug
A1‧‧‧陣列區 A1‧‧‧Array area
A2‧‧‧周邊區 A2‧‧‧ surrounding area
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US8035160B2 (en) * | 2006-11-13 | 2011-10-11 | Micron Technology, Inc. | Recessed access device for a memory |
US8828786B2 (en) * | 2009-05-19 | 2014-09-09 | Rohm Co., Ltd. | Method of fabricating photodiode |
US8446751B2 (en) * | 2009-11-09 | 2013-05-21 | Panasonic Corporation | Semiconductor memory device |
US8324673B2 (en) * | 2009-12-31 | 2012-12-04 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of forming the same |
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