TWI573269B - Semiconductor device - Google Patents

Description

Semiconductor component

The present application relates to a semiconductor device, and more particularly to a semiconductor device having a growth region and a growth suppression region.

Due to the development of Metal Organic Chemical Vapor Deposition (MOCVD) and Molecular Beam Epitaxy (MBE) technology, the technology for the growth of the Group III compound semiconductors has become more mature, among which Wide-gap compound materials with gallium nitride (GaN) and gallium nitride as GaN based materials are attracting attention. In addition to direct energy gap and wide energy gap, gallium nitride also has high breakdown electric field, high electron mobility, and high saturation electron moving speed. The above advantages make the gallium nitride semiconductor material applicable to optical semiconductor components, high voltage and high power semiconductor components, high speed electrons, and high temperature electrons. In addition, in the bandgap engineering of gallium nitride, a heterostructure of aluminum gallium nitride/gallium nitride can be used to generate a two-dimensional electron gas (2DEG) at the heterojunction. Due to the material properties of the nitrides described above, high electron mobility field effect transistors fabricated using aluminum gallium nitride/gallium nitride heterostructures have excellent potential for high frequency, high voltage and high power applications.

However, in the current semiconductor element having an aluminum gallium nitride/gallium nitride heterostructure In the fabrication of the device, a patterned mask layer is formed on the substrate before the semiconductor material is grown, and the patterned mask layer is not removed during the growth of the semiconductor material. Therefore, during the growth of the semiconductor material, the patterned mask layer is liable to cause contamination of the semiconductor material, resulting in low component characteristics.

The present application provides a semiconductor device having a growth region and a growth suppression region, and the semiconductor material can selectively grow from the growth region.

An embodiment of the present application provides a semiconductor device suitable for being disposed on a substrate. The semiconductor device includes a semiconductor device layer, at least a first electrode, and a second electrode. The semiconductor device layer includes a first portion and a second portion, wherein the first portion is disposed on the substrate. The first portion has a first surface, a plurality of growth inhibiting regions extending from the first surface to the inside, and a growth region adjacent to the growth inhibiting region. The second portion is disposed on the first surface to cover a portion of the growth zone. The second electrode is disposed on the second portion.

In an embodiment of the invention, the semiconductor device includes a light emitting diode, a photodiode, a rectifying diode, or a solar cell.

In an embodiment of the invention, the first portion includes a first type doped semiconductor layer, and the second portion includes an active layer and a second type doped semiconductor layer. Further, the active layer is between the first type doped semiconductor layer and the second type doped semiconductor layer.

In an embodiment of the invention, the first portion further includes a nucleation layer disposed between the substrate and the first type doped semiconductor layer.

In an embodiment of the invention, the first portion further includes a nucleation layer and a buffer layer, wherein the nucleation layer is disposed between the substrate and the first type doped semiconductor layer, and the buffer layer is disposed on the nucleation layer Between the substrate and the substrate.

In an embodiment of the invention, the semiconductor device described above includes a transistor.

In an embodiment of the invention, the second portion further covers an edge of the growth suppression zone.

In an embodiment of the invention, the growth inhibition zone has a depth of between 1 nm and 1000 nm.

In an embodiment of the invention, the resistivity of the growth zone is higher than the resistivity of the growth suppression zone.

In an embodiment of the invention, the semiconductor device further includes a protective layer to cover the semiconductor device layer.

Based on the above, in the design of the growth suppression zone and the growth zone of the present invention, the semiconductor material can be grown on the growth zone without the patterned mask layer. Since the present invention does not require the use of a patterned mask layer during the growth of the semiconductor material, the growth of the semiconductor material can be improved by the patterned mask layer, which leads to a problem of low component performance.

The above features and advantages of the present invention will become more apparent from the following description.

50‧‧‧Substrate

100, 200‧‧‧ semiconductor components

110‧‧‧Semiconductor component layer

112, 210‧‧‧ first part

113, 313‧‧‧ first surface

113a, 313a‧‧‧ growing areas

113b, 313b‧‧‧ growth inhibition zone

114, 220‧‧‧ Part II

120, 230‧‧‧ first electrode

130, 240‧‧‧ second electrode

211‧‧‧ nucleation layer

212‧‧‧First type doped semiconductor layer

213‧‧‧buffer layer

222‧‧‧Second type doped semiconductor layer

224‧‧‧ active layer

300‧‧‧High electron mobility transistor

311‧‧‧Channel material layer

311a‧‧‧Two-dimensional electronic cloud

312‧‧‧First barrier layer

314‧‧‧High resistance zone

316‧‧‧Intermediate

320‧‧‧second barrier layer

360‧‧‧Protective layer

D‧‧‧depth

D‧‧‧汲

G‧‧‧ gate

S‧‧‧ source

SL‧‧‧Ion barrier layer

PR, PR', PR2, PR3‧‧‧ photoresist layer

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the invention.

2 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.

3 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.

4 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.

FIG. 6 is a cross-sectional view of a high electron mobility transistor according to another embodiment of the invention.

FIG. 7 is a cross-sectional view of a high electron mobility transistor according to another embodiment of the invention.

FIG. 8 is a cross-sectional view of a high electron mobility transistor according to another embodiment of the invention.

9A-9M are schematic cross-sectional views showing a high electron mobility transistor process step according to another embodiment of the invention.

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the invention. Referring to FIG. 1 , the semiconductor device 100 of the present embodiment is adapted to be disposed on a substrate 50 , and the semiconductor device 100 includes a semiconductor device layer 110 , at least a first electrode 120 , and a second electrode 130 . Further, the semiconductor element layer 110 includes a first portion 112 and a second portion 114. The first portion 112 is disposed on the substrate 50, and the first portion 112 has a first surface 113, and a plurality of extending from the first surface 113 to the inside thereof The growth suppression zone 113b and the growth zone 113a adjacent to the growth suppression zone 113b. On the other hand, the second portion 114 is disposed on the first surface 113 of the first portion 112 to cover the growth region 113a. In addition, the first electrode 120 is disposed on the first surface 113 to cover a portion of the growth suppression region 113b, and the second electrode 130 is disposed on the second portion 114.

In the present embodiment, the substrate 50 is, for example, a germanium (Si) substrate, a tantalum carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or aluminum nitride ( AlN) substrate, gallium phosphide (GaP) substrate, gallium arsenide (GaAs) substrate or aluminum gallium arsenide (AlGaAs) substrate.

Further, in the present embodiment, the growth suppression region 113b of the first surface 113 is formed, for example, by ion implantation, impurity diffusion, or plasma treatment. For example, during ion implantation, the growth suppression zone 113b is subject to ion bombardment, causing the crystal lattice of the semiconductor material to scatter and change its lattice constant. Therefore, the subsequent semiconductor material will preferentially re-grow the growth region 113a of the first surface 113. In other words, the semiconductor material selectively grows on the first surface 113. Therefore, in this embodiment, in the process of growing the semiconductor material on the surface of the device, it is not necessary to further form a patterned mask layer on the first surface 113 of the semiconductor device 100. Therefore, the growth mode of the embodiment can prevent the mask layer material from causing contamination during the growth of the semiconductor material, thereby causing the component performance to be low. Further, in the present embodiment, the depth d of the growth suppression zone 113b is, for example, between 1 nm and 1000 nm. However, the present embodiment is not limited thereto, and the depth d of the growth suppression region 113b can be controlled by parameters such as ion implantation energy or ion species. Further, the resistivity of the growth suppression region 113b can be effectively reduced by the ion implantation described above, so that the resistivity of the growth suppression region 113b is smaller than that of the growth region 113a. It is to be noted that the growth suppression region 113b is in ohmic contact with the first electrode 120 covered thereon. In other words, the contact resistance between the growth suppression region 113b and the first electrode 120 can be low. In the present embodiment, the specific contact resistance between the growth suppression region 113b and the first electrode 120 is, for example, between 1 x 10 ^-2 Ω cm ² and 1 x 10 ^-6 Ω cm ² .

2 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. Referring to FIG. 2, in the present embodiment, the second portion 114 of the semiconductor element may further cover the edge of the growth suppression region 113b due to lateral growth. In addition, the extent to which the second portion 114 covers the growth suppression region 113b may vary depending on actual process conditions. This embodiment does not limit the area of the second portion 114 covering the growth suppression region 113b.

3 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. Referring to FIG. 3, in the present embodiment, the semiconductor device 200 is, for example, a light emitting diode, a photodiode, a rectifying diode, or a solar cell. In addition, the first portion 210 of the semiconductor device 200 includes the first type doped semiconductor layer 212 and the first electrode 230, and the second portion 220 of the semiconductor element includes the active layer 224, the second type doped semiconductor layer 222, and the second electrode 240. The active layer 224 is disposed between the first type doped semiconductor layer 212 and the second type doped semiconductor layer 222. For example, the first type doped semiconductor layer 212 is, for example, an N-type semiconductor doped layer, and the material thereof is, for example, gallium nitride (GaN) doped with germanium (Si) or germanium (Ge), and a method of forming the same, for example. It is a metalorganic chemical vapor deposition (MOCVD). In addition, the second type doped semiconductor layer 222 of the second portion 220 is, for example, a P-type doped layer, and the material thereof is, for example, gallium nitride doped with magnesium (Mg) or zinc (Zn), and the second type is doped. The hetero semiconductor layer 222 can also be formed by an organometallic chemical vapor deposition method. to make.

On the other hand, in the present embodiment, when the semiconductor element 200 is a light emitting diode, the active layer 224 is, for example, a light emitting layer, and the light emitting layer is, for example, a multiple quantum well layer. Further, the configuration of the multiple quantum well layers of the present embodiment can effectively improve the quantum efficiency of electron-hole bonding and further improve the luminous efficiency of the semiconductor device 200. In addition, when the semiconductor device 200 is a photodiode, the active layer 224 may be a light absorbing layer, that is, an intrinsic layer between the first type doped semiconductor layer 212 and the second type doped semiconductor layer 222 ( Intrinsic layer). Furthermore, when the semiconductor device 200 is a rectifying diode, the active layer 224 is an intrinsic layer between the first type doped semiconductor layer 212 and the second type doped semiconductor layer 222. In other embodiments, when the semiconductor device 200 is a solar cell, the active layer 224 can be a photosensitive layer sensitive to sunlight, that is, the first type doped semiconductor layer 212 and the second type doped semiconductor layer 222. A photoelectric conversion layer (or light absorbing layer).

4 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. Referring to FIG. 4 , in the embodiment, the first portion 210 of the semiconductor device 200 may further include a nucleation layer 211 , and the nucleation layer 211 is disposed between the substrate 50 and the first type doped semiconductor layer 212 . For example, the nucleation layer 211 of the present embodiment may be an aluminum nitride (AlN) layer.

FIG. 5 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. Referring to FIG. 5, in the embodiment, the first portion 210 of the semiconductor device 200 may further include a nucleation layer, in addition to the nucleation layer 211 disposed between the substrate 50 and the first type doped semiconductor 212. A buffer layer 213 between the 211 and the substrate 50. In the present embodiment, the buffer layer 213 is, for example, an undoped GaN layer. In addition, the buffer layer 213 of the present embodiment can improve the nucleation layer 211. The problem of lattice mismatch caused when growing on the heterogeneous substrate 50 is a problem of lattice mismatch. In this embodiment, the buffer layer 213 is formed by depositing gallium nitride (GaN), aluminum gallium nitride or nitrogen on the substrate 50, for example, by low temperature epitaxial growth or by physical deposition. The aluminum film layer has a thickness of between 1 nm and 100 nm. Furthermore, the aforementioned physical deposition method may be an electron beam (E-beam) or a sputtering method.

FIG. 6 is a cross-sectional view of a high electron mobility transistor according to another embodiment of the invention. Referring to FIG. 6 , the semiconductor device of the present embodiment is, for example, a high electron mobility transistor (HEMT) 300 , and the high electron mobility transistor 300 is suitable for being disposed on the substrate 50 . In the present embodiment, the high electron mobility transistor 300 includes a channel material layer 311, a first barrier layer 312, a second barrier layer 320, a source S, a drain D, and a gate G. The channel material layer 311 is disposed on the substrate 50, and the first barrier layer 312 is disposed on the channel material layer 311. Further, the first barrier layer 312 has a first surface 313, a plurality of growth suppression regions 313b extending from the first surface 313 toward the inside thereof, and a growth region 313a adjacent to the growth suppression region 313b. The second barrier layer 320 is disposed on the first surface 313 of the first barrier layer 312 to cover the growth region 313a. On the other hand, the gate G of the present embodiment is disposed on the second barrier layer 320.

In the present embodiment, the substrate 50 is, for example, a germanium (Si) substrate, a tantalum carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or aluminum nitride ( AlN) substrate, gallium phosphide (GaP) substrate, gallium arsenide (GaAs) substrate or aluminum gallium arsenide (AlGaAs) substrate. However, the embodiment is not limited thereto.

In the present embodiment, the growth suppression region 313b on the first surface 313 of the first barrier layer 312 may be ion implanted, impurity diffused or plasma as in the previous embodiment. The way of processing is formed. In addition, the depth d of the growth suppression zone 313b of the present embodiment may be between 1 nm and 1000 nm. However, the embodiment is not limited thereto. In addition, it is to be noted that the depth d of the aforementioned growth suppression region 313b is smaller than the thickness of the first barrier layer 312. Furthermore, the growth suppression zone 313b of the present embodiment is formed, for example, by ion implantation, wherein the implanted ion species are, for example, germanium (Si), phosphorus (P), arsenic (As), oxygen (O), and selenium. (Se), germanium (Ge), tellurium (Te), Ti (titanium) or a combination of the foregoing ions.

Further, according to the ion implantation described above, the present embodiment can reduce the resistivity of the growth suppression region 313b such that the resistivity of the growth suppression region 313b is smaller than the resistivity of the growth region 313a. In other words, a lower ohmic contact is formed between the growth suppression region 313b and the source S and the drain G overlying it.

In addition, in the present embodiment, the interface of the channel material layer 311 and the first barrier layer 312 can generate a high concentration of two dimensional electron gas 311a (2DEG). In this embodiment, the materials of the channel material layer 311 and the first barrier layer 312 are respectively undoped gallium nitride and undoped aluminum gallium nitride.

As shown in FIG. 6 , the source S and the drain D are respectively disposed on the growth suppression region 313 b of the second barrier layer 320 , and the gate G is disposed on the second barrier layer 320 , and The source S and the drain D are respectively located on both sides of the gate G. In the present embodiment, when the bias voltage G is not applied (i.e., when the gate voltage Vg is 0), the gate G causes the channel material layer 311 below it to be depleted. In other words, the two-dimensional electron cloud 311a present in the channel material layer 311 creates a depletion region under the gate, at which time the high electron mobility transistor 300 will assume a closed state. In contrast, when a forward voltage is applied to the gate G, the channel material layer 311 under the gate G The two-dimensional electron cloud 311a will appear, and the high electron mobility transistor 300 will be turned on. In other words, the high electron mobility transistor 300 of the present embodiment can be a normally off type semiconductor element, and it can be controlled to be turned on or off by applying an applied bias. This type of high electron mobility transistor 300 is generally referred to as an enhancement mode-mode (E-mode) high electron mobility transistor.

FIG. 7 is a cross-sectional view of a high electron mobility transistor according to another embodiment of the present invention. Referring to FIG. 7 , the high electron mobility transistor 300 of the present embodiment may further include an interlayer 316 disposed between the first barrier layer 312 and the channel material layer 311 . In the present embodiment, the intermediate layer 316 is, for example, an aluminum nitride (AlN) layer.

FIG. 8 is a cross-sectional view of a high electron mobility transistor according to another embodiment of the present invention. Referring to FIG. 8, in the embodiment, the first barrier layer 312 may further have a plurality of high resistance regions 314 extending from the first surface 313 toward the inside thereof, and the high resistance regions 314 are respectively located at the source S and the second Between the barrier layers 320 and between the drain D and the second barrier layer 320. In detail, the present embodiment can perform ion implantation on the first surface 313 between the source S and the second barrier layer 320 and between the drain D and the second barrier layer 320 to improve the area. A high resistance region 314 is formed in the first barrier layer 312 by a resistance value. The aforementioned high resistance region 314 can reduce the probability of leakage current between the gate G and the source S and/or between the gate G and the drain D. In the present embodiment, the ions used to form the high resistance region 314 are, for example, argon (Ar), zinc (Zn), bismuth (Be), nitrogen (N), hydrogen (H), helium (He), magnesium. (Mg), iron (Fe), manganese (Mn) or a combination of the foregoing ions. Further, the high resistance region 314 formed through the aforementioned ion implantation may have a resistance value higher than that of the growth region 313a. As described above, in the present embodiment, the resistance value of the high resistance region 314 is higher than the resistance value of the growth suppression region 313b.

9A-9M are schematic cross-sectional views showing a process of fabricating a semiconductor device in accordance with another embodiment of the present invention. Referring to FIGS. 9A and 9B, in the present example, the method of manufacturing the high electron mobility transistor 300 includes the following steps. First, a substrate 50 is provided. Next, a channel material layer 311 and a first barrier layer 312 are formed on the substrate 50 in sequence. The channel material layer 311 and the first barrier layer 312 are grown on the substrate 50, for example, by metal organic chemical vapor deposition (MOCVD). In addition, the surface of the channel material layer 311 of the present embodiment adjacent to the first barrier layer 312 can generate a high concentration of the two-dimensional electron cloud 311a. In this embodiment, the materials of the channel material layer 311 and the first barrier layer 312 are respectively undoped gallium nitride and undoped aluminum gallium nitride. On the other hand, the first surface 313 of the first barrier layer 312 can selectively form an ion stopping layer (SL) so that ions implanted in the process step of subsequent ion implantation can mostly stay at The first surface 313 of the first barrier layer 312 is on. Further, the material of the ion barrier layer SL of the present embodiment is, for example, cerium oxide (SiO 2 ), but the embodiment is not limited thereto.

Next, an ion implantation region is defined on the first surface 313 of the first barrier layer 312. In this embodiment, the ion implantation region is defined by, for example, forming a photoresist layer PR or a patterned material layer on the first surface, wherein a region not covered by the photoresist layer PR or the patterned material layer is defined as The ion implantation region, and the region covered by the photoresist layer PR or the patterned material layer is defined as a non-ion implantation region.

As shown in FIG. 9B, ion implantation is performed on the ion implantation region on the first surface 313. When the ion implantation is completed, the ion implantation region forms a growth suppression region 313b of the semiconductor material. In detail, the ion implantation region of the first surface 313 is subjected to ion bombardment during ion implantation, causing the semiconductor material crystal lattice of the ion implantation region to be scattered and changing its lattice constant. Therefore, in the follow-up In the process, the semiconductor material is less likely to grow on the ion implantation region than the non-ion implanted region, and the growth inhibiting region 313b of the semiconductor material is formed.

In contrast, the first surface 313 of the first barrier layer 312 covered by the photoresist layer PR is not damaged by the bombardment of ions, and the semiconductor material can smoothly grow on the surface of the region, thereby forming a growth region of the semiconductor material. 313a. In the present embodiment, the ion implantation mode of the growth suppression zone 313b is, for example, plasma ion implantation, and the implanted ions are, for example, germanium (Si), phosphorus (P), arsenic (As), oxygen (O), Selenium (Se), germanium (Ge), tellurium (Te), Ti (titanium) or a combination of the foregoing ions. However, the manner in which the growth suppression region 313b of the present embodiment is formed is not limited to the above-described manufacturing method.

Referring to FIG. 9C, after the ion implantation on the first barrier layer 312 is completed, the ion barrier layer SL and the photoresist layer PR covering the growth region 313a and the growth suppression region 313b are subsequently removed. In the present embodiment, the manner in which the ion barrier layer SL and the photoresist layer PR are removed is removed by chemical etching such as hydrofluoric acid (HF), acetone (ACE) or isopropyl alcohol (IPA). Further, after the ion implantation is completed in the growth suppression region 313b, the growth suppression region 313b can be subjected to a suitable thermal annealing treatment to generate a localized surface-dead surface, and simultaneously increase the electron concentration of the growth suppression region 313b. . Therefore, the growth suppression region 313b can have a good ohmic contact with the subsequently formed electrode after the thermal annealing treatment described above.

Referring to FIG. 9D, after defining the growth region 313a and the growth suppression region 313b on the first surface 313, a second barrier layer 320 is formed on the growth region 313a. For example. The second barrier layer 320 of the high electron mobility transistor 300 can be formed by metal organic chemical vapor deposition. Further, in the present embodiment, the second barrier layer 320 of the high electron mobility transistor 300 is, for example, a P-type gallium nitride layer.

Referring to FIG. 9E, the second barrier layer 320 of the embodiment is laterally formed. The second barrier layer 320 may further cover the edge of the growth suppression region 313b. In this embodiment, the extent to which the second barrier layer 320 covers the growth suppression region 313b may vary according to actual process conditions. This embodiment does not limit the area of the second barrier layer 320 covering the growth suppression region 313b.

Furthermore, referring to FIG. 9F to FIG. 9H, in the present embodiment, ion implantation can be selectively performed on the growth suppression regions 313b on both sides of the second barrier layer 320, and the implanted ions are, for example, argon (Ar). ), phosphorus (P), zinc (Zn), bismuth (Be), nitrogen (N), hydrogen (H), helium (He), magnesium (Mg), iron (Fe), manganese (Mn) or the aforementioned ions A combination or the like to form a high resistance region 314. The formation of the high resistance region 314 can prevent leakage current from being generated between the source S and the gate G or between the gate D and the gate G when the subsequent source S, the drain D, and the gate G are formed, and can be increased. The breakdown voltage of the high electron mobility transistor 300. As shown in FIG. 9F, the process of forming the high resistance region 314 includes forming a photoresist layer PR' on a portion of the growth suppression region 313b and the second barrier layer 320 to define a high resistance region 314 (FIG. 9G). The area shown). Next, the first surface 313 is selectively ion implanted with the photoresist layer PR' as a mask to form a high resistance region 314. Then, as shown in Fig. 9H, after ion implantation is completed, the photoresist layer PR' is removed by chemical etching such as acetone or isopropyl alcohol. In the embodiment, the process steps of forming the high resistance region 314 in FIG. 9F to FIG. 9H described above may be performed or omitted according to actual needs.

Next, referring to FIG. 9I, a photoresist layer PR2 is formed on the first surface 313 to define a formation position of the source S and the drain D on the growth suppression regions 313b on both sides of the second barrier layer 320. Thereafter, a metal electrode material is formed at a formation position defined by the growth suppression zone 313b. Then, as shown in FIG. 9J, for example, chemical etching The photoresist layer PR2 covering the first surface 313 is removed, and after the photoresist layer PR2 is removed, the source S and the drain D are formed on the growth suppression region 313b. In the present embodiment, the material of the source S and the drain D includes a metal such as a titanium aluminum (Ti/Al) alloy or a chromium gold (Cr/Au) alloy.

Next, referring to FIGS. 9K and 9L, after the source S and the drain D are formed, a photoresist layer PR3 is formed on the first surface 313 and a portion of the second barrier layer 320 to be defined on the second barrier layer 320. The position at which the gate G is formed. Next, a metal electrode material is formed at a position where the gate G is defined as described above. Then, the photoresist layer PR3 is removed, that is, the gate G is formed on the second barrier layer 320.

Finally, referring to FIG. 9M, after completing the above process steps, the embodiment may further form the protective layer 360 by, for example, plasma-assisted chemical vapor deposition (PECVD), wherein the protective layer 360 exposes the source S. With bungee D. So far, the fabrication of the high electron mobility transistor 300 is initially completed. It should be noted that the foregoing protective layer 360 is not a component and may be omitted according to actual needs.

As described above, in the above embodiments, the growth region and the growth suppression region are defined on the surface of the semiconductor element layer by ion implantation so that the semiconductor element can selectively grow on the growth region. Therefore, in the subsequent process of the semiconductor device, the present invention can preferentially grow the semiconductor material on the growth region without the aid of the patterned mask layer. Since the semiconductor device of the present invention does not need to use a patterned mask layer in the process of growing the semiconductor material, the contamination caused by the growth of the semiconductor material can be avoided and the performance is lowered.

Although the present application has been disclosed in the above embodiments, it is not intended to limit the present application, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present application. The scope of protection of this application It is subject to the definition of the scope of the patent application attached.

50‧‧‧Substrate

100‧‧‧Semiconductor components

110‧‧‧Semiconductor component layer

112‧‧‧Part I

113‧‧‧ first surface

113a‧‧‧ Growing Area

113b‧‧‧ Growth inhibition zone

114‧‧‧Part II

120‧‧‧first electrode

130‧‧‧second electrode

D‧‧‧depth

Claims (9)

A semiconductor device, configured to be disposed on a substrate, the semiconductor device comprising: a semiconductor device layer comprising a first portion and a second portion, wherein the first portion is disposed on the substrate, and the first portion has a first a surface, a plurality of growth suppression regions extending from the first surface toward the interior thereof, and a growth region adjacent to the growth suppression regions, wherein the second portion is disposed on the first surface to cover the growth region, And the second portion further covers the edges of the growth suppression regions; at least one first electrode is disposed on the first surface to cover a portion of the growth suppression region; and a second electrode is disposed on the second portion . The semiconductor device according to claim 1, wherein the semiconductor device comprises a light emitting diode, a photodiode, a rectifying diode or a solar cell. The semiconductor device of claim 2, wherein the first portion comprises a first type doped semiconductor layer, and the second portion comprises an active layer and a second type doped semiconductor layer, and the active layer Located between the first type doped semiconductor layer and the second type doped semiconductor layer. The semiconductor device of claim 3, wherein the first portion further comprises: a nucleation layer disposed between the substrate and the first type doped semiconductor layer. The semiconductor component according to claim 3, wherein the first component The portion further includes: a nucleation layer disposed between the substrate and the first type doped semiconductor layer; and a buffer layer disposed between the nucleation layer and the substrate. The semiconductor device of claim 1, wherein the semiconductor device comprises a transistor. The semiconductor device according to claim 1, wherein the growth suppression region has a depth of from 1 nm to 1000 nm. The semiconductor device according to claim 1, wherein a resistivity of each of the growth regions is higher than a resistivity of the growth suppression region. The semiconductor device according to claim 1, further comprising: a protective layer covering the semiconductor device layer.