TWI573112B - Display device - Google Patents

Description

Display device

The present invention relates to a display device, and more particularly to a display device that compensates for the characteristic impedance of a film on film (COF).

In some display devices, in order to meet the requirements of a narrow bezel, the display panel is connected to a circuit board provided with a timing controller through a thin film flip chip package structure, and the driving chip is disposed on the thin film flip chip package structure. Generally speaking, if the performance of the driving chip is to be measured, the test point should be located on the driving chip, but since it is not easy to measure the signal on the film flip-chip package structure, the test point is generally set on the circuit board. However, the performance measured at these two endpoints is not the same, and the actual performance of the driven wafer is usually higher than the measured performance. Therefore, those of ordinary skill in the art are still seeking to see if there is a design that can solve this problem.

Embodiments of the present invention provide a display device including a display panel, a wafer, a circuit board, and a film flip chip package structure. The film flip chip package structure is connected between the display panel and the circuit board, and the wafer is disposed on the film cover On the crystal package structure. The thin film flip chip package structure includes a first signal line and a second signal line connected to the chip, and a spacing between the first signal line and the second signal line is greater than a line width of the first signal line and the second signal line.

In an embodiment, the spacing between the first signal line and the second signal line is greater than 1.5 times the line width.

In an embodiment, the thin film flip chip package structure further includes a first ground line and a second ground line. The first ground line is disposed on the other side of the first signal line relative to the second signal line, and the second ground line is disposed on the other side of the second signal line relative to the first signal line. The first spacing between the first signal line and the first ground line is greater than the line width, and the second spacing between the second signal line and the second ground line is also greater than the line width.

In one embodiment, the spacing between the first signal line and the second signal line is proportional to the length of the thin film flip chip package from the wafer to the length of the circuit board.

In one embodiment, the spacing between the first signal line and the second signal line is inversely proportional to the impedance of the wafer.

In one embodiment, the spacing and line width between the first signal line and the second signal line are maintained at each position on the film flip chip package structure.

In one embodiment, the characteristic impedance of the thin film flip chip package structure is greater than the system impedance of the display device.

In one embodiment, the thin film flip chip package has a characteristic impedance greater than 100 ohms.

To make the above features and advantages of the present invention more apparent, The following specific embodiments are described in detail below with reference to the accompanying drawings.

100‧‧‧ display device

110‧‧‧ display panel

120‧‧‧ wafer

130‧‧‧film flip chip package structure

140‧‧‧ boards

150‧‧‧Soft cable

151‧‧‧Endpoint

152‧‧‧Test points

160‧‧‧Sequence Controller

210‧‧‧Voltage difference

310, 340‧‧‧ ground

320, 330‧‧‧ signal line

410‧‧‧voltage difference

S, S1, S2‧‧‧ spacing

W‧‧‧Line width

FIG. 1A is a side view showing a display panel according to an embodiment.

FIG. 1B is a top view showing a display panel according to an embodiment.

[Fig. 2A] and [Fig. 2B] depict eye diagrams measured from different endpoints.

FIG. 3 is a schematic view showing a circuit on a film flip chip package structure according to an embodiment.

FIG. 4 is an eye diagram after increasing the characteristic impedance of the thin film flip chip package structure 130 according to an embodiment.

The terms "first", "second", "etc." used in this document are not intended to mean the order or the order, and are merely to distinguish between elements or operations described in the same technical terms.

FIG. 1A is a side view showing a display panel according to an embodiment. FIG. 1B is a top plan view of a display panel according to an embodiment. Referring to FIGS. 1A and 1B , the display device 100 includes a display panel 110 , a wafer 120 , a thin film flip chip package structure 130 , and a circuit board 140 . The display device 100 can be implemented as a television, a mobile phone screen, a computer screen, etc., or the display device 100 can also be implemented as a semi-finished product (for example, without including a casing), and the present invention does not limit what the display device 100 is.

The display panel 110 can be a liquid crystal (Liquid Crystal) Display, LCD) display panel, Organic Light-Emitting Diode (OLED) display panel, or other suitable display panel, the invention is not limited thereto. The wafer 120 is, for example, a gate or source drive wafer disposed on the thin film flip chip package structure 130. The thin film flip chip package structure 130 is connected between the display panel 110 and the circuit board 140. In some embodiments, the circuit board 140 is coupled to the timing controller 160 via a flexible flat cable (FFC) 150, although the invention does not limit the material of the circuit board 140 to the components disposed on the circuit board 140.

In theory, the performance of the wafer 120 can be measured at the end point 151, but since the wafer 120 is disposed on the thin film flip chip package 130 and cannot be measured on the end point 151, it is typically selected at the test point 152. The performance of the wafer 120 is measured. For example, the measured signal can be drawn as an eye diagram. When the eye is relatively open, it indicates better performance. Conversely, if the eye is closed, the performance is poor. 2A depicts an eye diagram measured from test point 152, and FIG. 2B depicts a virtually eye diagram of wafer 120. As can be seen from FIG. 2A and FIG. 2B, the eye diagram of FIG. 2B is relatively open, but The eye pattern of 2A is relatively closed because the impedance on the circuit board 140 is generally high (for example, 100 ohms), but the impedance of the thin film flip chip package 130 and the wafer 120 is low, so when the signal is transmitted from high impedance. There is a reverse reflection at low impedance, causing the phenomenon of Figure 2A. In this embodiment, the characteristic impedance of the film flip chip package structure 130 is increased, so that the problem of FIG. 2A can be improved.

3 is a schematic view showing a circuit on a film flip-chip package structure according to an embodiment, it is noted that FIG. 3 is not drawn according to actual dimensions. Show. Referring to FIG. 3, in this embodiment, the thin film flip chip package structure 130 includes a first signal line 320, a second signal line 330, a first ground line 310, and a second ground line 340. The signal lines are connected to Wafer 120. The first ground line 310 is disposed on the other side of the first signal line 320 relative to the second signal line 330, and the second ground line 340 is disposed on the other side of the second signal line 330 relative to the first signal line 320. . The first signal line 320 and the second signal line 330 have a line width W; the first signal line 320 and the second signal line 330 have a spacing S; and the first ground line 310 and the first signal line 320 have a spacing S1 ( Also known as the first pitch); the second signal line 330 and the second ground line 340 have a spacing S2 (also referred to as a second spacing). In this embodiment, the first signal line 320 and the second signal line 330 have the same line width, and the first spacing S1 is the same as the second spacing S2, but in other embodiments, the values may also be different. Not limited to this.

In particular, these line widths and pitches are related to the characteristic impedance of the film flip chip package structure 130. Specifically, when the pitch S is larger, the characteristic impedance of the film flip chip package structure 130 is larger; when the line width W is larger, the characteristic impedance of the film flip chip package structure 130 is smaller; when the first pitch S1 is The greater the second pitch S2, the greater the characteristic impedance of the thin film flip chip package structure 130. Therefore, if the pitch S is increased, the line width W is decreased, the pitch S1 is increased, or a combination thereof, the characteristic impedance of the film flip chip package structure 130 can be increased.

In some embodiments, the thin film flip chip package structure 130 is not provided with the first ground line 310 and the second ground line 340. In these embodiments, the spacing S will be greater than the line width W. In some embodiments, the spacing S will be greater than 1.5 times the line width W. For example, the line width W can be 27 nm, and the spacing S can be 189. Nano. If the first ground line 310 and the second ground line 340 are disposed on the film flip chip package structure 130, in some embodiments, the pitch S may be greater than the line width W, and the pitches S1, S2 may be greater than the line width W. For example, the line width W may be 27 nm, the pitch S may be 189 nm, and the pitch S1, S2 may be 300 nm. It should be noted that the above-mentioned line width W, spacing S, S1, S2 are merely examples, and those skilled in the art can adjust the appropriate line width W and spacing S, S1, S2 when the experiment is not sufficient.

In the above embodiment, the characteristic impedance of the thin film flip chip package structure 130 is increased by adjusting the line width W and the pitches S, S1, S2, but other factors may affect the required adjustment amount. For example, when the impedance of the wafer 120 is higher, the thin film flip chip package structure 130 does not require too high characteristic impedance, and the required adjustment amount is lowered, so that the pitch S can be set inversely proportional to the impedance of the wafer 120 to avoid When the impedance of the wafer 120 is large, the characteristic impedance of the thin film flip chip package structure 130 is increased too much to form an over design. In addition, when the length of the film flip chip package structure 130 (the length from the wafer 120 to the circuit board 140) is small, the characteristic impedance of the film flip chip package structure 130 itself is also increased, and the required adjustment amount is reduced. Therefore, the pitch S can be set to be proportional to the length from the wafer 120 to the circuit board 140 on the thin film flip chip package structure 130. Since the length of the film flip chip package structure 130 varies with the size of the display device 100, the pitch S is adjusted in accordance with the size of the display device 100 in this embodiment. It is to be noted that in the above embodiment in which the pitch S is increased or decreased, the pitch S is still greater than the line width W, for example, greater than 1.5 times the line width W.

Referring back to FIG. 1B, in some conventional techniques, in the film Where the flip chip package structure 130 is adjacent to the wafer 120, the pitch of the lines on the thin film flip chip package structure 130 may be relatively small. In some embodiments, the pitches S, S1, S2 and the line width W described above are maintained at each position of the film flip chip package structure 130. However, in other embodiments, different spacings S, S1, S2 and line width W may be present at different locations, and the invention is not limited thereto.

On the other hand, as long as the characteristic impedance of the film flip chip package structure 130 is increased, the problem of eye pattern closure in FIG. 2A can be improved. In some embodiments, the characteristic impedance of the thin film flip chip package structure 130 is greater than the system impedance of the display device 100. For example, the characteristic impedance of the thin film flip chip package structure 130 may be greater than 100 ohms. Those skilled in the art will understand how to vary the spacings S, S1, S2 and line width W described above such that the characteristic impedance of the thin film flip chip package 130 can be greater than 100 ohms. Alternatively, different materials may be used, so that the characteristic impedance of the film flip chip package structure 130 is greater than 100 ohms. For example, a material having a larger dielectric constant has a larger characteristic impedance, but the present invention does not limit the film flip chip package structure. 130 What materials are used.

4 is an eye diagram after increasing the characteristic impedance of the thin film flip chip package structure 130, in accordance with an embodiment. Referring to FIG. 2A and FIG. 4, after increasing the characteristic impedance of the thin film flip chip package structure 130 according to the above embodiment, it can be seen that the same is measured from the test point 152, but the voltage difference 410 of FIG. 4 is greater than the voltage difference of FIG. 2A. 210, indicating that the eye diagram of FIG. 4 is more open than the eye diagram of FIG. 2A.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art is not The scope of the present invention is defined by the scope of the appended claims.

130‧‧‧film flip chip package structure

310, 340‧‧‧ ground

320, 330‧‧‧ signal line

S, S1, S2‧‧‧ spacing

W‧‧‧Line width

Claims (8)

A display device comprising: a display panel; a circuit board; a film flip chip package structure, connected between the display panel and the circuit board, comprising a first signal line and a second signal line; and a chip, The first signal line and the second signal line are connected to the chip, and a distance between the first signal line and the second signal line is greater than the first signal line and The line of the second signal line is one line wide. The display device of claim 1, wherein the spacing between the first signal line and the second signal line is greater than 1.5 times the line width. The display device of claim 1, wherein the film flip chip package structure further includes a first ground line and a second ground line, wherein the first ground line is disposed on the first signal line relative to the first On the other side of the second signal line, the second ground line is disposed on the other side of the second signal line relative to the first signal line, and a first between the first signal line and the first ground line The spacing is greater than the line width, and a second spacing between the second signal line and the second ground line is greater than the line width. The display device of claim 1, wherein the spacing between the first signal line and the second signal line is measured from the wafer to a length of the circuit board on the film flip chip package structure. In direct proportion. The display device of claim 1, wherein the spacing between the first signal line and the second signal line is inversely proportional to an impedance of the wafer. The display device of claim 1, wherein the spacing between the first signal line and the second signal line and the line width are maintained at each position on the film flip chip package structure. constant. The display device of claim 1, wherein a characteristic impedance of the thin film flip chip package structure is greater than a system impedance of the display device. The display device of claim 7, wherein the characteristic impedance of the thin film flip chip package structure is greater than 100 ohms.