TWI571686B - Pixel electrode - Google Patents

Pixel electrode Download PDF

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Publication number
TWI571686B
TWI571686B TW105131450A TW105131450A TWI571686B TW I571686 B TWI571686 B TW I571686B TW 105131450 A TW105131450 A TW 105131450A TW 105131450 A TW105131450 A TW 105131450A TW I571686 B TWI571686 B TW I571686B
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pixel electrode
slits
slit
boundary
adjacent
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TW105131450A
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Chinese (zh)
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TW201814380A (en
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徐嘉均
郭玉苹
鄭景升
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友達光電股份有限公司
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Priority to TW105131450A priority Critical patent/TWI571686B/en
Priority to CN201611044356.0A priority patent/CN106405952A/en
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Publication of TW201814380A publication Critical patent/TW201814380A/en

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • G02F1/134372Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Geometry (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)

Description

畫素電極Pixel electrode

本發明係關於一種畫素電極。The present invention relates to a pixel electrode.

液晶顯示面板由於具有輕薄短小與節能等優點,已被廣泛地應用在各式電子產品及可攜式電子產品,如智慧型手機(smart phone)、筆記型電腦(notebook computer)、平板電腦(tablet PC)與電視(TV)等。一般而言,當液晶顯示面板中的電極被提供電壓時,會驅使液晶分子旋轉,並藉此控制光線的穿透率,進而達成畫面顯示。Due to its advantages of lightness, thinness, and energy saving, liquid crystal display panels have been widely used in various electronic products and portable electronic products, such as smart phones, notebook computers, and tablets. PC) and TV (TV), etc. In general, when the electrodes in the liquid crystal display panel are supplied with a voltage, the liquid crystal molecules are driven to rotate, and thereby the transmittance of the light is controlled, thereby achieving a screen display.

本發明之目的之一在於提供一種畫素電極,其電極形狀透過特殊的圖案化設計以降低液晶反應時間,進而提升液晶顯示面板的顯示畫面的流暢度。One of the objects of the present invention is to provide a pixel electrode whose electrode shape is transparently designed to reduce the liquid crystal reaction time, thereby improving the smoothness of the display screen of the liquid crystal display panel.

本發明之一實施例提供一種畫素電極,包括複數個狹縫。狹縫之其中一個具有第一虛擬距離a以及第二虛擬距離b,第一虛擬距離a平行於第一方向,第二虛擬距離b平行於第二方向,其中第一方向實質上不同於第二方向,第二方向實質上垂直於光軸方向,且2/(3W)≦a/b≦(3W)/2,而W係為子畫素之寬度。An embodiment of the invention provides a pixel electrode comprising a plurality of slits. One of the slits has a first virtual distance a and a second virtual distance b, the first virtual distance a being parallel to the first direction, the second virtual distance b being parallel to the second direction, wherein the first direction is substantially different from the second The direction, the second direction is substantially perpendicular to the optical axis direction, and 2/(3W)≦a/b≦(3W)/2, and W is the width of the sub-pixel.

本發明之至少一實施例之畫素電極由於具有特殊的狹縫圖案設計,並且第一虛擬距離a與第二虛擬距離b具有2/(3W)≦a/b≦(3W)/2的關係,因此相較於傳統之畫素電極具有較強的平行於第一方向之邊緣電場,形成較短的暗紋距離。The pixel electrode of at least one embodiment of the present invention has a special slit pattern design, and the first virtual distance a and the second virtual distance b have a relationship of 2/(3W)≦a/b≦(3W)/2. Therefore, compared with the conventional pixel electrode, the electric field is stronger parallel to the edge of the first direction, forming a shorter dark line distance.

請參考第1圖,第1圖繪示本發明一實施例之液晶顯示面板的剖面示意圖,其中本發明之液晶顯示面板係以邊緣電場切換型(Fringe Field Switching, FFS)之液晶顯示面板為例,但不以此為限。如第1圖所示,本實施例之液晶顯示面板包括第一基板10、第二基板20、液晶層30、主動電路結構層40,以下將依序介紹上述元件之結構以及彼此之相對設置關係。第二基板20與第一基板10相對設置,而第一基板10與第二基板20係為透明基板例如玻璃基板、塑膠基板、石英基板、藍寶石基板或其它適合的硬質基板或可撓式基板,液晶層30設置於第一基板10與第二基板20之間,且液晶層30包括複數個液晶分子,主動電路結構層40設置於第一基板10上,並位於第一基板10與液晶層30之間。在本實施例中,主動電路結構層40包括第一絕緣層42、共用電極層44、第二絕緣層46以及畫素電極層48,並依序堆疊於第一基板10上,且主動電路結構層40具有複數個畫素,而各畫素可包括至少一個子畫素,其中共用電極層44與畫素電極層48的材料可為透明導電材料,例如氧化銦錫、氧化銦鋅或其它適合的透明導電材料,而畫素電極層48可包括複數個畫素電極,共用電極層44可包括至少一共用電極,且共用電極層44與畫素電極電性絕緣並分別被提供不同的電位,藉此形成邊緣電場,以控制液晶分子的旋轉。此外,本實施例之主動電路結構層40可另包括複數個開關元件、複數條掃描線、複數條資料線,各開關元件可分別與對應之掃描線、資料線、畫素電極電性連接,因此,可藉由掃描線所提供之開/關訊號控制開關元件,使得資料線所傳送之顯示灰階訊號得以傳送至對應的畫素電極,進而造成液晶分子的對應旋轉。除此之外,本實施例之液晶顯示面板可另包括彩色濾光層50、遮光層(或稱黑色矩陣層)60以及偏光片70,彩色濾光層50與遮光層60可設置於第二基板20上,但不以此為限,彩色濾光層50與遮光層60也可設置於第一基板10上或是分別設置於不同基板上,藉由彩色濾光層50以顯示彩色畫面,而遮光層60用以遮蔽漏光與非透光區,偏光片70可設置於第一基板10外側表面以及第二基板20外側表面,以搭配液晶分子的旋轉而達成灰階顯示。值得說明的是,本發明之液晶顯示面板並不以上述結構為限,其他可能之結構例如COA、BOA等亦在本發明所屬之範疇內。Please refer to FIG. 1 . FIG. 1 is a cross-sectional view of a liquid crystal display panel according to an embodiment of the present invention. The liquid crystal display panel of the present invention is a liquid crystal display panel of a fringe field switching type (FFS). , but not limited to this. As shown in FIG. 1, the liquid crystal display panel of the present embodiment includes a first substrate 10, a second substrate 20, a liquid crystal layer 30, and an active circuit structure layer 40. The structure of the above components and their relative arrangement relationship will be sequentially described below. . The second substrate 20 is disposed opposite to the first substrate 10, and the first substrate 10 and the second substrate 20 are transparent substrates such as a glass substrate, a plastic substrate, a quartz substrate, a sapphire substrate, or other suitable rigid substrate or flexible substrate. The liquid crystal layer 30 is disposed between the first substrate 10 and the second substrate 20, and the liquid crystal layer 30 includes a plurality of liquid crystal molecules. The active circuit structure layer 40 is disposed on the first substrate 10 and located on the first substrate 10 and the liquid crystal layer 30. between. In this embodiment, the active circuit structure layer 40 includes a first insulating layer 42 , a common electrode layer 44 , a second insulating layer 46 , and a pixel electrode layer 48 , and is sequentially stacked on the first substrate 10 , and the active circuit structure The layer 40 has a plurality of pixels, and each pixel may include at least one sub-pixel, wherein the material of the common electrode layer 44 and the pixel electrode layer 48 may be a transparent conductive material, such as indium tin oxide, indium zinc oxide or other suitable The transparent conductive material, and the pixel electrode layer 48 may include a plurality of pixel electrodes, the common electrode layer 44 may include at least one common electrode, and the common electrode layer 44 is electrically insulated from the pixel electrodes and respectively provided with different potentials, Thereby, a fringe electric field is formed to control the rotation of the liquid crystal molecules. In addition, the active circuit structure layer 40 of the embodiment may further include a plurality of switching elements, a plurality of scanning lines, and a plurality of data lines, and each of the switching elements may be electrically connected to the corresponding scanning line, the data line, and the pixel electrode, respectively. Therefore, the switching element can be controlled by the on/off signal provided by the scan line, so that the display gray scale signal transmitted by the data line can be transmitted to the corresponding pixel electrode, thereby causing corresponding rotation of the liquid crystal molecules. In addition, the liquid crystal display panel of the present embodiment may further include a color filter layer 50, a light shielding layer (or black matrix layer) 60, and a polarizer 70. The color filter layer 50 and the light shielding layer 60 may be disposed on the second layer. On the substrate 20, but not limited thereto, the color filter layer 50 and the light shielding layer 60 may be disposed on the first substrate 10 or on different substrates respectively, and the color filter layer 50 is used to display a color picture. The light shielding layer 60 is used to shield the light leakage and non-light transmission regions. The polarizer 70 can be disposed on the outer surface of the first substrate 10 and the outer surface of the second substrate 20 to achieve gray scale display in conjunction with the rotation of the liquid crystal molecules. It should be noted that the liquid crystal display panel of the present invention is not limited to the above structure, and other possible structures such as COA, BOA, etc. are also within the scope of the present invention.

請參考第2A圖,第2A圖繪示本發明第一實施例之畫素電極的上視示意圖。如第2A圖所示,本實施例之畫素電極100包括複數個狹縫110,為方便說明,本實施例係以10個狹縫為例,但不以此為限。狹縫110具有平行於第一方向D1的第一虛擬距離a以及平行於第二方向D2的第二虛擬距離b,其中第一方向D1實質上不平形於第二方向D2,第二方向D2實質上垂直於其中一個偏光片(例如上述第1圖中上位於第一基板10之外側表面的偏光片70或位於第二基板20之外側表面的偏光片70)之光軸方向,且2/(3W)≦a/b≦(3W)/2,而W係為子畫素之寬度,在本實施例中,寬度W為子畫素在第一方向D1上的寬度,但不以此為限。此外,在本實施例中,狹縫110在第二方向D2上具有兩種以上之寬度,但不以此為限。詳細而言,狹縫110可包括至少一個單元圖案110U,而第一虛擬距離a為單元圖案110U於第一方向D1上之寬度,第二虛擬距離b為單元圖案110U在第二方向D2上的最小寬度。在本實施例中,狹縫110僅包括單一個單元圖案110U,第一方向D1與第二方向D2互相垂直,也就是說,第一方向D1平行於其中一偏光片70之光軸方向,但不以此為限。另外,進一步說明,單元圖案110U可具有第一側邊111、第二側邊112、第三側邊113以及第四側邊114,其中第一側邊111與第二側邊112相互連接,第三側邊113與第四側邊114相互連接,第一側邊111與第四側邊114在第二方向D2上互相對應,第二側邊112與第三側邊113在第二方向D2上互相對應,並且,第一側邊111以及第三側邊113實質上平行第三方向D3,第二側邊112以及第四側邊114實質上平行第四方向D4,而第一方向D1、第二方向D2、第三方向D3以及第四方向D4不互相平行,也就是說,第一側邊111、第二側邊112、第三側邊113以及第四側邊114相對於偏光片70之光軸方向為不平行也不垂直,因此,單元圖案110U在第二方向D2上之寬度呈連續性變化,在較佳實施例中,第一側邊111與第二側邊112之間的夾角α為約160度,但不以此為限。除此之外,本實施例之單元圖案110U可另具有第五側邊115以及第六側邊116,其中第五側邊115連接於第一側邊111與第四側邊114之間,第六側邊116連接於第二側邊112與第三側邊113之間,且第五側邊115與第六側邊116實質上平行第二方向D2。相鄰狹縫110的較佳為以相對平行於第一方向D1之一假想線而對稱。在本實施例中,狹縫110的形狀可為封閉圖形,亦即狹縫110之單元圖案110U可為封閉圖形,如第2A圖中之六邊形狹縫,但不以此為限,舉例而言,封閉圖形可為梯形、矩形、六邊形、八邊形、橢圓形、長條形或其他適合的多邊形,且其內角為直角或鈍角。Please refer to FIG. 2A. FIG. 2A is a schematic top view of the pixel electrode of the first embodiment of the present invention. As shown in FIG. 2A, the pixel electrode 100 of the present embodiment includes a plurality of slits 110. For convenience of description, the present embodiment uses 10 slits as an example, but is not limited thereto. The slit 110 has a first virtual distance a parallel to the first direction D1 and a second virtual distance b parallel to the second direction D2, wherein the first direction D1 is substantially non-flat in the second direction D2, and the second direction D2 is substantially The direction perpendicular to the optical axis of one of the polarizers (for example, the polarizer 70 on the outer surface of the first substrate 10 or the polarizer 70 on the outer surface of the second substrate 20 in the above-mentioned first FIG. 1) is 2/( 3W) ≦a/b≦(3W)/2, and W is the width of the sub-pixel. In the embodiment, the width W is the width of the sub-pixel in the first direction D1, but not limited thereto. . In addition, in the embodiment, the slit 110 has two or more widths in the second direction D2, but is not limited thereto. In detail, the slit 110 may include at least one unit pattern 110U, and the first virtual distance a is the width of the unit pattern 110U in the first direction D1, and the second virtual distance b is the unit pattern 110U in the second direction D2. Minimum width. In the present embodiment, the slit 110 includes only a single unit pattern 110U, and the first direction D1 and the second direction D2 are perpendicular to each other, that is, the first direction D1 is parallel to the optical axis direction of one of the polarizers 70, but Not limited to this. In addition, the unit pattern 110U may have a first side 111, a second side 112, a third side 113, and a fourth side 114, wherein the first side 111 and the second side 112 are connected to each other, The three sides 113 and the fourth side 114 are connected to each other. The first side 111 and the fourth side 114 correspond to each other in the second direction D2, and the second side 112 and the third side 113 are in the second direction D2. Corresponding to each other, and the first side 111 and the third side 113 are substantially parallel to the third direction D3, and the second side 112 and the fourth side 114 are substantially parallel to the fourth direction D4, and the first direction D1, The two directions D2, the third direction D3, and the fourth direction D4 are not parallel to each other, that is, the first side 111, the second side 112, the third side 113, and the fourth side 114 are opposite to the polarizer 70. The direction of the optical axis is not parallel or perpendicular, and therefore, the width of the unit pattern 110U in the second direction D2 varies continuously. In the preferred embodiment, the angle between the first side 111 and the second side 112 α is about 160 degrees, but not limited to this. In addition, the unit pattern 110U of the embodiment may further have a fifth side 115 and a sixth side 116, wherein the fifth side 115 is connected between the first side 111 and the fourth side 114, The six side edges 116 are connected between the second side edge 112 and the third side edge 113, and the fifth side edge 115 and the sixth side edge 116 are substantially parallel to the second direction D2. Preferably, the adjacent slits 110 are symmetrical with respect to an imaginary line that is relatively parallel to the first direction D1. In this embodiment, the shape of the slit 110 may be a closed pattern, that is, the unit pattern 110U of the slit 110 may be a closed pattern, such as a hexagonal slit in FIG. 2A, but not limited thereto. In other words, the closed figure may be trapezoidal, rectangular, hexagonal, octagonal, elliptical, elongated, or other suitable polygon, and its inner angle is a right angle or an obtuse angle.

畫素電極100之狹縫110可沿著第一方向D1延伸排列而形成複數個狹縫列110R,且相鄰的狹縫列110R沿著第二方向D2並排,而在本實施例中,畫素電極100之狹縫110可呈現陣列排列,如在第2A圖中,畫素電極100可包括五個狹縫列110R,各狹縫列110R可包括兩個狹縫110,也就是說,畫素電極100之狹縫110可排列成兩行五列之矩陣排列形式,但不以此為限,在其他實施例中,可依據狹縫110之尺寸以及畫素電極100之尺寸而排成兩行十列、一行五列、四行一列、兩行一列或其他適合的矩陣排列形式。除此之外,在本實施例中的第二方向D2上,狹縫110之第一側邊111可與相鄰的另一個狹縫110之第四側邊114相鄰且對應,狹縫110之第二側邊112可與相鄰的另一個狹縫110之第三側邊113相鄰且對應,而由於第一側邊111與第四側邊114不互相平行,且第二側邊112與第三側邊113不互相平行,因此,在第二方向D2上相鄰的兩狹縫110之相鄰且對應之側邊皆不互相平行,並且,在第二方向D2上狹縫110具有最大寬度之部分係互相對應,且狹縫110具有最小寬度之部分係互相對應,換句話說,在第二方向D2上相鄰之狹縫110在第二方向D2上完全重疊,並且相鄰之側邊彼此對應。The slits 110 of the pixel electrodes 100 may be arranged to extend along the first direction D1 to form a plurality of slit rows 110R, and the adjacent slit rows 110R are arranged side by side along the second direction D2, and in the present embodiment, The slits 110 of the prime electrode 100 may be arranged in an array. As in FIG. 2A, the pixel electrode 100 may include five slit rows 110R, and each slit row 110R may include two slits 110, that is, draw The slits 110 of the element electrodes 100 may be arranged in a matrix of two rows and five columns, but not limited thereto. In other embodiments, the slits 110 may be arranged according to the size of the slits 110 and the size of the pixel electrodes 100. Rows of ten columns, five rows and one column, four rows and one column, two rows and one column, or other suitable matrix arrangement. In addition, in the second direction D2 in this embodiment, the first side 111 of the slit 110 may be adjacent to and correspond to the fourth side 114 of the adjacent other slit 110, and the slit 110 The second side 112 may be adjacent to and correspond to the third side 113 of the adjacent other slit 110, and since the first side 111 and the fourth side 114 are not parallel to each other, and the second side 112 The third side edges 113 are not parallel to each other. Therefore, the adjacent and corresponding side edges of the adjacent two slits 110 in the second direction D2 are not parallel to each other, and the slit 110 has the second direction D2. The portions of the maximum width correspond to each other, and the portions of the slit 110 having the smallest width correspond to each other. In other words, the slits 110 adjacent in the second direction D2 completely overlap in the second direction D2, and adjacent thereto The sides correspond to each other.

另外,關於子畫素的部分,單一個畫素電極100可與至少一個子畫素重疊,也就是說,各子畫素的區域可為單一個畫素電極100的部分區域或是整體區域,例如整個畫素電極100的區域、二分之一個畫素電極100的區域、四分之一個畫素電極100的區域,因此,子畫素的寬度W可等於畫素電極100的寬度或可為畫素電極100的寬度的二分之一或四分之一。在本實施例中,子畫素的區域係為整個畫素電極100的區域,故子畫素在第一方向D1上的寬度W等於畫素電極100在第一方向D1上的寬度。此外,在單一子畫素中的第一方向D1上,各狹縫110之第一虛擬距離a的和與寬度W之比值可大於或等於0.7,舉例而言,在第2A圖中,由於單一子畫素中的第一方向D1上具有兩個狹縫110,故2a/W≧0.7。In addition, regarding the portion of the sub-pixel, the single pixel electrode 100 may overlap with at least one sub-pixel, that is, the region of each sub-pixel may be a partial region or an entire region of the single pixel electrode 100. For example, a region of the entire pixel electrode 100, a region of one-half of the pixel electrode 100, and a region of one quarter of the pixel electrode 100, and therefore, the width W of the sub-pixel may be equal to the width of the pixel electrode 100 or It may be one-half or one-quarter of the width of the pixel electrode 100. In the present embodiment, the region of the sub-pixel is the region of the entire pixel electrode 100, so the width W of the sub-pixel in the first direction D1 is equal to the width of the pixel electrode 100 in the first direction D1. Further, in the first direction D1 of the single sub-pixel, the ratio of the sum of the first virtual distances a of the slits 110 to the width W may be greater than or equal to 0.7, for example, in the second diagram, due to the single The first direction D1 in the sub-pixel has two slits 110, so 2a/W ≧ 0.7.

請參考第2B圖,第2B圖繪示本發明第一實施例之變化實施例之畫素電極的上視示意圖。如第2B圖所示,本變化實施例之畫素電極100’與第一實施例之畫素電極100在電極的圖形上相同,其差異在於畫素電極100’與複數個子畫素重疊,詳細而言,以第2B圖為例,畫素電極100’在第一方向D1上平分為四等分區域(如虛線A-A’、B-B’、C-C’),而子畫素的區域僅為四等分區域中的其中一個,使子畫素的區域為四分之一個畫素電極100’的區域,子畫素在第一方向D1上的寬度W也為畫素電極100’在第一方向D1上的寬度的四分之一,且相鄰的子畫素可共用同一狹縫110,但不以此為限,畫素電極100’也可平分為二等分、三等分或其他適合的分割方式,並且其分割方向也不限定在第一方向D1,也可於第二方向上分割。由此可知,子畫素在第一方向D1上的寬度W係為畫素電極100’所具有之狹縫110的至少一個完整的第一虛擬距離a或至少一個部分的第一虛擬距離a與狹縫間的電極的寬度之和。而當單一個畫素電極100’與複數個子畫素重疊時,可藉此使畫素電極100’跨接複數個子畫素,即一個畫素電極100’的寬度對應多個子畫素的寬度,以利於高解析度的畫素設計。Please refer to FIG. 2B. FIG. 2B is a top view of the pixel electrode of the modified embodiment of the first embodiment of the present invention. As shown in FIG. 2B, the pixel electrode 100' of the present embodiment is identical to the pixel electrode 100 of the first embodiment in the pattern of the electrode, and the difference is that the pixel electrode 100' overlaps with a plurality of sub-pixels. For example, taking FIG. 2B as an example, the pixel electrode 100 ′ is equally divided into quarters in the first direction D1 (eg, dashed lines A-A′, B-B′, C-C′), and the sub-pixels The area is only one of the quarters, the area of the sub-pixel is one quarter of the pixel electrode 100', and the width W of the sub-pixel in the first direction D1 is also the pixel electrode. 100' is a quarter of the width in the first direction D1, and the adjacent sub-pixels may share the same slit 110, but not limited thereto, the pixel electrode 100' may be equally divided into two equal parts. The halving or other suitable division method, and the division direction thereof is not limited to the first direction D1, but may be divided in the second direction. It can be seen that the width W of the sub-pixel in the first direction D1 is at least one complete first virtual distance a of the slit 110 of the pixel electrode 100 ′ or the first virtual distance a of at least one portion and The sum of the widths of the electrodes between the slits. When the single pixel electrode 100' overlaps with the plurality of sub-pixels, the pixel electrode 100' can be bridged across the plurality of sub-pixels, that is, the width of one pixel electrode 100' corresponds to the width of the plurality of sub-pixels. To facilitate high-resolution pixel design.

請參考第3圖與第4圖,第3圖繪示本發明第一實施例之畫素電極100之電場示意圖,且僅繪示被提供驅動電位之畫素電極100之單一狹縫110之區域,第4圖繪示本發明第一實施例之畫素電極100被提供驅動電壓的明亮區示意圖,且僅繪示出被提供驅動電位之畫素電極100之單一狹縫110之區域顯示白畫面(例如顯示灰階為255)之狀態。如第3圖與第4圖所示,本實施例之單一狹縫110中之區域可分為第一區域1101、第二區域1102、第三區域1103以及第四區域1104,而當畫素電極100被提供驅動電位時,可藉由狹縫110之特殊圖案設計,產生不同方向的邊緣電場(如第3圖中之箭頭所示),而此些邊緣電場可分別對應第一側邊111、第二側邊112、第三側邊113、第四側邊114、第五側邊115以及第六側邊116,因此,由於此些不同方向的邊緣電場的作用,使得位於狹縫110上之部分液晶分子水平旋轉,造成狹縫110中之第一區域1101、第二區域1102、第三區域1103以及第四區域1104中皆有部分區域的光線穿透率被提升,進而產生明亮區LA(如第4圖所示)。另一方面,在各區域之交界處(如第3圖之十字狀虛線處),由於本實施例之狹縫110之圖案設計,並配合第一虛擬距離a與第二虛擬距離b具有2/(3W)≦a/b≦(3W)/2的關係,因此,相較於傳統之畫素電極,本實施例之畫素電極100具有較強的平行於第一方向D1之邊緣電場,而此電場可影響液晶分子的旋轉,使得位於各區域之交界處之液晶分子不產生旋轉或旋轉角度過小,進而產生暗紋,同樣的,在部分之畫素電極100上,例如各狹縫110之間的電極處,也會因為邊緣電場所產生之效果較弱而使此部分之液晶分子不產生旋轉或旋轉角度過小,進而產生暗紋,也就是說,在單一狹縫110之畫素電極100區域,會具有明顯的明亮區LA以及暗紋。Please refer to FIG. 3 and FIG. 4 . FIG. 3 is a schematic diagram of the electric field of the pixel electrode 100 of the first embodiment of the present invention, and only shows the area of the single slit 110 of the pixel electrode 100 provided with the driving potential. 4 is a schematic view showing a bright region in which the pixel electrode 100 of the first embodiment of the present invention is supplied with a driving voltage, and only shows a region of a single slit 110 of the pixel electrode 100 to which the driving potential is supplied. (For example, the grayscale is displayed as 255). As shown in FIGS. 3 and 4, the region in the single slit 110 of the present embodiment can be divided into a first region 1101, a second region 1102, a third region 1103, and a fourth region 1104, and when the pixel electrode is When the driving potential is provided by 100, the edge electric field in different directions can be generated by the special pattern design of the slit 110 (as indicated by the arrow in FIG. 3), and the fringe electric fields can respectively correspond to the first side 111, The second side 112, the third side 113, the fourth side 114, the fifth side 115, and the sixth side 116 are thus located on the slit 110 due to the action of the fringe electric fields in the different directions. Part of the liquid crystal molecules rotate horizontally, causing the light transmittance of the first region 1101, the second region 1102, the third region 1103, and the fourth region 1104 in the slit 110 to be increased, thereby generating a bright region LA ( As shown in Figure 4). On the other hand, at the intersection of the respective regions (as shown by the cross-hatched line in Fig. 3), due to the pattern design of the slit 110 of the present embodiment, and the first virtual distance a and the second virtual distance b have 2/. (3W) the relationship of ≦a/b≦(3W)/2, therefore, the pixel electrode 100 of the present embodiment has a strong fringe electric field parallel to the first direction D1 compared to the conventional pixel electrode, and The electric field can affect the rotation of the liquid crystal molecules, so that the liquid crystal molecules located at the interface of the respective regions do not rotate or the rotation angle is too small, thereby generating dark lines, and similarly, on a part of the pixel electrodes 100, for example, the slits 110 At the electrodes, the liquid crystal molecules in this portion are not rotated or the rotation angle is too small due to the weak effect of the edge electric field, thereby generating dark lines, that is, the pixel electrode 100 in the single slit 110. The area will have a distinct bright area LA and dark lines.

更進一步說明,「液晶反應時間」可定義為「上升時間與下降時間之和」,並且「上升時間」與「下降時間」符合下列之公式: Furthermore, the "liquid crystal reaction time" can be defined as "the sum of the rise time and the fall time", and the "rise time" and the "fall time" conform to the following formula: , ,

其中,τ rise表示上升時間,τ decay表示下降時間,γ表示旋轉黏度,Δ□表示液晶分子之介電係數差,E表示電場,K 1、K 2表示彈性係數,d表示液晶層30之間隙,x表示兩相鄰暗紋之距離。由上述公式可知,由於第一虛擬距離a與第二虛擬距離b具有2/(3W)≦a/b≦(3W)/2的關係,而使本實施例之畫素電極100相較於傳統之畫素電極具有較強的平行於第一方向D1之邊緣電場,並於狹縫110中產生了暗紋,而使本實施例之畫素電極100所產生之暗紋之距離相較於傳統之畫素電極所產生之暗紋之距離較小,因此,造成公式中的E提升與x下降,進而使得液晶反應時間降低。因此,當液晶層30之間隙在3微米的條件下,本實施例於25℃時之液晶反應時間(下文稱25℃液晶反應時間)可達到約9.7毫秒(ms),液晶效率約為67%(液晶效率可定義為「搭配同一背光源下,包含上下偏光片70之液晶顯示面板在白畫面的亮度除以去除上下偏光片70之液晶顯示面板在白畫面的亮度」),相較於傳統之畫素電極之設計,傳統之液晶反應時間約大於15毫秒,故本實施例之畫素電極100可達到降低液晶反應時間之功效。 Where τ rise represents the rise time, τ decay represents the fall time, γ represents the rotational viscosity, Δ□ represents the difference in dielectric constant of the liquid crystal molecules, E represents the electric field, K 1 and K 2 represent the elastic coefficient, and d represents the gap of the liquid crystal layer 30. , x represents the distance between two adjacent dark lines. It can be seen from the above formula that since the first virtual distance a and the second virtual distance b have a relationship of 2/(3W)≦a/b≦(3W)/2, the pixel electrode 100 of the present embodiment is compared with the conventional one. The pixel electrode has a strong electric field parallel to the edge of the first direction D1, and a dark line is generated in the slit 110, so that the distance of the dark lines generated by the pixel electrode 100 of the embodiment is compared with the conventional one. The distance between the dark lines generated by the pixel electrodes is small, and therefore, the E rise and the decrease of x in the formula are caused, thereby causing the liquid crystal reaction time to decrease. Therefore, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time (hereinafter referred to as 25 ° C liquid crystal reaction time) at 25 ° C of the present embodiment can reach about 9.7 milliseconds (ms), and the liquid crystal efficiency is about 67%. (The liquid crystal efficiency can be defined as "the brightness of the white screen of the liquid crystal display panel including the upper and lower polarizers 70 divided by the brightness of the liquid crystal display panel of the upper and lower polarizers 70 in the white screen with the same backlight"), compared with the conventional The design of the pixel electrode, the conventional liquid crystal reaction time is more than about 15 milliseconds, so the pixel electrode 100 of the embodiment can achieve the effect of reducing the liquid crystal reaction time.

本發明之畫素電極並不以上述實施例為限。下文將依序介紹本發明之其它較佳實施例之畫素電極,且為了便於比較各實施例之相異處並簡化說明,在下文之各實施例中使用相同的符號標注相同的元件,且主要針對各實施例之相異處進行說明,而不再對重覆部分進行贅述。The pixel electrode of the present invention is not limited to the above embodiment. The pixel electrodes of other preferred embodiments of the present invention will be sequentially described below, and in order to facilitate the comparison of the differences of the embodiments and simplify the description, the same components are denoted by the same reference numerals in the following embodiments, and The differences between the embodiments will be mainly described, and the repeated parts will not be described again.

請參考第5圖,第5圖繪示本發明第一實施例之變化實施例之畫素電極的上視示意圖。如第5圖所示,本發明之另一變化實施例之畫素電極110’’與第一實施例之間之差異在於本變化實施例之畫素電極110’’之部分狹縫110之圖形係為單元圖案110U之一部分所構成,例如位於畫素電極110’’兩端之狹縫110為單元圖案110U之二分之一、三分之一、四分之一所構成,但不以此為限。在本變化實施例中,當液晶層30之間隙在3微米的條件下,25℃液晶反應時間可達到約9.7毫秒,液晶效率約為55%。Referring to FIG. 5, FIG. 5 is a top view of a pixel electrode according to a variation of the first embodiment of the present invention. As shown in FIG. 5, the difference between the pixel electrode 110'' of the other modified embodiment of the present invention and the first embodiment is the pattern of the partial slit 110 of the pixel electrode 110'' of the modified embodiment. It is composed of a part of the unit pattern 110U. For example, the slit 110 located at both ends of the pixel electrode 110'' is composed of one-half, one-third, one-quarter of the unit pattern 110U, but not Limited. In the present variation, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time at 25 ° C can reach about 9.7 milliseconds, and the liquid crystal efficiency is about 55%.

請參考第6圖,第6圖繪示本發明第二實施例之畫素電極的上視示意圖。如第6圖所示,本實施例之畫素電極200與第一實施例之間之差異在於本實施例之畫素電極200之狹縫110具有複數個單元圖案110U,且單元圖案110U沿著第一方向D1連續重複排列,並且,單元圖案110U不具有上述第一實施例中所述之第五側邊115與第六側邊116,在本實施例中,狹縫110不為封閉圖形,但不以此為限,例如畫素電極200的一個狹縫列110R也可具有多個重複排列的單元圖案110U,但狹縫110為封閉圖形,亦即在第一個與最後一個單元圖案110U分別具有第五側邊115與第六側邊116。由上述可知,由於本實施例的單元圖案110U不具有第五側邊115與第六側邊116,亦即本實施例之畫素電極200相較於第一實施例之畫素電極100之電極所佔面積較小(減少了沿第二方向D2延伸之電極部分),因此,相較於第一實施例,本實施例位於電極上的暗紋減少,且狹縫110中各區域交界之暗紋寬度減少,亦即增加了各區域中之明亮區的面積,進而提升液晶效率。此外,雖然本實施例之單元圖案110U不具有第五側邊115與第六側邊116,但由於本實施例之畫素電極200具有尖點CP,而尖點CP與共用電極之間可提供多個方向的邊緣電場,因此,仍可在狹縫110中產生平行於第一方向D1之電場,狹縫110中各區域交界仍具有暗紋,液晶反應時間仍可被降低。在本實施例中,當液晶層30之間隙在3微米的條件下,25℃液晶反應時間可達約9.7毫秒,液晶效率為約72%,因此本實施例可具有低液晶反應時間以及較佳之液晶效率。Please refer to FIG. 6. FIG. 6 is a schematic top view of a pixel electrode according to a second embodiment of the present invention. As shown in FIG. 6, the difference between the pixel electrode 200 of the present embodiment and the first embodiment is that the slit 110 of the pixel electrode 200 of the present embodiment has a plurality of unit patterns 110U, and the unit pattern 110U is along The first direction D1 is continuously and repeatedly arranged, and the unit pattern 110U does not have the fifth side 115 and the sixth side 116 described in the first embodiment. In the embodiment, the slit 110 is not a closed figure. However, not limited thereto, for example, one slit row 110R of the pixel electrode 200 may have a plurality of repeatedly arranged unit patterns 110U, but the slits 110 are closed patterns, that is, in the first and last unit patterns 110U. There are a fifth side 115 and a sixth side 116, respectively. As can be seen from the above, since the unit pattern 110U of the present embodiment does not have the fifth side 115 and the sixth side 116, that is, the pixel electrode 200 of the present embodiment is compared with the electrode of the pixel electrode 100 of the first embodiment. The occupied area is small (the portion of the electrode extending in the second direction D2 is reduced), and therefore, compared with the first embodiment, the dark lines on the electrode of the present embodiment are reduced, and the boundary of each area in the slit 110 is dark. The width of the pattern is reduced, that is, the area of the bright area in each area is increased, thereby improving the liquid crystal efficiency. In addition, although the unit pattern 110U of the present embodiment does not have the fifth side 115 and the sixth side 116, since the pixel electrode 200 of the embodiment has the cusp CP, the cusp CP and the common electrode may be provided. The fringe electric field in a plurality of directions, therefore, an electric field parallel to the first direction D1 can still be generated in the slit 110, and the boundary of each region in the slit 110 still has dark lines, and the liquid crystal reaction time can still be lowered. In this embodiment, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time of 25 ° C can reach about 9.7 milliseconds, and the liquid crystal efficiency is about 72%, so this embodiment can have a low liquid crystal reaction time and preferably. LCD efficiency.

請參考第7圖,第7圖繪示本發明第二實施例之變化實施例之畫素電極的上視示意圖。如第7圖所示,本變化實施例之畫素電極200’與第二實施例之間之差異在於本變化實施例之畫素電極200’之狹縫110之單元圖案110U具有第一圓弧211、第二圓弧212、第三圓弧213以及第四圓弧214,第一圓弧211與第四圓弧214在第二方向D2上互相對應,第二圓弧212與第三圓弧213在第二方向D2上互相對應。由於本變化實施例之單元圖案110U具有圓弧,而圓弧與共用電極之間可提供多種方向的邊緣電場,因此,仍可在狹縫110中產生平行於第一方向D1之電場,狹縫110中各區域交界仍具有暗紋,液晶反應時間仍可被降低。Please refer to FIG. 7. FIG. 7 is a schematic top view of a pixel electrode according to a variation of the second embodiment of the present invention. As shown in FIG. 7, the difference between the pixel electrode 200' of the modified embodiment and the second embodiment is that the unit pattern 110U of the slit 110 of the pixel electrode 200' of the modified embodiment has the first circular arc. 211, the second arc 212, the third arc 213, and the fourth arc 214, the first arc 211 and the fourth arc 214 correspond to each other in the second direction D2, and the second arc 212 and the third arc 213 correspond to each other in the second direction D2. Since the unit pattern 110U of the modified embodiment has a circular arc, and a fringe electric field of a plurality of directions can be provided between the circular arc and the common electrode, an electric field parallel to the first direction D1 can still be generated in the slit 110, and the slit The junction of each region in 110 still has dark lines, and the liquid crystal reaction time can still be lowered.

請參考第8圖,第8圖繪示本發明第三實施例之畫素電極的上視示意圖。如第8圖所示,本實施例之畫素電極300與第一實施例之間之差異在於狹縫110之第一側邊111與在第二方向D2上相鄰的另一個狹縫110之第三側邊113相鄰且對應,且狹縫110之第二側邊112與在第二方向D2上相鄰的另一個狹縫110之第四側邊114相鄰且對應,換句話說,兩相鄰之狹縫列110R在第一方向D1上具有二分之一第一虛擬距離a之錯位排列。另外,由於兩相鄰之狹縫列110R在第一方向D1上錯位排列,因此,相鄰之狹縫110在第二方向D2上僅部分重疊,也就是說,在第二方向D2上,相鄰之狹縫110具有最大寬度之部分係互相錯位,且相鄰之狹縫110具有最小寬度之部分亦互相錯位。由於本實施例之狹縫110相對於第一實施例較為緊密,因此,畫素電極300與共用電極之間所造成之邊緣電場較多,使得液晶效率較高。在本實施例中,當液晶層30之間隙在3微米的條件下,25℃液晶反應時間可達約12.1毫秒,液晶效率為約69%,因此本實施例可具有低液晶反應時間。Please refer to FIG. 8. FIG. 8 is a schematic top view of a pixel electrode according to a third embodiment of the present invention. As shown in FIG. 8, the difference between the pixel electrode 300 of the present embodiment and the first embodiment is that the first side 111 of the slit 110 and the other slit 110 adjacent to the second direction D2 The third side 113 is adjacent and corresponding, and the second side 112 of the slit 110 is adjacent and corresponding to the fourth side 114 of the other slit 110 adjacent in the second direction D2, in other words, The two adjacent slit rows 110R have a misaligned arrangement of one-half of the first virtual distance a in the first direction D1. In addition, since the two adjacent slit rows 110R are misaligned in the first direction D1, the adjacent slits 110 only partially overlap in the second direction D2, that is, in the second direction D2, The portions of the adjacent slits 110 having the largest width are offset from each other, and the portions of the adjacent slits 110 having the smallest width are also offset from each other. Since the slit 110 of the present embodiment is relatively tight with respect to the first embodiment, the fringe electrode 300 and the common electrode cause a large electric field at the edge, so that the liquid crystal efficiency is high. In the present embodiment, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time at 25 ° C can reach about 12.1 milliseconds, and the liquid crystal efficiency is about 69%, so this embodiment can have a low liquid crystal reaction time.

請參考第9圖,第9圖繪示本發明第四實施例之畫素電極的上視示意圖。如第9圖所示,本實施例之畫素電極400包括第一狹縫區401、第二狹縫區402、第三狹縫區403以及第四狹縫區404。第一狹縫區401以及第三狹縫區403分別具有複數個狹縫110,而狹縫110具有平行於第一方向D1的第一虛擬距離a以及平行於第二方向D2的第二虛擬距離b,其中第一方向D1實質上不平形於第二方向D2,第二方向D2實質上垂直於其中一個偏光片70之光軸方向,且2/(3W)≦a/b≦(3W)/2,而在本實施例中,第一虛擬距離a為各狹縫110於第一方向D1上之最大寬度,第二虛擬距離b為各狹縫110在第二方向D2上的最大寬度,且各狹縫110之第一虛擬距離a可不完全相同,亦即此些狹縫110可具有兩種以上的第一虛擬距離a。進一步說明,第一狹縫區401與第二狹縫區402之間具有第一邊界411,第二狹縫區402與第三狹縫區403之間具有第二邊界412,第三狹縫區403與第四狹縫區404之間具有第三邊界413,第四狹縫區404與第一狹縫區401之間具有第四邊界414,第一邊界411以及第三邊界413沿第三方向D3延伸,且第二邊界412以及第四邊界414沿第四方向D4延伸,而第一方向D1、第二方向D2、第三方向D3以及第四方向D4不互相平行,在本實施例中,第三方向D3與第一方向D1之間的夾角a1範圍為約0度至約90度,且第四方向D4與第一方向D1之間的夾角a2範圍為約0度至約90度,在較佳實施例中,第三方向D3與第一方向D1之間的夾角a1與第四方向D4與第一方向D1之間的夾角a2相等,使得第一邊界411、第二邊界412、第三邊界413以及第四邊界414實質上構成X字形。Please refer to FIG. 9. FIG. 9 is a schematic top view of a pixel electrode according to a fourth embodiment of the present invention. As shown in FIG. 9, the pixel electrode 400 of the present embodiment includes a first slit region 401, a second slit region 402, a third slit region 403, and a fourth slit region 404. The first slit region 401 and the third slit region 403 respectively have a plurality of slits 110, and the slit 110 has a first virtual distance a parallel to the first direction D1 and a second virtual distance parallel to the second direction D2 b, wherein the first direction D1 is substantially non-flat in the second direction D2, and the second direction D2 is substantially perpendicular to the optical axis direction of one of the polarizers 70, and 2/(3W)≦a/b≦(3W)/ 2, in the embodiment, the first virtual distance a is the maximum width of each slit 110 in the first direction D1, and the second virtual distance b is the maximum width of each slit 110 in the second direction D2, and The first virtual distances a of the slits 110 may not be identical, that is, the slits 110 may have more than two first virtual distances a. Further, there is a first boundary 411 between the first slit region 401 and the second slit region 402, and a second boundary 412 between the second slit region 402 and the third slit region 403, and a third slit region There is a third boundary 413 between the 403 and the fourth slit region 404, and a fourth boundary 414 between the fourth slit region 404 and the first slit region 401. The first boundary 411 and the third boundary 413 are along the third direction. D3 extends, and the second boundary 412 and the fourth boundary 414 extend along the fourth direction D4, and the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4 are not parallel to each other. In this embodiment, The angle a1 between the third direction D3 and the first direction D1 ranges from about 0 degrees to about 90 degrees, and the angle a2 between the fourth direction D4 and the first direction D1 ranges from about 0 degrees to about 90 degrees. In a preferred embodiment, the angle a1 between the third direction D3 and the first direction D1 and the angle a2 between the fourth direction D4 and the first direction D1 are equal, such that the first boundary 411, the second boundary 412, and the third The boundary 413 and the fourth boundary 414 substantially constitute an X shape.

另一方面,在本實施例中,第二狹縫區402以及第四狹縫區404分別具有複數個縱向狹縫420,而縱向狹縫420具有平行於第一方向D1的第三虛擬距離c以及平行於第二方向D2的第四虛擬距離d,且2/(3W)≦d/c≦(3W)/2,因此,在第9圖中,第一狹縫區401中之一狹縫110、第二狹縫區402中之一縱向狹縫420、第三狹縫區403中之一狹縫110以及第四狹縫區404中之一縱向狹縫420可形成「口」字形,故本實施例並不明顯具有如前述實施例所述的狹縫列110R。除此之外,狹縫110的形狀較佳為以平行於第一方向D1之一假想線呈鏡像對稱,縱向狹縫420的形狀較佳為以平行於第二方向D2之一假想線呈鏡像對稱,在本實施例中,狹縫110與縱向狹縫420的形狀可為封閉圖形,舉例而言,封閉圖形可為梯形、矩形、六邊形、八邊形、橢圓形、長條形或其他適合的多邊形,且其內角為直角或鈍角,在第9圖中,狹縫110與縱向狹縫420以梯形為例。On the other hand, in the present embodiment, the second slit region 402 and the fourth slit region 404 respectively have a plurality of longitudinal slits 420, and the longitudinal slits 420 have a third virtual distance c parallel to the first direction D1. And a fourth virtual distance d parallel to the second direction D2, and 2/(3W) ≦d/c ≦ (3W)/2, therefore, in FIG. 9, one of the slits in the first slit region 401 110. One of the longitudinal slits 420 of the second slit region 402, one of the slits 110 of the third slit region 403, and one of the longitudinal slits 420 of the fourth slit region 404 may form a "mouth" shape. This embodiment does not obviously have the slit row 110R as described in the foregoing embodiment. In addition, the shape of the slit 110 is preferably mirror-symmetrical with respect to an imaginary line parallel to the first direction D1, and the shape of the longitudinal slit 420 is preferably mirrored by an imaginary line parallel to the second direction D2. Symmetrically, in the present embodiment, the shape of the slit 110 and the longitudinal slit 420 may be a closed figure. For example, the closed figure may be trapezoidal, rectangular, hexagonal, octagonal, elliptical, elongated or Other suitable polygons, and the inner corners thereof are right angles or obtuse angles. In FIG. 9, the slits 110 and the longitudinal slits 420 are exemplified by trapezoids.

由於本實施例之狹縫110之圖案設計,並配合第一虛擬距離a與第二虛擬距離b具有2/(3W)≦a/b≦(3W)/2的關係,因此,相較於傳統之畫素電極,本實施例之畫素電極400具有較強的平行於第一方向D1之邊緣電場,而此電場可影響液晶分子的旋轉,使得位於狹縫110中之部分液晶分子不產生旋轉或旋轉角度過小,進而產生暗紋,同樣的,在部分之畫素電極400上,例如各狹縫110之間的電極處,也會因為邊緣電場所產生之效果較弱而使此部分之液晶分子不產生旋轉或旋轉角度過小,進而產生暗紋,因此,在第一狹縫區401與第三狹縫區403中有明顯的明亮區與暗紋,並可藉由此些暗紋的產生,而達到降低液晶反應時間的功效。另一方面,由於縱向狹縫420中之第三虛擬距離c與第四虛擬距離d具有2/(3W)≦d/c≦(3W)/2的關係,因此,平行於第一方向D1之邊緣電場較強,使得位於縱向狹縫420上之液晶分子的旋轉不明顯或不旋轉,因此,在第二狹縫區402與第四狹縫區404中無法產生明亮區。在本實施例中,當液晶層30之間隙在3微米的條件下,25℃液晶反應時間可達約10.5毫秒,液晶效率為約37%,故本實施例之畫素電極400相較於傳統之畫素電極之設計可達到降低液晶反應時間之功效。Due to the pattern design of the slit 110 of the embodiment, and the first virtual distance a and the second virtual distance b have a relationship of 2/(3W) ≦ a/b ≦ (3W)/2, compared with the conventional The pixel electrode 400 of the present embodiment has a strong fringe electric field parallel to the first direction D1, and the electric field can affect the rotation of the liquid crystal molecules, so that some liquid crystal molecules located in the slit 110 do not rotate. Or the rotation angle is too small, and then the dark lines are generated. Similarly, on the portion of the pixel electrode 400, for example, the electrode between the slits 110, the liquid crystal of the portion is also weakened due to the effect of the edge electric field. The molecules do not rotate or the rotation angle is too small, thereby generating dark lines. Therefore, there are obvious bright areas and dark lines in the first slit region 401 and the third slit region 403, and the dark lines can be generated by the molecules. , to achieve the effect of reducing the liquid crystal reaction time. On the other hand, since the third virtual distance c and the fourth virtual distance d in the longitudinal slit 420 have a relationship of 2/(3W) ≦d/c ≦ (3W)/2, they are parallel to the first direction D1. The fringe electric field is strong, so that the rotation of the liquid crystal molecules located on the longitudinal slit 420 is not obvious or rotated, and therefore, a bright region cannot be generated in the second slit region 402 and the fourth slit region 404. In this embodiment, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time of 25 ° C can reach about 10.5 milliseconds, and the liquid crystal efficiency is about 37%, so the pixel electrode 400 of the embodiment is compared with the conventional one. The design of the pixel electrode can achieve the effect of reducing the liquid crystal reaction time.

請參考第10圖,第10圖繪示本發明第五實施例之畫素電極的上視示意圖,其中狹縫110係以長條形為例。如第10圖所示,本實施例之畫素電極500與第四實施例之間之差異在於本實施例之畫素電極500之第二狹縫區402以及第四狹縫區404分別具有複數個狹縫110,並且不具有縱向狹縫420。由於第一狹縫區401、第二狹縫區402、第三狹縫區403以及第四狹縫區404中之狹縫110之第一虛擬距離a與第二虛擬距離b具有2/(3W)≦a/b≦(3W)/2的關係,因此,在第一狹縫區401、第二狹縫區402、第三狹縫區403以及第四狹縫區404中皆可有明顯的明亮區與暗紋,並可藉由此些暗紋的產生,而達到降低液晶反應時間的功效。另外,由於第二狹縫區402與第四狹縫區404皆可產生明亮區,因此,相較於第四實施例,本實施例具有較高的液晶效率。在本實施例中,當液晶層30之間隙在3微米的條件下,25℃液晶反應時間可達約9.9毫秒,液晶效率為約55%,因此本實施例可具有低液晶反應時間以及較佳之液晶效率。Please refer to FIG. 10, which is a top view of a pixel electrode according to a fifth embodiment of the present invention, wherein the slit 110 is exemplified by a strip shape. As shown in FIG. 10, the difference between the pixel electrode 500 of the present embodiment and the fourth embodiment is that the second slit region 402 and the fourth slit region 404 of the pixel electrode 500 of the present embodiment have plural numbers, respectively. There are slits 110 and no longitudinal slits 420. Since the first virtual distance a and the second virtual distance b of the slits 110 in the first slit region 401, the second slit region 402, the third slit region 403, and the fourth slit region 404 have 2/(3W) ≦a / b ≦ (3W) / 2, therefore, in the first slit region 401, the second slit region 402, the third slit region 403 and the fourth slit region 404 can be obvious The bright area and the dark lines can be used to reduce the liquid crystal reaction time by the generation of the dark lines. In addition, since both the second slit region 402 and the fourth slit region 404 can produce a bright region, the present embodiment has higher liquid crystal efficiency than the fourth embodiment. In this embodiment, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time of 25 ° C can reach about 9.9 milliseconds, and the liquid crystal efficiency is about 55%, so this embodiment can have a low liquid crystal reaction time and preferably. LCD efficiency.

請參考第11圖,第11圖繪示本發明第五實施例之變化實施例之畫素電極的上視示意圖,其中狹縫110係以橢圓形為例。如第11圖所示,本變化實施例之畫素電極500’與第五實施例之間之差異在於本實施例之第一邊界411、第二邊界412、第三邊界413、第四邊界414呈彎折形,但第一邊界411、第三邊界413大體上仍沿第三方向D3延伸,第二邊界412、第四邊界414大體上仍沿第四方向D4延伸。在本變化實施例中,當液晶層30之間隙在3微米的條件下,25℃液晶反應時間可達約10毫秒,液晶效率為約53%,因此本變化實施例具有低液晶反應時間以及較佳之液晶效率。Referring to FIG. 11, FIG. 11 is a top view of a pixel electrode according to a variation of the fifth embodiment of the present invention, wherein the slit 110 is exemplified by an ellipse. As shown in FIG. 11, the difference between the pixel electrode 500' of the modified embodiment and the fifth embodiment lies in the first boundary 411, the second boundary 412, the third boundary 413, and the fourth boundary 414 of the present embodiment. The first boundary 411 and the third boundary 413 extend substantially in the third direction D3, and the second boundary 412 and the fourth boundary 414 extend substantially in the fourth direction D4. In the present variation, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time of 25 ° C can reach about 10 msec, and the liquid crystal efficiency is about 53%, so the present variation embodiment has a low liquid crystal reaction time and Good LCD efficiency.

請參考第12圖,第12圖繪示本發明第六實施例之畫素電極的上視示意圖,其中狹縫110係以矩形為例。如第12圖所示,本實施例之畫素電極600與第五實施例之間之差異在於本實施例之畫素電極600另包括複數個邊界狹縫610,設置於第一邊界411、第二邊界412、第三邊界413及第四邊界414的至少其中一者上。在本實施例中,當液晶層30之間隙在3微米的條件下,25℃液晶反應時間可達約11.1毫秒,液晶效率為約54%,因此本變化實施例可具有低液晶反應時間以及較佳之液晶效率。Referring to FIG. 12, FIG. 12 is a top view of a pixel electrode according to a sixth embodiment of the present invention, wherein the slit 110 is exemplified by a rectangle. As shown in FIG. 12, the difference between the pixel electrode 600 of the present embodiment and the fifth embodiment is that the pixel electrode 600 of the embodiment further includes a plurality of boundary slits 610 disposed on the first boundary 411, At least one of the second boundary 412, the third boundary 413, and the fourth boundary 414. In this embodiment, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time of 25 ° C can reach about 11.1 milliseconds, and the liquid crystal efficiency is about 54%, so the present variation embodiment can have a low liquid crystal reaction time and Good LCD efficiency.

請參考第13圖,第13圖繪示本發明第七實施例之畫素電極的上視示意圖,其中狹縫110係以八邊形為例。如第13圖所示,本實施例之畫素電極700包括複數個狹縫110,狹縫110之大小可不相同,而狹縫110具有平行於第一方向D1的第一虛擬距離a以及平行於第二方向D2的第二虛擬距離b,其中第一方向D1實質上不平形於第二方向D2,第二方向D2實質上垂直於其中一個偏光片70之光軸方向,且2/(3W)≦a/b≦(3W)/2,此外,在本實施例中,第一虛擬距離a為各狹縫110於第一方向D1上之最大寬度,第二虛擬距離b為各狹縫110在第二方向D2上的最大寬度,各狹縫110之第二虛擬距離b可相同,且各狹縫110之第一虛擬距離a可不相同,亦即此些狹縫110可具有兩種以上的第一虛擬距離a。另一方面,部分狹縫110係沿著第二方向D2相鄰並排,並且在第二方向D2上相鄰之狹縫110係互相錯位,而在本實施例中,狹縫110之中心在第二方向D2上可不與相鄰之狹縫110對應,但不以此為限,在變化實施例中,狹縫110之中心在第二方向D2上可與相鄰之狹縫110對應,但不與相鄰之狹縫110之中心對應。在本實施例中,當液晶層30之間隙在3微米的條件下,25℃液晶反應時間可達約11.2毫秒,液晶效率為約63%,因此本變化實施例可達到降低液晶反應時間的功效。Referring to FIG. 13, FIG. 13 is a schematic top view of a pixel electrode according to a seventh embodiment of the present invention, wherein the slit 110 is exemplified by an octagon. As shown in FIG. 13, the pixel electrode 700 of the present embodiment includes a plurality of slits 110. The slits 110 may have different sizes, and the slits 110 have a first virtual distance a parallel to the first direction D1 and are parallel to a second virtual distance b of the second direction D2, wherein the first direction D1 is substantially non-flat in the second direction D2, and the second direction D2 is substantially perpendicular to the optical axis direction of one of the polarizers 70, and 2/(3W) ≦a/b≦(3W)/2, further, in the embodiment, the first virtual distance a is the maximum width of each slit 110 in the first direction D1, and the second virtual distance b is the slit 110 The maximum width in the second direction D2, the second virtual distance b of each slit 110 may be the same, and the first virtual distance a of each slit 110 may be different, that is, the slits 110 may have two or more types. A virtual distance a. On the other hand, the partial slits 110 are adjacent to each other along the second direction D2, and the adjacent slits 110 in the second direction D2 are mutually displaced, and in the present embodiment, the center of the slit 110 is at the The two directions D2 may not correspond to the adjacent slits 110, but not limited thereto. In the modified embodiment, the center of the slit 110 may correspond to the adjacent slits 110 in the second direction D2, but not Corresponding to the center of the adjacent slit 110. In this embodiment, when the gap of the liquid crystal layer 30 is 3 micrometers, the liquid crystal reaction time of 25 ° C can reach about 11.2 milliseconds, and the liquid crystal efficiency is about 63%, so the present embodiment can achieve the effect of reducing the liquid crystal reaction time. .

請參考表1,表1為本發明第二實施例、第五實施例、第七實施例以及對照實施例之畫素電極之液晶效率、25℃液晶反應時間以及-30℃液晶反應時間,其中對照實施例係為傳統具有狹縫但狹縫的形狀大小不滿足2/(3W)≦a/b≦(3W)/2之畫素電極,而各實施例之液晶層30之間隙皆為2.8微米。如表1所示,本發明之第二實施例、第五實施例以及第七實施例,不論液晶於常溫25℃還是較低溫的-30℃,相對於對照實施例皆具有較低的液晶反應時間。此外,由於本發明的實施例之-30℃液晶反應時間小於250毫秒,較佳小於200毫秒,因此,可明顯改善於低溫顯示時的殘影問題,進而達到較佳的顯示品質。Please refer to Table 1. Table 1 is a liquid crystal efficiency of a pixel electrode, a liquid crystal reaction time of 25 ° C, and a liquid crystal reaction time of -30 ° C according to the second embodiment, the fifth embodiment, the seventh embodiment, and the comparative example of the present invention, wherein The comparative example is a pixel electrode having a slit shape but having a slit shape which does not satisfy 2/(3W)≦a/b≦(3W)/2, and the gap of the liquid crystal layer 30 of each embodiment is 2.8. Micron. As shown in Table 1, the second, fifth and seventh embodiments of the present invention have a lower liquid crystal reaction than the comparative examples, regardless of whether the liquid crystal is at a normal temperature of 25 ° C or a relatively low temperature of -30 ° C. time. In addition, since the -30 ° C liquid crystal reaction time of the embodiment of the present invention is less than 250 milliseconds, preferably less than 200 milliseconds, the image sticking problem at the time of low temperature display can be remarkably improved, thereby achieving better display quality.

表1 <TABLE border="1" borderColor="#000000" width="_0003"><TBODY><tr><td>   </td><td> 第二實施例 </td><td> 第五實施例 </td><td> 第七實施例 </td><td> 對照實施例 </td></tr><tr><td> 液晶效率 </td><td> 82% </td><td> 78% </td><td> 77% </td><td> 100% </td></tr><tr><td> 25℃液晶反應時間 </td><td> 7.7毫秒 </td><td> 8.1毫秒 </td><td> 9.3毫秒 </td><td> 11.4毫秒 </td></tr><tr><td> -30℃液晶反應時間 </td><td> 173毫秒 </td><td> 176毫秒 </td><td> 227毫秒 </td><td> 256毫秒 </td></tr></TBODY></TABLE>Table 1         <TABLE border="1" borderColor="#000000" width="_0003"><TBODY><tr><td> </td><td> Second Embodiment </td><td> Fifth Embodiment </td><td> Seventh Embodiment </td><td> Comparative Example </td></tr><tr><td> Liquid Crystal Efficiency</td><td> 82% </td> <td> 78% </td><td> 77% </td><td> 100% </td></tr><tr><td> 25°C liquid crystal reaction time</td><td> 7.7 Milliseconds</td><td> 8.1 milliseconds</td><td> 9.3 milliseconds</td><td> 11.4 milliseconds</td></tr><tr><td> -30 °C liquid crystal reaction time</ Td><td> 173ms</td><td> 176ms</td><td> 227ms</td><td> 256ms</td></tr></TBODY></TABLE>

綜上所述,本發明之畫素電極由於具有特殊的狹縫圖案設計,並且第一虛擬距離a與第二虛擬距離b具有2/(3W)≦a/b≦(3W)/2的關係,因此相較於傳統之畫素電極具有較強的平行於第一方向之邊緣電場,並且具有較短的暗紋距離,進而造成液晶反應時間降低。   以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。In summary, the pixel electrode of the present invention has a special slit pattern design, and the first virtual distance a and the second virtual distance b have a relationship of 2/(3W)≦a/b≦(3W)/2. Therefore, compared with the conventional pixel electrode, the electrode has a strong electric field parallel to the first direction, and has a short dark line distance, thereby causing a decrease in liquid crystal reaction time. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧第一基板
20‧‧‧第二基板
30‧‧‧液晶層
40‧‧‧主動電路結構層
42‧‧‧第一絕緣層
44‧‧‧共用電極層
46‧‧‧第二絕緣層
48‧‧‧畫素電極層
50‧‧‧彩色濾光層
60‧‧‧遮光層
70‧‧‧偏光片
100、100’、100’’、200、200’、300、400、500、500’、600、700‧‧‧畫素電極
110‧‧‧狹縫
110R‧‧‧狹縫列
110U‧‧‧單元圖案
1101‧‧‧第一區域
1102‧‧‧第二區域
1103‧‧‧第三區域
1104‧‧‧第四區域
111‧‧‧第一側邊
112‧‧‧第二側邊
113‧‧‧第三側邊
114‧‧‧第四側邊
115‧‧‧第五側邊
116‧‧‧第六側邊
211‧‧‧第一圓弧
212‧‧‧第二圓弧
213‧‧‧第三圓弧
214‧‧‧第四圓弧
401‧‧‧第一狹縫區
402‧‧‧第二狹縫區
403‧‧‧第三狹縫區
404‧‧‧第四狹縫區
411‧‧‧第一邊界
412‧‧‧第二邊界
413‧‧‧第三邊界
414‧‧‧第四邊界
420‧‧‧縱向狹縫
610‧‧‧邊界狹縫
a‧‧‧第一虛擬距離
a1、a2、α‧‧‧夾角
b‧‧‧第二虛擬距離
c‧‧‧第三虛擬距離
CP‧‧‧尖點
d‧‧‧第四虛擬距離
D1‧‧‧第一方向
D2‧‧‧第二方向
D3‧‧‧第三方向
D4‧‧‧第四方向
LA‧‧‧明亮區
W‧‧‧寬度
10‧‧‧First substrate
20‧‧‧second substrate
30‧‧‧Liquid layer
40‧‧‧Active circuit structure layer
42‧‧‧First insulation
44‧‧‧Common electrode layer
46‧‧‧Second insulation
48‧‧‧pixel electrode layer
50‧‧‧Color filter layer
60‧‧‧ shading layer
70‧‧‧ polarizer
100, 100', 100'', 200, 200', 300, 400, 500, 500', 600, 700‧‧ ‧ pixel electrodes
110‧‧‧slit
110R‧‧‧Slit column
110U‧‧‧ unit pattern
1101‧‧‧First area
1102‧‧‧Second area
1103‧‧‧ third area
1104‧‧‧ fourth area
111‧‧‧First side
112‧‧‧Second side
113‧‧‧ third side
114‧‧‧ fourth side
115‧‧‧ fifth side
116‧‧‧ Sixth side
211‧‧‧First arc
212‧‧‧Second arc
213‧‧‧ third arc
214‧‧‧ fourth arc
401‧‧‧First slit zone
402‧‧‧Second slit zone
403‧‧‧ third slit zone
404‧‧‧4th slit zone
411‧‧‧ first border
412‧‧‧ second border
413‧‧‧ third border
414‧‧‧ fourth border
420‧‧‧ longitudinal slit
610‧‧‧Boundary Slit
A‧‧‧first virtual distance
A1, a2, α‧‧‧ angle
B‧‧‧second virtual distance
C‧‧‧third virtual distance
CP‧‧‧ Point
D‧‧‧fourth virtual distance
D1‧‧‧ first direction
D2‧‧‧ second direction
D3‧‧‧ third direction
D4‧‧‧ fourth direction
LA‧‧‧Bright District
W‧‧‧Width

第1圖繪示本發明一實施例之液晶顯示面板的剖面示意圖。 第2A圖繪示本發明第一實施例之畫素電極的上視示意圖。 第2B圖繪示本發明第一實施例之變化實施例之畫素電極的上視示意圖。 第3圖繪示本發明第一實施例之畫素電極之電場示意圖。 第4圖繪示本發明第一實施例之畫素電極被提供驅動電壓的明亮區示意圖。 第5圖繪示本發明第一實施例之變化實施例之畫素電極的上視示意圖。 第6圖繪示本發明第二實施例之畫素電極的上視示意圖。 第7圖繪示本發明第二實施例之變化實施例之畫素電極的上視示意圖。 第8圖繪示本發明第三實施例之畫素電極的上視示意圖。 第9圖繪示本發明第四實施例之畫素電極的上視示意圖。 第10圖繪示本發明第五實施例之畫素電極的上視示意圖。 第11圖繪示本發明第五實施例之變化實施例之畫素電極的上視示意圖。 第12圖繪示本發明第六實施例之畫素電極的上視示意圖。 第13圖繪示本發明第七實施例之畫素電極的上視示意圖。FIG. 1 is a cross-sectional view showing a liquid crystal display panel according to an embodiment of the present invention. FIG. 2A is a top view showing the pixel electrode of the first embodiment of the present invention. FIG. 2B is a top view of the pixel electrode of the modified embodiment of the first embodiment of the present invention. FIG. 3 is a schematic view showing the electric field of the pixel electrode of the first embodiment of the present invention. 4 is a schematic view showing a bright region in which a pixel electrode of the first embodiment of the present invention is supplied with a driving voltage. Fig. 5 is a top plan view showing a pixel electrode of a modified embodiment of the first embodiment of the present invention. Fig. 6 is a top plan view showing a pixel electrode of a second embodiment of the present invention. Fig. 7 is a top plan view showing a pixel electrode of a modified embodiment of the second embodiment of the present invention. Fig. 8 is a top plan view showing a pixel electrode of a third embodiment of the present invention. Figure 9 is a top plan view showing a pixel electrode of a fourth embodiment of the present invention. Fig. 10 is a top plan view showing a pixel electrode of a fifth embodiment of the present invention. Figure 11 is a top plan view showing a pixel electrode of a variation of the fifth embodiment of the present invention. Fig. 12 is a top plan view showing a pixel electrode of a sixth embodiment of the present invention. Figure 13 is a top plan view showing a pixel electrode of a seventh embodiment of the present invention.

100‧‧‧畫素電極 100‧‧‧ pixel electrodes

110‧‧‧狹縫 110‧‧‧slit

110R‧‧‧狹縫列 110R‧‧‧Slit column

110U‧‧‧單元圖案 110U‧‧‧ unit pattern

111‧‧‧第一側邊 111‧‧‧First side

112‧‧‧第二側邊 112‧‧‧Second side

113‧‧‧第三側邊 113‧‧‧ third side

114‧‧‧第四側邊 114‧‧‧ fourth side

115‧‧‧第五側邊 115‧‧‧ fifth side

116‧‧‧第六側邊 116‧‧‧ Sixth side

a‧‧‧第一虛擬距離 A‧‧‧first virtual distance

b‧‧‧第二虛擬距離 B‧‧‧second virtual distance

D1‧‧‧第一方向 D1‧‧‧ first direction

D2‧‧‧第二方向 D2‧‧‧ second direction

D3‧‧‧第三方向 D3‧‧‧ third direction

D4‧‧‧第四方向 D4‧‧‧ fourth direction

W‧‧‧寬度 W‧‧‧Width

α‧‧‧夾角 ‧‧‧‧ angle

Claims (27)

一種畫素電極,包括複數個狹縫,且該等狹縫之其中一個具有: 一第一虛擬距離a,平行於一第一方向;以及 一第二虛擬距離b,平行於一第二方向,其中該第一方向實質上不同於該第二方向,該第二方向實質上垂直於一光軸方向,且2/(3W)≦a/b≦(3W)/2,W係為一子畫素之寬度。A pixel electrode comprising a plurality of slits, and one of the slits has: a first virtual distance a parallel to a first direction; and a second virtual distance b parallel to a second direction Wherein the first direction is substantially different from the second direction, the second direction is substantially perpendicular to an optical axis direction, and 2/(3W)≦a/b≦(3W)/2, and the W is a sub-picture The width of the prime. 如請求項1所述之畫素電極,其中該狹縫在該第二方向上具有兩種以上之寬度。The pixel electrode of claim 1, wherein the slit has two or more widths in the second direction. 如請求項2所述之畫素電極,其中該等狹縫分別包括一單元圖案,該第一虛擬距離a為該單元圖案於該第一方向上之寬度,而該第二虛擬距離b為該單元圖案在該第二方向上的最小寬度。The pixel electrode of claim 2, wherein the slits respectively comprise a unit pattern, the first virtual distance a is a width of the unit pattern in the first direction, and the second virtual distance b is the The minimum width of the unit pattern in the second direction. 如請求項3所述之畫素電極,其中該單元圖案具有一第一側邊、一第二側邊、一第三側邊以及一第四側邊,該第一側邊以及該第三側邊實質上平行一第三方向,該第二側邊以及該第四側邊實質上平行一第四方向,該第一側邊與該第四側邊在該第二方向上互相對應,該第二側邊與該第三側邊在該第二方向上互相對應,且該第一方向、該第二方向、該第三方以及該第四方向不互相平行。The pixel electrode of claim 3, wherein the unit pattern has a first side, a second side, a third side, and a fourth side, the first side and the third side The side is substantially parallel to a third direction, the second side and the fourth side are substantially parallel to a fourth direction, and the first side and the fourth side correspond to each other in the second direction, the first The two sides and the third side correspond to each other in the second direction, and the first direction, the second direction, the third party, and the fourth direction are not parallel to each other. 如請求項4所述之畫素電極,其中在該第二方向上,各該狹縫之該第一側邊係與相鄰的另一個該狹縫之該第四側邊相鄰且對應。The pixel electrode of claim 4, wherein in the second direction, the first side of each of the slits is adjacent to and corresponds to the fourth side of the adjacent one of the slits. 如請求項4所述之畫素電極,其中在該第二方向上,各該狹縫之該第一側邊係與相鄰的另一個該狹縫之該第三側邊相鄰且對應。The pixel electrode of claim 4, wherein in the second direction, the first side of each of the slits is adjacent to and corresponds to the third side of the adjacent one of the slits. 如請求項4所述之畫素電極,其中該單元圖案係為一六邊形。The pixel electrode of claim 4, wherein the unit pattern is a hexagon. 如請求項3所述之畫素電極,其中該單元圖案具有一第一圓弧、一第二圓弧、一第三圓弧以及一第四圓弧,該第一圓弧與該第四圓弧在該第二方向上互相對應,該第二圓弧與該第三圓弧在該第二方向上互相對應。The pixel electrode of claim 3, wherein the unit pattern has a first arc, a second arc, a third arc, and a fourth arc, the first arc and the fourth circle The arcs correspond to each other in the second direction, and the second arc and the third arc correspond to each other in the second direction. 如請求項2所述之畫素電極,其中該等狹縫分別包括複數個單元圖案,且該等單元圖案係沿著該第一方向連續重複排列,該第一虛擬距離a為各該單元圖案於該第一方向上之寬度,而該第二虛擬距離b為各該單元圖案在該第二方向上的最小寬度。The pixel electrode of claim 2, wherein the slits respectively comprise a plurality of unit patterns, and the unit patterns are successively repeatedly arranged along the first direction, the first virtual distance a being each of the unit patterns a width in the first direction, and the second virtual distance b is a minimum width of each of the unit patterns in the second direction. 如請求項2所述之畫素電極,其中部分該等狹縫係沿著該第二方向相鄰並排,在該第二方向上,該等狹縫具有最大寬度之部分係互相對應,且該等狹縫具有最小寬度之部分係互相對應。The pixel electrode of claim 2, wherein a part of the slits are adjacent to each other along the second direction, and in the second direction, the portions of the slits having the largest width correspond to each other, and The portions of the slits having the smallest width correspond to each other. 如請求項2所述之畫素電極,其中部分該等狹縫係沿著該第二方向相鄰並排,在該第二方向上,相鄰之該等狹縫具有最大寬度之部分係互相錯位,且相鄰之該等狹縫具有最小寬度之部分係互相錯位。The pixel electrode of claim 2, wherein a part of the slits are adjacent to each other along the second direction, and in the second direction, adjacent portions of the slits having the largest width are mutually displaced And adjacent portions of the slits having the smallest width are offset from each other. 如請求項1所述之畫素電極,該第一虛擬距離a為各該狹縫於該第一方向上之最大寬度,而該第二虛擬距離b為各該狹縫在該第二方向上的最大寬度。The pixel electrode of claim 1, wherein the first virtual distance a is a maximum width of each of the slits in the first direction, and the second virtual distance b is that the slits are in the second direction. The maximum width. 如請求項12所述之畫素電極,其另包括一第一狹縫區、一第二狹縫區、一第三狹縫區以及一第四狹縫區,其中該第一狹縫區以及該第三狹縫區分別具有複數個該狹縫,該第一狹縫區與該第二狹縫區之間具有一第一邊界,該第二狹縫區與該第三狹縫區之間具有一第二邊界,該第三狹縫區與該第四狹縫區之間具有一第三邊界,該第四狹縫區與該第一狹縫區之間具有一第四邊界,該第一邊界以及該第三邊界沿一第三方向延伸,且該第二邊界以及該第四邊界沿一第四方向延伸。The pixel electrode of claim 12, further comprising a first slit region, a second slit region, a third slit region and a fourth slit region, wherein the first slit region and The third slit region has a plurality of the slits respectively, and the first slit region and the second slit region have a first boundary between the second slit region and the third slit region Having a second boundary, a third boundary between the third slit region and the fourth slit region, and a fourth boundary between the fourth slit region and the first slit region, the first A boundary and the third boundary extend in a third direction, and the second boundary and the fourth boundary extend in a fourth direction. 如請求項13所述之畫素電極,其中該第二狹縫區以及該第四狹縫區分別具有複數個縱向狹縫,該等縱向狹縫之其中一個具有: 一第三虛擬距離c,平行於該第一方向;以及 一第四虛擬距離d,平行於該第二方向,且2/(3W)≦d/c≦(3W)/2。The pixel electrode of claim 13, wherein the second slit region and the fourth slit region respectively have a plurality of longitudinal slits, one of the longitudinal slits having: a third virtual distance c, Parallel to the first direction; and a fourth virtual distance d, parallel to the second direction, and 2/(3W) ≦d/c ≦ (3W)/2. 如請求項13所述之畫素電極,其中該第二狹縫區以及該第四狹縫區分別具有複數個該狹縫。The pixel electrode of claim 13, wherein the second slit region and the fourth slit region respectively have a plurality of the slits. 如請求項13所述之畫素電極,其另包括複數個邊界狹縫,設置於該第一邊界、該第二邊界、該第三邊界及該第四邊界的至少其中一者上。The pixel electrode of claim 13, further comprising a plurality of boundary slits disposed on at least one of the first boundary, the second boundary, the third boundary, and the fourth boundary. 如請求項13所述之畫素電極,其中該第三方向與該第一方向之間的夾角範圍為約0度至約90度,且該第四方向與該第一方向之間的夾角範圍為約0度至約90度。The pixel electrode of claim 13, wherein an angle between the third direction and the first direction ranges from about 0 degrees to about 90 degrees, and an angle range between the fourth direction and the first direction It is from about 0 degrees to about 90 degrees. 如請求項13所述之畫素電極,其中該第一邊界、該第二邊界、該第三邊界以及該第四邊界實質上呈X字形。The pixel electrode of claim 13, wherein the first boundary, the second boundary, the third boundary, and the fourth boundary are substantially X-shaped. 如請求項12所述之畫素電極,其中部分該等狹縫係沿著該第二方向相鄰並排,在該第二方向上,相鄰之該等狹縫係互相錯位。The pixel electrode of claim 12, wherein a portion of the slits are adjacent to each other along the second direction, and adjacent slits are offset from each other in the second direction. 如請求項19所述之畫素電極,其中各該狹縫之一中心在該第二方向上係不與相鄰之該等狹縫對應。The pixel electrode of claim 19, wherein a center of each of the slits does not correspond to the adjacent slits in the second direction. 如請求項12所述之畫素電極,其中該等狹縫具有兩種以上的該第一虛擬距離a。The pixel electrode of claim 12, wherein the slits have more than two of the first virtual distances a. 如請求項1所述之畫素電極,其中該等狹縫沿著該第一方向延伸排列成複數個狹縫列,且該等狹縫列沿著該第二方向上平行並排。The pixel electrode of claim 1, wherein the slits are arranged in a plurality of slit rows along the first direction, and the slit rows are parallel to each other along the second direction. 如請求項22所述之畫素電極,其中兩相鄰之該等狹縫列之該等狹縫在該第二方向上彼此對應。The pixel electrode of claim 22, wherein the slits of the two adjacent slit columns correspond to each other in the second direction. 如請求項22所述之畫素電極,其中兩相鄰之該等狹縫列在該第一方向上錯位排列。The pixel electrode of claim 22, wherein the two adjacent slit columns are misaligned in the first direction. 如請求項24所述之畫素電極,其中兩相鄰之該等狹縫列在該第一方向上具有二分之一該第一虛擬距離a之錯位排列。The pixel electrode of claim 24, wherein the two adjacent slits have a misalignment of the first virtual distance a in the first direction. 如請求項1所述之畫素電極,其中該等狹縫分別為一多邊形,且該多邊形之內角為直角或鈍角。The pixel electrode of claim 1, wherein the slits are respectively a polygon, and the inner corner of the polygon is a right angle or an obtuse angle. 如請求項1所述之畫素電極,其中該等狹縫係為梯形、矩形、六邊形、八邊形、橢圓形或長條形。The pixel electrode of claim 1, wherein the slits are trapezoidal, rectangular, hexagonal, octagonal, elliptical or elongated.
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