TWI565036B - Reduced size semiconductor device and method for manufacture thereof - Google Patents

Description

Dimensional reduced semiconductor device and method of manufacturing same 【0001】

Exemplary embodiments of the present invention are generally directed to a semiconductor device, and more particularly to a reduced size semiconductor device that avoids word line interference.

【0002】

A semiconductor device can be typically classified into a volatile semiconductor device that requires a power source to maintain the storage of data, or a non-volatile semiconductor device that retains data even if the power source is removed. An example of a non-volatile semiconductor device is a flash memory device that generally includes an array of memory cells arranged in columns and columns. Each memory cell includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. Each memory cell is located at an intersection between the word line and the bit line, where the gate is connected to the word line, the drain is connected to the bit line, and the source is connected to the source line. Then connect to the common ground. The gate of the conventional flash memory cell generally comprises a double gate structure, the double gate structure comprises a control gate and a floating gate, wherein the floating gate is sandwiched between two dielectric layers. To capture a carrier (such as an electron) to write to a memory cell.

[0003]

The flash memory device can then be divided into NOR or NAND flash memory devices. While NOR flash memory has its benefits, NAND flash memory typically provides faster write and erase speeds, mostly because of its serialized structure, which allows for stringing of memory cells. Write and erase operations are performed on the column.

[0004]

Despite the advantages of existing NAND flash memory, the semiconductor industry is increasingly moving toward smaller and more performance electronic devices. In order to maintain or improve their respective performance while reducing the size of such devices, the dimensions of the components within the device and the distance between these components must be reduced.

[0005]

With regard to NAND flash memory devices, the problem arises from maintaining memory cell performance and respective functions preventing size reduction. For example, the traditional tandem height of selected transistors and contacts has gradually become an obstacle to reducing the size of memory cells. Because of the concern of reducing the distance between the word line and the source line, it has proven difficult to reach these dimensions. In this regard, the Gate-Induced Drain Leakage (GIDL) current from the ground select line (GSL) can cause hot electrons to the memory cells adjacent to the high threshold voltage. -E) Interference. Therefore, edge word lines often experience this interference.

[0006]

Accordingly, there is still a need in the art to reduce the size of NAND flash memory devices while reducing the likelihood of hot electron edge word line interference.

【0007】

In accordance with an embodiment of the present invention, a non-volatile semiconductor device capable of simultaneously reducing the size of a wafer and avoiding thermal electronic interference of edge word lines is provided. As described herein, removing ground select lines (GSLs) from a series comprising a plurality of blocks can reduce the size of the wafer and can reduce the number of edge word lines susceptible to thermal electron interference. Also, in some embodiments, embodiments of the present invention use space and/or dummy word lines to prevent operations performed in one block from interfering with word lines of neighboring blocks. Therefore, the operation for writing, erasing, or reading the memory cell function is good, the interference of the edge word line is reduced, and the size of the wafer can be substantially reduced.

[0008]

In a first exemplary embodiment, a non-volatile semiconductor device is provided, including a substrate and a plurality of blocks, the plurality of blocks forming a series, wherein each of the blocks is on the substrate and includes being disposed on the substrate Multiple word lines. Each block is located on the substrate and includes a plurality of word lines disposed on the substrate. The series includes a single ground selection line disposed on one side of the plurality of blocks, and a single serial selection line is disposed on the other side of the plurality of blocks. Non-volatile semiconductor devices can include flash memory, and in particular can include NAND flash memory.

【0009】

In some embodiments, the word lines of the plurality of blocks define a gap separating the individual blocks in the string from adjacent blocks in the string. In this regard, one or more dummy word lines can be placed in the gap between the aligned blocks. In one embodiment, the dummy word line is a floating dummy word line. In another embodiment, the dummy word line has a bias voltage. In yet another embodiment, the dummy word lines are grounded. In other embodiments, the dummy word line can include a plurality of word lines.

[0010]

In another exemplary embodiment, a method of fabricating a non-volatile semiconductor device is provided. The method includes providing a substrate and disposing a plurality of blocks on the substrate to form a series, wherein each of the plurality of blocks includes a plurality of word lines disposed on the substrate. The method further includes forming a single ground select line associated with the string, wherein the single ground select line is disposed on one side of the plurality of blocks and forms a single string selection associated with the series A line, wherein the single serial selection line is configured on the other side of the plurality of blocks. A ground selection line and a tandem selection line may be disposed on opposite sides of the plurality of blocks.

[0011]

In some embodiments of the method, the step of setting a plurality of blocks on the substrate comprises: separating the respective blocks in the series from adjacent blocks in the series by the word line definition of the plurality of blocks Clearance. In this regard, the method can include setting a dummy word line in a gap separating two of the plurality of blocks. To this end, in one embodiment, the dummy word line is a floating dummy word line. In another embodiment, the dummy word line has a bias voltage. In yet another embodiment, the dummy word lines are grounded. In other embodiments, the dummy word line includes a plurality of word lines.

[0012]

In yet another embodiment, a method of operating a non-volatile semiconductor device is provided. In this regard, a method of operating a non-volatile semiconductor device can include selecting a first block from a plurality of blocks forming a series and performing an operation on the selected block.

[0013]

In one such embodiment, the operation includes an erase operation in which a bias voltage is applied to a plurality of word lines of the selected block to erase data stored in a plurality of memory cells of the selected block, biased and Not applied to the dummy word line.

[0014]

In another such embodiment, the operation includes a write operation in which a bias voltage is applied to a plurality of word lines of the selected block to write into a plurality of memory cells of the selected block, and the bias voltage is not applied to Dummy word line.

[0015]

In yet another such embodiment, the operation includes a read operation, applying a pass voltage to the dummy word line.

[0016]

The above summary is provided merely to summarize the purpose of some example embodiments to provide a basic understanding of some aspects of the invention. Therefore, it is to be understood that the above-described embodiments are merely exemplary and are not to be construed as limiting the scope or spirit of the invention. It is to be understood that the scope of the invention includes many potential embodiments in addition to those embodiments set forth herein, and some of the embodiments are further described below.

[0017]

For a better understanding of the above and other aspects of the present invention, the preferred embodiments of the present invention are described in detail herein below,

[0036]

102‧‧‧ character line
102d‧‧‧dummy word line
102e‧‧‧Edge word line
104‧‧‧ bit line
106‧‧‧Source line
108‧‧‧Sequence selection line
110‧‧‧ Grounding selection line
112‧‧‧ Height
202‧‧‧ gap
302‧‧‧ Height
402, 502, 602, BLK _n , BLK _n+1 ‧‧‧ blocks
702, 704, 706, 708‧‧‧ operations

[0018]

Figure 1 is a top view of a conventional flash memory device.
2 is a top view of a modification of a semiconductor device that allows for reduced string height in accordance with an exemplary embodiment of the present invention.
3 is a top view of a semiconductor device of reduced size in accordance with an exemplary embodiment of the present invention.
4-6 illustrate exemplary operations that may be implemented using a reduced size semiconductor device in accordance with an exemplary embodiment of the present invention.
FIG. 7 is a flow chart showing the operation of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention.

[0019]

Some embodiments of the invention are described more fully hereinafter with reference to the accompanying drawings. In fact, these inventions may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, the embodiments are provided to make the disclosure comply with applicable legal requirements. Like reference numerals in the present disclosure refer to like elements.

[0020]

As used herein, "non-volatile memory" refers to a semiconductor device that is capable of storing information even if electrical supply is removed from the memory. Non-volatile memory includes, but is not limited to, Mask Read-Only Memory, Programmable Read-Only Memory, Erasable Programmable Read -Only Memory), Electronically Erasable Programmable Read-Only Memory and Flash Memory.

[0021]

As used herein, a "substrate" can include any material below that can form a device, circuit, epitaxial layer, or semiconductor thereon. In general, a substrate can be used to define a layer underlying a semiconductor device or even forming a base layer of a semiconductor device. The substrate can include one or any combination of germanium, germanium, germanium, antimony, semiconductor compounds, or other semiconductor materials.

[0022]

Referring now to Figure 1, a conventional non-volatile semiconductor device is illustrated. The semiconductor device of FIG. 1 comprises a plurality of first blocks (although a similar configuration can be attached to additional blocks of the semiconductor, display and two blocks BLK _n BLK _{n + 1} Example thereto). Each block includes a plurality of word lines 102 that intersect the plurality of bit lines 104. The memory cell is located at each intersection, and the memory cell includes a gate, a drain, a source, and a channel defined between the drain and the source. As described above, the gate of each memory cell is connected to the word line, the drain is connected to the bit line, and the source is connected to the source disposed between the adjacent blocks BLK _n and BLK _n+1 . The pole line 106, the block BLK _n and the BLK _n+1 are connected to a common ground. As further shown in FIG. 1, each block has a corresponding tandem select line 108 and a ground select line 110.

[0023]

Using this conventional semiconductor construction, the series of two blocks has a corresponding height 112. However, in order to reduce the size of the overall wafer, the constituent elements of the respective blocks must be reduced in size and/or in a relatively close relationship to each other. However, as described above, the word line and the string selection line and the ground selection line are disposed at a relatively close position, so that the possibility of thermal electron interference of the edge word line is large. In this regard, because of the potential difference between the edge word line 102e and the channel voltage of the series select line and the ground select line, a lateral electric field that affects the edge word line may be generated. In particular, this electric field can generate hot electrons at the edge word line 102e, which may be injected into the data layer associated with the memory cells along the edge word line. Edge word line 102e may therefore be improperly written. Similarly, placing the blocks closer to each other, the write and erase operations may also direct the accompanying interference to the edge word line 102e of the adjacent block. Therefore, there is a need for a tandem configuration that can reduce the size of the wafer while avoiding these interference problems.

[0024]

2 is a top view of a modification of a semiconductor device capable of reducing the string height in accordance with an exemplary embodiment of the present invention. Figure 2 also depicts the two blocks BLK _n and BLK _n+1 , but their configuration has been different from those shown in Figure 1. In this regard, FIG. 2 illustrates that source line 106 has been moved to one side of an adjacent block and only a single string select line 108 and a single ground select line 110 are provided. As such, the same tandem height 112 is used to provide a gap 202 between the connected blocks. Providing such a large gap 202 reduces the likelihood of interference from one of these blocks caused by write or erase operations performed on other blocks. Moreover, because only a single string select line 108 and a single ground select line 110 are used, only one edge word line 120e is associated with the string select line 108, and there is only one edge word line 120e and ground select line 110 associations. Therefore, although the conventional semiconductor device shown in Fig. 1 includes four edge word lines 120e susceptible to thermal electron interference, the modified semiconductor device shown in Fig. 2 includes only two edge word lines 120e. Therefore, in addition to providing a large gap between adjacent blocks, the semiconductor device of Fig. 2 has fewer word lines susceptible to thermal electron interference. It should be noted that although Figure 2 illustrates that the string has only two blocks BLK _n and BLK _n+1 , any number of additional blocks may be added to the string.

[0025]

Referring now to FIG. 3, a top view of a reduced size semiconductor device in accordance with an exemplary embodiment of the present invention is shown. The semiconductor device shown in Fig. 3 shows a further modification to the device shown in Fig. 2. The semiconductor device of Figure 3 moves adjacent blocks closer together and separates them using one or more dummy word lines 102d, rather than simply creating a gap 202 between adjacent blocks of the series. Although two dummy word lines are depicted in FIG. 3, in some embodiments, there may be more or fewer dummy word lines 102d separating adjacent blocks in the series. Although adjacent blocks are closer together in this figure, the dummy word line 102d prevents interference caused by operating in its neighboring blocks in one block.

[0026]

In one embodiment, the dummy word lines are floating, and the impedance of the dummy word lines and the distance between adjacent blocks generate sufficient buffer to mitigate potential interference. In another embodiment, a dummy word line having a bias voltage is provided that can interfere with any lateral electric field that may cause thermal electron interference during operation. In yet another embodiment, the dummy word lines are grounded, which removes hot electrons from the circuit before the hot electrons can move from one block through the dummy word line 102d to its neighboring blocks. As described above, the dummy word line can include a plurality of word lines.

[0027]

In various examples, the presence of one or more dummy word lines 102d allows for full write, erase, and read functions, although moving adjacent blocks are closer together. Therefore, as shown in FIG. 3, since the height of the two block series is reduced from the height 112 in the semiconductor device shown in FIGS. 1 and 2 to the reduced tandem height 302, the wafer size can be remarkable. The amplitude is reduced.

[0028]

It should be noted that although Figure 3 illustrates that the string has only two blocks BLK _n and BLK _n+1 , any number of additional blocks may be added to the string. In particular, when compared with the conventional apparatus shown in Fig. 1, each of the additional blocks supplied to the series as shown in Fig. 3 produces a greater degree of efficiency because when each additional When a block is added to a plurality of word lines, no new serial select line 108 or ground select line 110 is added, so that for each block added to the semiconductor device, compared to the device configured according to FIG. 1 or FIG. The overall tandem height, the overall tandem height of the device having the configuration as shown in Figure 3, increases by a small margin.

[0029]

4-6 illustrate example operations that may be implemented using a reduced size semiconductor device in accordance with an exemplary embodiment of the present invention.

[0030]

Figure 4 illustrates an embodiment in which dummy word line 102d is used to avoid interference caused by the implementation of erase operations on selected neighboring blocks in a block. In this regard, block 402 is selected for erasure. This operation can apply a bias voltage to the memory cells of the selected block. In particular, even when a bias voltage is applied to the selected block, the dummy word line is floated with the unselected block of the series.

[0031]

Figure 5 illustrates an embodiment in which a dummy word line 102d is used in association with a write operation implemented on a selected adjacent block. In this regard, block 502 is selected for writing. In particular, the dummy word line 102d need not be associated with a memory cell and therefore may not be written.

[0032]

Figure 6 illustrates an embodiment in which a dummy word line 102d is used in performing a read operation on a selected adjacent block. In this example, block 602 is selected to be read. This operation can apply a turn-on voltage to the unselected word lines of the series. In this regard, by establishing a lower voltage to the word line being inspected and establishing a turn-on voltage to all other word lines, the read operation identifies whether a memory cell contains captured electrons. Thus, in addition to all unselected word lines, the turn-on voltage is applied to the dummy word lines.

[0033]

Referring now to FIG. 7, a flowchart of the operation of fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention is shown. In operation 702, a substrate is provided. In operation 704, a plurality of blocks are disposed on the substrate to form a series, wherein each of the plurality of blocks includes a plurality of word lines disposed on the substrate. Some of the plurality of word lines may include dummy word lines between the blocks including the remaining word lines. In some embodiments, there is no need to make any difference between the dummy word line and the remaining word lines, however in other embodiments, the dummy word lines can be connected to a common ground or voltage source. In operation 706, a single ground select line associated with the string is formed, wherein the single ground select line is disposed on one side of the plurality of blocks. Finally, in operation 708, a single string select line associated with the string is formed, wherein the single string select line is disposed on the other side of the plurality of blocks.

[0034]

Therefore, as described above, the provision of the non-volatile semiconductor device, the method of manufacturing the same, and the method of operating the same can reduce the size of the wafer and avoid thermal electronic interference of the edge word lines. Moreover, even with a substantially reduced size wafer, the operation to write, erase or read the memory cell function is good. As previously mentioned, the number of dummy word lines located between adjacent blocks is not fixed, and different numbers of dummy word lines may be included in different embodiments. In this regard, dummy lines are not used in some embodiments, and gap 202 may be sufficient. Moreover, although only two adjacent blocks are shown in the series for simplicity, as in all aspects of the present application, any number of blocks may be used in conjunction with embodiments of the present invention. In some embodiments, the dummy word lines can include any suitable technique and are not limited to any particular material and/or structure. Finally, while some embodiments of the invention include NAND flash memory devices, embodiments of the invention are also intended for use with other non-volatile semiconductor devices, such as NOR flash memory or the like.

[0035]

Many modifications and other embodiments of the inventions set forth herein will be apparent to those skilled in the <RTIgt; Therefore, the invention is to be understood as not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, although the foregoing description of the specification and the accompanying drawings are intended to illustrate a particular exemplary combination of the elements and/or functions in the example embodiments, it should be understood that Examples provide different combinations of components and/or functions. In this regard, for example, combinations of elements and/or functions that are distinct from the above are also considered to be included in the scope of the appended claims. Although specific terms are used herein, they are used in a generic and descriptive sense and not for the purpose of limitation.

102d‧‧‧dummy word line

112‧‧‧ Height

302‧‧‧ Height

BLK _n , BLK _n+1 ‧‧‧ blocks

Claims (10)

[Item 1] A non-volatile semiconductor device comprising:
a substrate;
a plurality of blocks forming a series of columns, wherein each of the blocks is disposed on the substrate, and each of the blocks includes a plurality of word lines disposed on the substrate;
a single ground select line associated with the string, wherein the single ground select line is disposed on one side of the blocks; and a single string select line associated with the string, wherein the single The serial selection line is disposed on the other side of the blocks. [Item 2] The non-volatile semiconductor device of claim 1, wherein the word lines of the plurality of blocks define a gap separating the respective blocks in the series from adjacent blocks in the series. . [Item 3] The non-volatile semiconductor device of claim 1, wherein a dummy word line is disposed in a gap between a first block and a second block of the plurality of blocks of the series. The dummy word line is floating or grounded, or the dummy word line has a bias voltage. [Item 4] A method of manufacturing a non-volatile semiconductor device, comprising:
Providing a substrate;
Setting a plurality of blocks on the substrate to form a series, wherein each of the blocks includes a plurality of word lines disposed on the substrate;
Forming a single ground select line associated with the string, wherein the single ground select line is disposed on one side of the blocks; and forming a single string select line associated with the string, wherein the A single serial selection line is placed on the other side of the blocks. [Item 5] The manufacturing method of claim 4, wherein the step of setting the blocks on the substrate comprises: defining, by the word lines of the blocks, the blocks in the series from the The gap separating adjacent blocks in the series. [Item 6] The manufacturing method of claim 4, further comprising: setting a dummy word line to separate the gaps of the two blocks in the blocks, wherein the dummy word lines are floating or grounded, or The dummy word line has a bias voltage. [Item 7] A method of operating a non-volatile semiconductor device as described in claim 3, comprising:
Selecting the first block of the blocks forming the string; and implementing a first block operating in the selected one. [Item 8] The method of operation of claim 7, wherein the operation comprises an erasing operation, and wherein a bias voltage is applied to the selected word lines of the first block to erase the storage in the The data in the plurality of memory cells of the first block is selected, and the bias voltage is not applied to the dummy word line. [Item 9] The method of operation of claim 7, wherein the operation comprises a write operation, and wherein a bias voltage is applied to the selected word lines of the first block to write the selected The plurality of memory cells of the first block are not applied to the dummy word line. [Item 10] The method of operation of claim 7, wherein the operation comprises a read operation, and wherein a pass voltage is applied to the dummy word line.