TWI565022B - 具有以面對面組態互連之記憶體晶粒及邏輯晶粒之封裝 - Google Patents

具有以面對面組態互連之記憶體晶粒及邏輯晶粒之封裝 Download PDF

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TWI565022B
TWI565022B TW104116543A TW104116543A TWI565022B TW I565022 B TWI565022 B TW I565022B TW 104116543 A TW104116543 A TW 104116543A TW 104116543 A TW104116543 A TW 104116543A TW I565022 B TWI565022 B TW I565022B
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die
logic die
terminals
coupled
logic
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TW104116543A
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TW201603234A (zh
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孟枝 龐
軍 翟
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蘋果公司
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Description

具有以面對面組態互連之記憶體晶粒及邏輯晶粒之封裝
本文中所描述之實施例係關於半導體封裝及用於封裝半導體器件之方法。更特定言之，本文中所描述之一些實施例係關於具有以面對面組態互連至邏輯晶粒之記憶體晶粒的封裝。
在半導體工業中，持續存在使得半導體封裝具有較低成本、較高效能、增加之積體電路密度及增加之封裝密度之顯著推動力。邏輯晶粒(例如，系統單晶片(「SoC」))持續變得更加高度整合，其需要增加之互連密度。因此，互連間距正逐步減小至極精細或超精細之等級。
記憶體晶粒亦正持續地與邏輯晶粒置放地愈來愈近以增加晶粒之間的頻寬。記憶體頻寬之不斷增加的需求對半導體封裝內的記憶體通道之信號整合度提出經選擇之挑戰。作為一實例，12.6Gps之記憶體頻寬可能需要64位元(2通道)記憶體匯流排以800MHz之DDR(雙資料速率)產生時脈信號。通常，兩個或兩個以上記憶體晶粒經堆疊以增加封裝中之記憶體容量。
用於將兩個(或兩個以上)記憶體晶粒置於封裝中之典型組態係垂直地堆疊記憶體晶粒(例如，將一個記憶體晶粒直接堆疊於另一記憶體晶粒之頂部上)。垂直堆疊記憶體晶粒減小了封裝的總體厚度。然 而，垂直堆疊晶粒產生將兩個晶粒皆連接至封裝上之端子之難題。通常，晶粒上之I/O使用線接合在記憶體晶粒之頂部(其中堆疊中之底部記憶體晶粒之至少部分突出超出頂部記憶體晶粒之邊緣)與封裝之基板上之端子之間連接至端子。
然而，使用線接合增加封裝之高度，此係由於線接合路徑經分隔以防止自每一記憶體晶粒之不同線接合之短接。另外，線接合可包括導致3D域中之大迴路電感之線迴路。大迴路電感可歸因於L di/dt及/或不良信號整合而導致電壓雜訊。使用線接合亦可能限制可用之I/O之數目及至晶粒之電力遞送。
在封裝中自記憶體晶粒至端子之穿矽通孔(TSV)已用作克服一些線接合難題之解決方案。然而，提供TSV需要特殊記憶體晶粒、新增若干額外處理步驟且相對昂貴。覆晶封裝已廣泛用於進階SoC積體電路。覆晶封裝可提供較短(較小)阻抗，且允許更多I/O連接及電力/接地接腳。
在某些實施例中，一種半導體器件封裝包括以晶粒之間的距離至多為約50μm之面對面組態耦接至記憶體晶粒之邏輯晶粒。連接晶粒之端子可具有小於將邏輯晶粒耦接至重分佈層之端子或連接之互連間距的小互連間距(例如，至多約50μm)。將邏輯晶粒耦接至重分佈層之端子或連接可經扇出或隔開以提供用於至記憶體晶粒之連接的空間。
在一些實施例中，在囊封邏輯晶粒之前及將邏輯晶粒連接至重分佈層之前以晶圓級製程將記憶體晶粒連接至邏輯晶粒。在一些實施例中，在囊封邏輯晶粒之後及將邏輯晶粒連接至重分佈層之後以晶圓級製程將記憶體晶粒連接至邏輯晶粒。在某些實施例中，重分佈層經由重分佈層中之佈線將邏輯晶粒及/或記憶體晶粒(經由至邏輯晶粒之 連接)耦接至重分佈層之下部表面上之端子(例如，球狀柵格陣列)。重分佈層亦可經由重分佈層中之佈線將邏輯晶粒及/或記憶體晶粒耦接至經耦接至重分佈層之離散器件。
100‧‧‧載體
102‧‧‧邏輯晶粒
104‧‧‧端子
106‧‧‧端子
108‧‧‧記憶體晶粒
110‧‧‧囊封劑
112‧‧‧重分佈層
112'‧‧‧重分佈層
114‧‧‧佈線
114'‧‧‧佈線
116‧‧‧端子
118‧‧‧離散器件
120‧‧‧半導體器件封裝
120'‧‧‧半導體器件封裝
122‧‧‧連接
124‧‧‧端子
當結合附圖時，將藉由參考以下對目前較佳但仍為說明性之實施例的詳細描述而更全面地瞭解本文中所描述之方法與裝置之特徵及優點，在附圖中：圖1描繪耦接至載體之邏輯晶粒之截面表示。
圖2描繪耦接至載體上之邏輯晶粒之記憶體晶粒之截面表示。
圖3描繪至少部分囊封於囊封劑中之邏輯晶粒及記憶體晶粒之截面表示。
圖4描繪在囊封劑中使用端子耦接至重分佈層(RDL)之邏輯晶粒及記憶體晶粒之截面表示。
圖5描繪包括邏輯晶粒、記憶體晶粒及RDL之半導體器件封裝之截面表示。
圖6描繪至少部分囊封於囊封劑中且耦接至載體之邏輯晶粒之截面表示。
圖7描繪至少部分囊封於囊封劑中且耦接至RDL之邏輯晶粒之截面表示。
圖8描繪耦接至RDL上之端子之記憶體晶粒之截面表示。
圖9描繪耦接至RDL以形成封裝之端子之截面表示。
圖10描繪晶圓級載體上之複數個邏輯晶粒之截面表示。
圖11描繪形成於晶圓級RDL上之複數個封裝之一實施例之截面表示。
儘管所描述之實施例容易具有各種修改及替代形式，但其特定實施例在圖式中藉助於實例而展示且將在本文中詳細描述。圖式可能 並非按比例繪製。應理解，圖式及其詳細描述並非意欲將實施例限於所揭示之特定形式，而相反地，希望涵蓋由所附申請專利範圍界定之精神及範疇內之所有修改、等效物及替代物。
圖1至圖5描繪用於形成半導體器件封裝之處理流程之一實施例之截面表示。圖1描繪耦接至載體100之邏輯晶粒102之截面表示。載體100可為適合於支撐及承載薄基板之任何載體。舉例而言，載體100可為用於由矽、玻璃或鋼製成之薄基板之暫時性基板。舉例而言，邏輯晶粒102可為系統單晶片(「SoC」)。在一些實施例中，邏輯晶粒102為覆晶邏輯晶粒。
在某些實施例中，端子104耦接至邏輯晶粒102之下部表面。端子104可包括銅、鋁或另一適合之導電材料。在一些實施例中，端子104塗有焊料或塗有Sn。在某些實施例中，端子104為C4凸塊。端子104可包括用於邏輯晶粒102之扇出連接及用於邏輯晶粒之電力遞送連接。
在某些實施例中，端子104經扇出或隔開以允許用於待耦接至邏輯晶粒102之端子106的空間。端子106可包括銅、鋁或另一適合之導電材料。端子106可包括用於將邏輯晶粒102耦接至記憶體晶粒之連接。
圖2描繪耦接至載體100上之邏輯晶粒102之記憶體晶粒108的截面表示。在某些實施例中，記憶體晶粒108為DDR(雙資料速率)晶粒(例如，8GB DDR晶粒)。在一些實施例中，記憶體晶粒108為覆晶記憶體晶粒。在一些實施例中，記憶體晶粒108為離散記憶體晶粒。在一些實施例中，記憶體晶粒108包括兩個或兩個以上記憶體晶粒(例如，垂直堆疊之記憶體晶粒)。儘管記憶體晶粒108特定地展示於圖2中，但其他積體電路(IC)晶粒亦可類似地耦接至載體100上之邏輯晶 粒102。
記憶體晶粒108可使用端子106耦接至邏輯晶粒102。在某些實施例中，記憶體晶粒108以面對面組態耦接至邏輯晶粒102(例如，邏輯晶粒之下部表面)。舉例而言，記憶體晶粒108與邏輯晶粒102可使用覆晶接合製程而耦接，此係由於記憶體晶粒及邏輯晶粒兩者皆可為覆晶晶粒。
在某些實施例中，端子106具有至多約50μm之互連間距。在一些實施例中，端子106具有在約30μm與約50μm之間的互連間距。在某些實施例中，端子106具有小於端子104之互連間距。端子106之小互連間距允許在邏輯晶粒102與記憶體晶粒108之間的高互連密度。
端子106亦可提供在記憶體晶粒108與邏輯晶粒102之間的小連接距離。在某些實施例中，記憶體晶粒108之上部表面距邏輯晶粒102之下部表面最多約50μm。在一些實施例中，記憶體晶粒108之上部表面距邏輯晶粒102之下部表面在約10μm與約50μm之間。
在記憶體晶粒108耦接至邏輯晶粒102之後，邏輯晶粒及記憶體晶粒(以及端子104及端子106)可至少部分囊封於囊封劑110中，如圖3中所示。舉例而言，囊封劑110可為聚合物或模製化合物，諸如包覆模製物或曝露模製物。在一些實施例中，囊封劑110包覆模製於邏輯晶粒102、記憶體晶粒108及端子104、106上，且囊封劑隨後經磨蝕或以其他方式拋光以曝露端子104之至少一部分。
囊封之後，自邏輯晶粒102及囊封劑110移除載體100，且邏輯晶粒使用端子104耦接至重分佈層(例如，邏輯晶粒、記憶體晶粒108、端子104及端子106轉移至重分佈層)。圖4描繪在囊封劑110中使用端子104耦接至重分佈層(RDL)112之邏輯晶粒102及記憶體晶粒108之截面表示。端子104可將邏輯晶粒102連接至RDL 112中之佈線114。佈線114可將邏輯晶粒102連接至其他組件及/或耦接至RDL 112之其他端 子。
RDL 112可包括諸如(但不限於)PI(聚醯亞胺)、PBO(聚苯并噁唑)、BCB(苯并環丁烯)及WPR(晶圓光阻劑，諸如可以包括WPR-1020、WPR-1050及WPR-1201之商標名WPR購得之酚醛樹脂及聚(羥基苯乙烯)(PHS)(WPR為日本東京JSR公司之註冊商標))之材料。可使用此項技術中已知之技術(例如，用於聚合物沈積之技術)形成RDL 112。
RDL 112可包括佈線114之一或多個層。在某些實施例中，RDL 112包括佈線114之兩個或兩個以上層。舉例而言，RDL 112可包括佈線114之兩個與五個之間的層。舉例而言，佈線114可為銅線或另一適合之電導線。RDL 112之厚度可取決於RDL中的佈線114之層之數目。舉例而言，佈線114之每一層可為約5μm與約10μm之間的厚度。因此，通常，RDL 112可具有至少約5μm且至多約50μm之厚度。
將邏輯晶粒102耦接至RDL 112之後，額外端子可耦接至RDL之下部表面以形成半導體器件封裝。圖5描繪包括邏輯晶粒102、記憶體晶粒108及RDL 112之半導體器件封裝120之截面表示。端子116耦接至RDL 112之下部表面。端子116可包括鋁、銅或另一適合之導電材料。在一些實施例中，端子116塗有焊料或塗有Sn。在一些實施例中，端子116形成球狀柵格陣列。
在一些實施例中，封裝120包括耦接至RDL 112之一或多個離散器件118。離散器件118可新增至封裝120，且使用此項技術中已知之技術在圖1至圖5中所示之處理流程中之任何點處耦接至RDL 112。離散器件118可為被動器件，諸如(但不限於)電阻器、電容器、電感器、變壓器、濾波器及耦合器。離散器件118可耦接至RDL 112。佈線114可將邏輯晶粒102(經由端子104)及/或記憶體晶粒108(經由邏輯器件及端子106)連接至端子116及/或離散器件118。在一些實施例中， 端子116用於將封裝120耦接至主機板、系統印刷電路板(PCB)或另一封裝。
圖6至圖9描繪用於形成半導體器件封裝之處理流程之一替代實施例之截面表示。圖6描繪至少部分囊封於囊封劑110中且耦接至載體100之邏輯晶粒102之截面表示。囊封之後，自邏輯晶粒102及囊封劑110移除載體100，且將邏輯晶粒及囊封劑耦接至RDL 112'(例如，邏輯晶粒及囊封劑轉移至重分佈層)，如圖7中所示。在某些實施例中，RDL 112'包括佈線114'之兩個或兩個以上層。在一些實施例中，RDL 112'具有約10μm與約50μm之間的厚度。
邏輯晶粒102可使用連接122耦接至RDL 112'中之佈線114'。連接122可包括將邏輯晶粒102耦接至RDL 112'中之佈線114'之著陸墊或其他端子。舉例而言，連接122可包括用於將佈線114'耦接至邏輯晶粒102之鋁或銅著陸墊或塗有焊料或塗有Sn之著陸墊。
在某些實施例中，如圖7中所示，RDL 112'包括端子124。端子124可為(例如)銅或另一適合之電導體。在某些實施例中，端子122為穿過RDL 112'之佈線之一或多個層(例如，端子為垂直地或接近垂直地將RDL之下部表面與RDL之上部表面直接連接之佈線)。在一些實施例中，端子124為用銅或另一電導體填充之穿過RDL 112'之通孔。舉例而言，通孔(諸如穿模通孔(TMV))可經形成而穿過RDL 112'，且接著可將銅鍍覆(或以其他方式填充)於通孔中以形成端子124。
在某些實施例中，端子124具有至多約50μm之互連間距。在一些實施例中，端子124具有在約30μm與約50μm之間的互連間距。在某些實施例中，端子124具有小於連接122之互連間距。
圖8描繪耦接至RDL 112'上之端子124之記憶體晶粒108之截面表示。將記憶體晶粒108耦接至端子124將該記憶體晶粒連接至邏輯晶粒102。使用端子124連接記憶體晶粒108與邏輯晶粒102直接且垂直或接 近垂直地經由RDL 112'連接晶粒。在某些實施例中，記憶體晶粒108與邏輯晶粒102成面對面組態。舉例而言，記憶體晶粒108可使用將記憶體晶粒及邏輯晶粒102以面對面組態置放之覆晶接合製程耦接至RDL 112'上之端子124。
圖9描繪耦接至RDL 112'以形成封裝120'之端子116之截面表示。儘管圖8及圖9描繪在記憶體晶粒108耦接至端子124之後耦接至RDL 112'之端子116，但應理解，此等步驟可反轉：在將記憶體晶粒耦接至端子124之前將端子116耦接至RDL。步驟之次序可取決於所要之處理流程及/或可影響步驟之次序的合意性之其他因素。類似地，有可能在將端子116耦接至RDL之後且在將記憶體晶粒108耦接至端子124之前在RDL 112'中形成端子124。
類似於圖5中所描繪之封裝120之實施例，圖9中所示之封裝120'可包括耦接至RDL 112'之一或多個離散器件118。可使用此項技術中已知之技術在圖6至圖9中所示之處理流程中之任何點處新增離散器件118至封裝120'且耦接至RDL 112'。
使用圖5中所示之端子106或圖9中所示之端子124以面對面組態連接邏輯晶粒102與記憶體晶粒108提供低成本、高頻寬之記憶體至邏輯(例如，SoC)互連。舉例而言，使用端子106或端子124以面對面組態連接邏輯晶粒102與記憶體晶粒108以高互連密度(例如，至多約50μm之互連間距)在晶粒之間提供小路徑長度(例如，小於約50μm)。小路徑長度及高互連密度在邏輯晶粒102與記憶體晶粒108之間提供高頻寬且低潛時之連接。
在某些實施例中，在晶圓級製程中同時形成複數個封裝120或封裝120'。舉例而言，圖1至圖3及圖6中所示之載體100可為晶圓級載體，在其上耦接有複數個邏輯晶粒102，如圖10中所示。載體100上之複數個邏輯晶粒102可根據圖1至圖5中之處理流程或圖6至圖9中之處 理流程經受後續處理以在晶圓級重分佈層(例如，RDL 112或RDL 112'可為晶圓級重分佈層)上分別形成複數個封裝120或封裝120'。圖11描繪形成於晶圓級RDL 112(或RDL 112')上之複數個封裝120(或120')之一實施例之截面表示。在RDL 112上形成封裝120後，封裝可經單一化(例如，如由圖11中之點線所示藉由分割或切割而分離)以按其最終格式形成個別封裝。
在某些實施例中，本文中所描述之封裝120及/或封裝120'為離散半導體器件封裝。在一些實施例中，封裝120及/或封裝120'用作PoP(「疊層封裝」)封裝中之頂部或底部封裝。當用於PoP封裝中時，封裝120及/或封裝120'可包括供用於PoP封裝中之額外連接及/或端子。舉例而言，封裝120及/或封裝120'可包括穿過囊封劑110之一或多個通孔(例如，穿模通孔(TMV))。
鑒於此描述，熟習此項技術者將瞭解其他修改及替代實施例。因此，本描述應解釋為僅為說明性的且係用於向熟習此項技術者教示執行所描述實施例之通用方式之目的。應理解，本文中所展示及描述之實施例之形式應被認為係目前較佳之實施例。元件及材料可替代本文中所說明及描述之彼等者，部件及製程可反轉，且某些特徵可單獨利用，對於受益於本描述之後的熟習此項技術者而言，所有此等將皆為顯而易見的。在不脫離如在以下申請專利範圍中所描述之精神及範疇的情況下可對本文中所描述之元件做出改變。
102‧‧‧邏輯晶粒
104‧‧‧端子
106‧‧‧端子
108‧‧‧記憶體晶粒
110‧‧‧囊封劑
112‧‧‧重分佈層
114‧‧‧佈線
116‧‧‧端子
118‧‧‧離散器件
120‧‧‧半導體器件封裝

Claims (9)

  1. 一種半導體器件封裝，其包含：一邏輯晶粒，其至少部分囊封於一囊封劑中；一記憶體晶粒，其以一面對面組態耦接至該邏輯晶粒之一下部表面；一重分佈層，其耦接至該邏輯晶粒之該下部表面；複數個端子，其耦接至該重分佈層之一下部表面，其中該等端子中之至少一些經由該重分佈層中之佈線連接至該邏輯晶粒；及一或多個被動器件，其耦接至該重分佈層之一上部表面且與該邏輯晶粒隔開，其中該等被動器件至少部分囊封於該囊封劑中。
  2. 如請求項1之封裝，其進一步包含將該記憶體晶粒耦接至該邏輯晶粒之額外端子，其中該等額外端子具有比耦接至該重分佈層之該等端子小之一互連間距。
  3. 如請求項1之封裝，其進一步包含將該邏輯晶粒之該下部表面耦接至該重分佈層之複數個額外端子，其中該等額外端子經隔開以允許該記憶體晶粒耦接至該邏輯晶粒之該下部表面。
  4. 如請求項1之封裝，其中該邏輯晶粒之該下部表面直接附接至該重分佈層。
  5. 如請求項1之封裝，其中該記憶體晶粒至少部分囊封於該囊封劑中。
  6. 一種用於形成一半導體器件封裝之方法，其包含：將複數個第一端子耦接於一邏輯晶粒之一下部表面上，該邏輯晶粒之一上部表面耦接至一載體； 當該邏輯晶粒之該上部表面耦接至該載體時，將複數個第二端子耦接於該邏輯晶粒之該下部表面上，其中該等第二端子具有比該等第一端子小之一互連間距；當該邏輯晶粒之該上部表面耦接至該載體時，使用該等第二端子將一記憶體晶粒耦接至該邏輯晶粒，使得該記憶體晶粒以一面對面組態耦接至該邏輯晶粒；當該邏輯晶粒之該上部表面耦接至該載體時，將該邏輯晶粒、該記憶體晶粒、該等第一端子及該等第二端子至少部分囊封於一囊封劑中；將一重分佈層耦接至該等第一端子；及自該邏輯晶粒之該上部表面移除該載體。
  7. 如請求項6之方法，其中該等第二端子具有小於該等第一端子之一互連間距的一互連間距。
  8. 如請求項6之方法，其進一步包含將複數個第三端子耦接至該重分佈層之一下部表面，其中該等第三端子經由該重分佈層中之佈線連接至該邏輯晶粒。
  9. 如請求項6之方法，其進一步包含將一或多個被動器件耦接至該重分佈層之一上部表面且與該邏輯晶粒隔開，其中該等被動器件至少部分囊封於該囊封劑中。
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