TWI563803B - - Google Patents

Info

Publication number
TWI563803B
TWI563803B TW103103210A TW103103210A TWI563803B TW I563803 B TWI563803 B TW I563803B TW 103103210 A TW103103210 A TW 103103210A TW 103103210 A TW103103210 A TW 103103210A TW I563803 B TWI563803 B TW I563803B
Authority
TW
Taiwan
Application number
TW103103210A
Other languages
Chinese (zh)
Other versions
TW201503597A (en
Inventor
Hiroki Takahashi
Original Assignee
Ps4 Luxco Sarl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ps4 Luxco Sarl filed Critical Ps4 Luxco Sarl
Publication of TW201503597A publication Critical patent/TW201503597A/en
Application granted granted Critical
Publication of TWI563803B publication Critical patent/TWI563803B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
TW103103210A 2013-01-29 2014-01-28 Dll circuit and semiconductor device TW201503597A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013014453 2013-01-29

Publications (2)

Publication Number Publication Date
TW201503597A TW201503597A (en) 2015-01-16
TWI563803B true TWI563803B (en) 2016-12-21

Family

ID=51262272

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103103210A TW201503597A (en) 2013-01-29 2014-01-28 Dll circuit and semiconductor device

Country Status (4)

Country Link
US (1) US9543967B2 (en)
KR (1) KR20150110698A (en)
TW (1) TW201503597A (en)
WO (1) WO2014119558A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892764B1 (en) 2020-08-14 2021-01-12 Winbond Electronics Corp. Delay locked loop device and update method thereof

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160048512A (en) * 2014-10-24 2016-05-04 에스케이하이닉스 주식회사 Semiconductor apparatus with self tunning timing margin
US9601182B2 (en) 2015-05-08 2017-03-21 Micron Technology, Inc. Frequency synthesis for memory input-output operations
US9584105B1 (en) * 2016-03-10 2017-02-28 Analog Devices, Inc. Timing generator for generating high resolution pulses having arbitrary widths
US10110240B1 (en) * 2017-10-17 2018-10-23 Micron Technology, Inc. DLL circuit having variable clock divider
KR101989696B1 (en) 2017-11-30 2019-09-30 연세대학교 산학협력단 Apparatus and method having reduced static phase offset
US10339997B1 (en) * 2017-12-18 2019-07-02 Micron Technology, Inc. Multi-phase clock division
US10403340B2 (en) * 2018-02-07 2019-09-03 Micron Technology, Inc. Techniques for command synchronization in a memory device
US10431281B1 (en) * 2018-08-17 2019-10-01 Micron Technology, Inc. Access schemes for section-based data protection in a memory device
US10991411B2 (en) 2018-08-17 2021-04-27 Micron Technology, Inc. Method and apparatuses for performing a voltage adjustment operation on a section of memory cells based on a quantity of access operations
KR20200097903A (en) 2019-02-11 2020-08-20 삼성전자주식회사 Nonvolatile memory device
US10516403B1 (en) * 2019-02-27 2019-12-24 Ciena Corporation High-order phase tracking loop with segmented proportional and integral controls
CN110445492B (en) * 2019-09-09 2023-04-07 Oppo广东移动通信有限公司 Cross-clock-domain frequency division clock protection circuit, frequency division circuit, method and terminal equipment
US10965292B1 (en) 2020-06-08 2021-03-30 Winbond Electronics Corp. Delay-locked loop device and operation method therefor
JP7369829B1 (en) 2022-07-06 2023-10-26 華邦電子股▲ふん▼有限公司 A control circuit, a semiconductor memory device, and a method for controlling a semiconductor memory device.

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642762B2 (en) * 2001-07-09 2003-11-04 Broadcom Corporation Method and apparatus to ensure DLL locking at minimum delay
US6826247B1 (en) * 2000-03-24 2004-11-30 Stmicroelectronics, Inc. Digital phase lock loop
US7366270B2 (en) * 2000-12-20 2008-04-29 Primarion, Inc. PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator
US7403054B1 (en) * 2007-12-05 2008-07-22 International Business Machines Corporation Sub-picosecond multiphase clock generator
US7746134B1 (en) * 2007-04-18 2010-06-29 Altera Corporation Digitally controlled delay-locked loops
US20100213991A1 (en) * 2009-02-26 2010-08-26 Kabushiki Kaisha Toshiba Delay-locked loop circuit and method for synchronization by delay-locked loop
US20110204942A1 (en) * 2010-02-24 2011-08-25 Elpida Memory, Inc. Clock control circuit and semiconductor device including the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101027676B1 (en) * 2008-06-26 2011-04-12 주식회사 하이닉스반도체 Phase Synchronization Apparatus
KR101950320B1 (en) * 2012-06-29 2019-02-20 에스케이하이닉스 주식회사 Phase detection circuit and synchronization circuit using the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826247B1 (en) * 2000-03-24 2004-11-30 Stmicroelectronics, Inc. Digital phase lock loop
US7366270B2 (en) * 2000-12-20 2008-04-29 Primarion, Inc. PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator
US6642762B2 (en) * 2001-07-09 2003-11-04 Broadcom Corporation Method and apparatus to ensure DLL locking at minimum delay
US7746134B1 (en) * 2007-04-18 2010-06-29 Altera Corporation Digitally controlled delay-locked loops
US7403054B1 (en) * 2007-12-05 2008-07-22 International Business Machines Corporation Sub-picosecond multiphase clock generator
US20100213991A1 (en) * 2009-02-26 2010-08-26 Kabushiki Kaisha Toshiba Delay-locked loop circuit and method for synchronization by delay-locked loop
US20110204942A1 (en) * 2010-02-24 2011-08-25 Elpida Memory, Inc. Clock control circuit and semiconductor device including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892764B1 (en) 2020-08-14 2021-01-12 Winbond Electronics Corp. Delay locked loop device and update method thereof

Also Published As

Publication number Publication date
KR20150110698A (en) 2015-10-02
TW201503597A (en) 2015-01-16
US9543967B2 (en) 2017-01-10
WO2014119558A1 (en) 2014-08-07
US20150372683A1 (en) 2015-12-24

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