TWI559685B - Boost circuit and method for controlling boost signal output - Google Patents

Description

Boost circuit and method for controlling output of boost signal

The present invention relates to a booster circuit, and more particularly to a booster circuit having a control circuit that avoids collapse of the booster circuit, and a method for avoiding collapse of the booster circuit.

In semiconductor circuits, it may sometimes be necessary to apply a particular voltage value to a portion of the semiconductor circuit (e.g., a particular substrate or word line) that enables the semiconductor circuit to function properly. In some cases, the particular voltage is a relatively high voltage. This high voltage can be generated by a charge pump circuit that boosts the relatively low input voltage to a relatively high output voltage. In general, the charge pump circuit needs to operate with the clock signal, which requires a higher voltage level than the clock signal normally used in other parts of the semiconductor circuit. For example, if the supply voltage V _DD on the power rail of the semiconductor circuit is approximately 1.8V, the voltage level of the clock signal in the semiconductor circuit is also approximately 1.8V. In order for the charge pump circuit to generate a voltage higher than the supply voltage V _DD , a high voltage clock signal having a voltage level of approximately twice the supply voltage V _DD (ie, approximately 3.6 V) is required.

The boost circuit can be used to "boost" the voltage of an input clock signal and generate a high voltage clock signal (i.e., a boost clock signal) having a level approximately twice the supply voltage V _DD . The boosting circuit may include a plurality of semiconductor devices, including Field-Effect Transistors (FETs), such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). When the voltage of the input clock signal is boosted above V _DD , a boosted high voltage approximately twice the supply voltage V _DD may also be applied to one or more FETs.

Sometimes, a semiconductor circuit may need to switch between a low V _DD condition and a high V _DD condition (eg, between an operating condition where V _{DD is} approximately 1.8V and an operating condition where V _{DD is} approximately 3.3V). During operation when V _{DD is} approximately 3.3V, the boosted clock signal is approximately 6.6V, which may be higher than the breakdown voltage of one or more of the FETs, thus causing one or more FETs to collapse.

According to the present disclosure, a booster circuit is provided. The boosting circuit includes: a power rail for providing a supply voltage; a switching transistor for controlling the output of a boosting signal, a boosting signal outputted by a source of the switching transistor; and a timing and voltage control circuit, Used to generate an EQ signal to be applied to the gate of the switching transistor. The EQ signal has a one-level, which is an EQ high level, an EQ low level lower than the EQ high level or an EQ clamp level between the EQ low level and the EQ high level.

Still in accordance with the present disclosure, a method for controlling the output of a boost signal is provided. The method includes generating a one-bit EQ signal, the level It is an EQ high level, an EQ low level lower than the EQ high level, and one of the EQ clamp levels between the EQ low level and the EQ high level. The method further includes applying an EQ signal to one of the gates of a switching transistor to control the output of the boost signal.

The features and advantages of the present disclosure will be set forth in part in the description which follows. Such features and advantages will be realized and attained by the <RTIgt;

It is to be understood that the foregoing general description and the claims

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in FIG

BST1‧‧‧First boost source signal

BST2‧‧‧second boost source signal

BT1‧‧‧ first boost signal

BT2‧‧‧second boost signal

C1, C2‧‧‧ capacitor

CK1‧‧‧First boost clock signal

CK2‧‧‧second boost clock signal

CLK‧‧‧ input clock signal

EQ1‧‧‧First EQ signal

EQ2‧‧‧Second EQ signal

EQIN1‧‧‧First EQ input signal

EQIN2‧‧‧Second EQ input signal

M31 to M38‧‧‧O crystal

M71 to M77‧‧‧O crystal

PB1‧‧‧ first signal

PB2‧‧‧ second signal

PCLK1‧‧‧ first clock signal

PCLK2‧‧‧ second clock signal

PWCTL‧‧‧ power control signal

V _BOOST ‧‧‧Boost high level

V _BOOST-CK ‧‧‧Boost high clock level

V _CLAMP ‧‧‧EQ clamp level

V _DD ‧‧‧ supply voltage

V _{HIGH1 ‧‧‧The} first high standard

V _HIGH2 ‧‧‧ second highest level

V _ref ‧‧‧reference voltage

V _SHARE ‧‧‧pressure drop

100‧‧‧ boost circuit

102‧‧‧ Non-overlapping clock generation block

104‧‧‧Sequence and voltage control blocks

106‧‧‧Voltage boost block

302‧‧‧Power rail

304‧‧‧ Grounding terminal

Section 500‧‧‧

502‧‧‧Time delay element

503‧‧‧Logical Circuit

504‧‧‧AND gate

506‧‧‧OR gate

508‧‧‧EQ generating components

702‧‧‧First circuit branch

704‧‧‧Second circuit branch

706‧‧‧ Third Circuit Branch

708‧‧‧EQ output terminal

710‧‧‧Inverter

1 is a diagram of a booster circuit in accordance with an exemplary embodiment.

2 is a waveform diagram of the input clock signal CLK, the first clock signal PCLK1, and the second clock signal PCLK2 according to an exemplary embodiment.

FIG. 3 is a circuit diagram of a voltage boosting block of a booster circuit in accordance with an exemplary embodiment.

4 is a waveform diagram of the first boosting source signal BST1, the second boosting source signal BST2, the first boosting signal BT1, and the second boosting signal BT2 according to an exemplary embodiment.

FIG. 5 is a diagram showing a timing of one of the boosting circuits and a segment of the voltage control block according to the exemplary embodiment.

6 is a waveform diagram of the first clock signal PCLK1, the delayed first clock signal PCLK1, the first boost source signal BST1, and the first EQ input signal EQIN1 according to the exemplary embodiment.

Figure 7 is a circuit diagram showing an EQ generating component of a timing and voltage control block in accordance with an exemplary embodiment.

8A and 8B are diagrams showing waveforms of the first EQ input signal EQIN1, the power control signal PWCTL, the first equalization signal EQ1, and the second equalization signal EQ2 during low V _DD operation according to an exemplary embodiment, and Waveforms of the first EQ input signal EQIN1, the second signal PB2, the power control signal PWCTL, the first equalization signal EQ1, and the second equalization signal EQ2 during high V _DD operation.

9A and 9B are respectively a first equalized signal EQ1, a second equalized signal EQ2, a first boosted source signal BST1, and a second boosted during low V _DD and high V _DD operations according to an exemplary embodiment. A waveform diagram of the source signal BST2, the first boosting signal BT1, the second boosting signal BT2, the first boosting clock signal CK1, and the second boosting clock signal CK2.

Embodiments in accordance with the present disclosure include a boost circuit capable of maintaining a high output voltage and a method for avoiding collapse of the boost circuit.

Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings. Wherever possible, the same reference numerals will be used to the

FIG. 1 illustrates a booster circuit 100 in accordance with one embodiment of the present disclosure. The boosting circuit 100 is configured to generate a boosting clock signal having a boosted high clock level that is higher than the high clock level of the input clock signal (the boosting high clock position is approximately twice The high clock position of the input clock signal is about the same as the supply voltage V _DD . In some embodiments, as shown in FIG. 1, the boosting circuit 100 generates two boosting clock signals, that is, a first boosting clock signal CK1 and a second boosting clock signal CK2.

In accordance with an embodiment of the present disclosure, boost circuit 100 is operative to operate under both low _VDD operating conditions and high _VDD operating conditions and to switch between two operating conditions. As used in this disclosure, low V _DD means that such a V _DD does not cause the boosted clock signal's boosted high pulse level to be higher than the breakdown voltage of the electronic components in the boost circuit 100, but high V _DD indicates that such a V _DD may cause the boosted clock signal to have a boosted high clock level higher than the breakdown voltage of the electronic components in the booster circuit 100. For example, the low V _DD can be approximately 1.65V to approximately 2V, while the high V _DD can be approximately 2.7V to approximately 3.6V. In some embodiments, the low V _DD can be approximately 1.8V, while the high V _DD can be approximately 3.3V.

Referring to FIG. 1, the booster circuit 100 includes a non-overlapping clock generation block 102, a timing and voltage control block 104, and a voltage boost block 106. The non-overlapping clock generation block 102 is configured to generate the first clock signal PCLK1 and the second clock signal PCLK2 based on the input clock signal CLK.

FIG. 2 illustrates an exemplary waveform of the input clock signal CLK, the first clock signal PCLK1, and the second clock signal PCLK2. According to an embodiment of the present disclosure, the input clock signal CLK, the first clock signal PCLK1, and the second clock signal PCLK2 both have a high level approximately equal to V _DD and a low level approximately equal to the ground voltage (ie, 0V). The period is, for example, 40 ns. In the following, unless otherwise stated, the high level of a waveform is considered to be approximately V _DD , but may be a little lower than V _DD due to parasitic resistance. Again, the low level of a waveform is considered to be approximately 0V, but may be a little higher than 0V due to parasitic resistance. The difference between the high level and V _{DD and} between the low level and 0V is small because they result from a voltage drop such as a parasitic capacitance. As shown in FIG. 2, the first clock signal PCLK1 and the second clock signal PCLK2 do not overlap each other, that is, the first clock signal PCLK1 and the second clock signal PCLK2 do not become high at the same time. Within one cycle, the first clock signal PCLK1 rises from a low level to a high level after a time delay of the input clock signal CLK rising from a low level to a high level, and the first clock signal PCLK1 falls from a high level. The low level is about the same time as the input clock signal CLK falls from a high level to a low level. Similarly, the second clock signal PCLK2 rises from a low level to a high level after a time delay in which the input clock signal CLK falls from a high level to a low level, and the second clock signal PCLK2 falls from a high level to a low level. It is about the same time as the input clock signal CLK rises from a low level to a high level. Hereinafter, the transition of one waveform from one level to another is also referred to as the edge of the waveform. The transition of a waveform from a low level to a high level is also referred to as the rising edge of the waveform, and the transition of the waveform from a high level to a low level is also referred to as a falling edge.

Referring again to FIG. 1, the first clock signal PCLK1 and the second clock signal PCLK2 are input to the timing and voltage control block 104, and the timing and voltage control are performed. The block 104 generates a first boost source signal BST1 and a second boost source signal BST2 to be boosted by the voltage boost block 106. The first boost source signal BST1 and the second boost source signal BST2 also participate in the operation of the control voltage boost block 106. The timing and voltage control block 104 further generates a first equalization (EQ) signal EQ1 and a second EQ signal EQ2, which are also used to control the operation of the voltage boost block 106. As will be discussed later in this disclosure, the first EQ signal EQ1 and the second EQ signal EQ2 are used to control the conduction and non-conduction operations of a switching element (eg, a switching transistor) that outputs a boosted clock signal.

FIG. 3 illustrates a voltage boost block 106 in accordance with one embodiment of the present disclosure. The exemplary voltage boost block 106 shown in FIG. 3 has a "mirror" structure (i.e., a symmetrical structure), and the "mirror" structure includes transistors M31-M38 and capacitors C1 and C2. The transistor M31-M38 is a metal oxide semiconductor field effect transistor (MOSFET), in which the transistors M31, M32, M35, M36, M37 and M38 are n-channel MOSFETs (n-MOS), and the transistors M33 and M34 are It is a p-channel MOSFET (p-MOS). As will be seen from the discussion of Figure 3 and the disclosure of this disclosure, the gate and source/drain are for each of the transistors M31, M32, M35 and M36, even during high V _DD operation. The voltage difference applied between them is relatively low, and this voltage difference does not exceed the breakdown voltage of the oxide, that is, the voltage at which the gate oxide of the transistor is destroyed. Hereinafter, unless otherwise stated, the oxide breakdown voltage of the transistor is also referred to as the breakdown voltage of the transistor. Thus, for transistors M31, M32, M35, and M36, a thin oxide n-MOS with a lower threshold voltage can be used to reduce power consumption and charge sharing time.

As shown in FIG. 3, the drains of the transistors M31 and M32 are connected to the power rail 302, and the power rail 302 provides the supply voltage V _DD . The transistors M31 and M32 form a charging path, and the charging path together with the capacitors C1 and C2 generates the first boosting signal BT1 and the second boosting with the first boosting source signal BST1 and the second boosting source signal BST2 as inputs. Signal BT2. FIG. 4 is a diagram showing exemplary waveforms of the first boosting source signal BST1, the second boosting source signal BST2, the first boosting signal BT1, and the second boosting signal BT2. This disclosure will further discuss the generation of the first boost source signal BST1 and the second boost source signal BST2. It can be seen from FIG. 4 that when the second boosting source signal BST2 rises from the low level to the high level, the first boosting signal BT1 is charged to the first high level V _HIGH1 by the power rail 302 and maintained at the voltage level. Until the first boost source signal BST1 rises from the low level to the high level, at this time, the first boost signal BT1 is boosted from the first high level V _HIGH1 to the boost high level V _BOOST , and the boost high level V _BOOST can be about 1.8 times to about 2 times V _DD . Ideally, the first high level V _HIGH1 will be the same as V _DD . However, as described above, due to the parasitic resistance and capacitance of the electronic components in the booster circuit 100, the first high level V _HIGH1 is lower than V _DD . When the first boost source signal BST1 is lowered from the high level to the low level, the first boost signal BT1 is decreased from the boost high level V _BOOST to the second high level V _HIGH2 . Similarly, because of parasitic resistance and capacitance, the second high level V _HIGH2 is above the ground level but below V _DD and the first high level V _HIGH1 . The change of the second boosting signal BT2 with time is similar to the first boosting signal BT1, but has a different phase, and thus is not described in detail herein.

Please refer to Figure 3 again, the source of the transistors M37 and M38 Connected to the ground terminal 304, the drains of the transistors M37 and M38 are connected to the sources of the transistors M35 and M36, and the gates of the transistors M37 and M38 are respectively driven by the second boost source signal BST2 and the first boost source. Controlled by signal BST1. In addition, the gates of the transistors M35 and M36 are connected to the power rail 302, and therefore, the transistors M35 and M36 are always turned on during operation of the booster circuit 100. The transistors M35, M36, M37 and M38 form a discharge path. The discharge path is used to pull the first boosting clock signal CK1 to a low level when the second boosting source signal BST2 rises to a high level to conduct the conducting crystal M37. Similarly, the discharge path is also used to pull the second boosting clock signal CK2 to a low level when the first boosting source signal BST1 rises to a high level to conduct the conducting crystal M38. Transistors M35 and M36 are inserted in the discharge path to avoid large peak discharge currents and are used to avoid breakdown of transistors M37 and M38, respectively.

The transistors M33 and M34 function as charge sharing switching elements, and the charge sharing switching elements respectively control the outputs of the first boosting clock signal CK1 and the second boosting clock signal CK2. That is, the transistors M33 and M34 are the switching transistors in the voltage boosting block 106. For example, as shown in FIG. 3, when the second EQ signal EQ2 is at the level of the conducting transistor M33, the transistor M33 receives the first boosting signal BT1 at its drain and outputs the first liter at its source. Press the clock signal CK1. Similarly, when the first EQ signal EQ1 is at the level of the conducting crystal M34, the transistor M34 receives the second boosting signal BT2 at its drain and outputs the second boosting clock signal CK2 at its source. An exemplary waveform of the first EQ signal EQ1, the second EQ signal EQ2, the first boosted clock signal CK1, and the second boosted clock signal CK2 follows This will be explained later in this disclosure.

As described above, the first boosting source signal BST1, the second boosting source signal BST2, the first EQ signal EQ1, and the second EQ signal EQ2 are generated by the timing and voltage control block 104. In accordance with an embodiment of the present disclosure, timing and voltage control block 104 includes two nearly identical segments. One of the two sections is for generating the first boost source signal BST1 and the first EQ signal EQ1, and the other section is for generating the second boost source signal BST2 and the second EQ signal EQ2. For example, FIG. 5 illustrates an exemplary section 500 of the timing and voltage control block 104 for generating a first boost source signal BST1 and a first EQ signal EQ1. In the timing and voltage control block 104, another segment for generating the second boost source signal BST2 and the second EQ signal EQ2 is similar to the segment 500 and thus is not depicted herein.

As shown in FIG. 5, section 500 includes a time delay element 502 for generating a delayed signal based on an input signal. For example, the time delay element 502 delays the first clock signal PCLK1 to generate a delayed first clock signal PCLK1. That is, the output of the time delay element 502 (i.e., the delayed first clock signal PCLK1) has a waveform similar to the first clock signal PCLK1, but is delayed by, for example, about 2 ns. Both the first clock signal PCLK1 and the delayed first clock signal PCLK1 are input to a logic circuit 503 to generate a first boost source signal BST1 and a first EQ signal EQ1. In some embodiments, as shown in FIG. 5, logic circuit 503 includes an AND gate 504, an OR gate 506, and an EQ generating component 508. Specifically, the delayed first clock signal PCLK1 is associated with the first clock signal The number PCLK1 is input together to the AND gate 504 to generate a first boost source signal BST1. Similarly, the delayed first clock signal PCLK1 is also input to the OR gate 506 together with the first clock signal PCLK1 to generate a first EQ input signal EQIN1, which is then input to the EQ generating component 508 to generate a first An EQ signal EQ1.

FIG. 6 is a diagram showing an exemplary waveform of the first clock signal PCLK1, the delayed first clock signal PCLK1, the first boost source signal BST1, and the first EQ input signal EQIN1, each of which is at a high level and a low level. Change between quasi. As can be seen from Fig. 6, within one cycle, the rising edge of the first boosting source signal BST1 coincides with the rising edge of the delayed first clock signal PCLK1. That is, when the delayed first clock signal PCLK1 rises from a low level to a high level, the first boost source signal BST1 rises from a low level to a high level at about the same time. The falling edge of the first boost source signal BST1 coincides with the falling edge of the first clock signal PCLK1. That is, when the first clock signal PCLK1 is lowered from a high level to a low level, the first boost source signal BST1 is lowered from a high level to a low level at about the same time. Moreover, the rising edge of the first EQ input signal EQIN1 coincides with the rising edge of the first clock signal PCLK1, and the falling edge of the first EQ input signal EQIN1 coincides with the falling edge of the delayed first clock signal PCLK1. That is, the first EQ input signal EQIN1 rises before the first boost source signal BST1 rises and falls after the first boost source signal BST1 falls. It can be noted that due to system delay, the two edges that coincide with each other do not mean that they rise or fall at exactly the same time. For example, above the first boost source signal BST1 The rising edge may be slightly behind the rising edge of the delayed first clock signal PCLK1, which is typically less than the deliberate delay caused by the time delay element 502.

FIG. 7 illustrates an EQ generating component 508 exemplified in accordance with one embodiment of the present disclosure. The EQ generating component 508 includes a first circuit branch 702, a second circuit branch 704, and a third circuit branch 706 for generating different portions of the waveform of the first EQ signal EQ1. The first EQ signal EQ1 is from the EQ output terminal. 708 output. As shown in FIG. 7, the first circuit branch 702 and the second circuit branch 704 are connected between the power rail 302 and the EQ output terminal 708, and the third circuit branch 706 is connected to the ground terminal 304 and the EQ output terminal 708. between.

In the example shown in Figure 7, the EQ generating component 508 includes an inverter 710 and transistors M71-M77 controlled by different signals. In Fig. 7, the transistors M71, M74, M75, and M76 are p-MOS, and the transistors M72, M73, and M77 are n-MOS. The first circuit branch 702 includes a transistor M71. The second circuit branch 704 includes transistors M74, M75, and M76. The third circuit branch 706 includes transistors M72, M73, and M77.

In accordance with an embodiment of the present disclosure, EQ generating component 508 is used for operating conditions of low V _DD operating conditions (eg, from about 1.65 V to about 2 V) and high V _DD operating conditions (eg, from about 2.7 V to about 3.6 V). Work under. In the example shown in Figure 7, transistors M72 and M76 are controlled by a power supply control signal PWCTL that keeps transistor M72 conducting and transistor M76 non-conducting during operation under low _VDD operating conditions. The transistor M72 is kept non-conductive and the transistor M76 is turned on during operation under high V _DD operating conditions. That is, when the EQ generating component 508 operates under low _VDD operating conditions, the second circuit branch 704 is turned off, thereby not affecting the generation of the first EQ signal EQ1. When the EQ generating component 508 is operating under high _VDD operating conditions, the second circuit branch 704 is kicked in to affect the generation of the first EQ signal EQ1.

8A is a diagram showing waveforms of the first EQ input signal EQIN1, the power control signal PWCTL, and the first EQ signal EQ1 when the illustrated EQ generating element 508 shown in FIG. 7 operates under low V _DD operating conditions. Although FIG. 8A does not show the waveform of the first signal PB1 (ie, the output of the inverter 710), it will be apparent to those skilled in the art that the first signal PB1 is only the inverted signal of the first EQ input signal EQIN1. In this example, the power control signal PWCTL is set to a high level to keep the transistor M72 conducting and the transistor M76 not conducting. As shown in FIG. 8A, under the condition of low V _DD operation, the first EQ signal EQ1 has a level of EQ high level or EQ low level, and its level is the same as the high level and the low level of the first EQ input signal EQIN1. In accordance with an embodiment of the present disclosure, the EQ high level is approximately equal to V _DD and the EQ low level is approximately equal to 0V.

When the EQ generating component 508 is operating under high _VDD operating conditions, as shown in FIG. 8B, the power control signal PWCTL is set to a low level to keep the transistor M72 off and the transistor M76 turned on. In accordance with an embodiment of the present disclosure, the transistor M74 in the second circuit branch 704 is controlled by a reference voltage V _ref such that the transistor M74 remains in a partially conductive state and there is a voltage drop V _SHARE (eg, approximately 2V). ) across the drain and source of transistor M74. Therefore, when the transistor M75 is turned on, the voltage applied to the EQ output terminal is not a voltage of about V _DD but a voltage of about V _DD -V _SHARE . That is, the transistor M74 controlled by the reference voltage V _ref acts as a voltage clamping component, and clamps the voltage outputted by the EQ output terminal to the EQ clamp level V _CLAMP , which is approximately equal to V _DD -V _SHARE .

In some embodiments, other electronic components can be used as the voltage clamping component instead of the _Vref controlled transistor M74. For example, a FET coupled to a diode, or a decoupling capacitor, can also be used as a voltage clamping component. The use of a FET coupled to a diode can reduce the area of the boost circuit 100 because the reference voltage V _{ref is} not required to be generated by the circuit.

As described above, during high V _DD operation, the power supply control signal PWCTL is set to a low level, so that the transistor M72 does not conduct during this operation, which corresponds to the third circuit branch 706 not including the transistor M72 but only the transistor. M73 and M77. As can be seen from FIG. 7, both the transistor M77 in the third circuit branch 706 and the transistor M75 in the second circuit branch 704 are both identical to the second signal PB2 (ie, the second EQ input signal EQIN2 is inverted). Signal) is controlled. Since the transistors M75 and M77 belong to the opposite type (in the example shown in Fig. 7, one is p-MOS and the other is n-MOS), they are sequentially turned on and off. That is, when the transistor M75 is turned on, the transistor M77 is not turned on, and vice versa. Similarly, the transistors M71 and M73 are also of the opposite type and are controlled by the same first signal PB1 (i.e., the inverted signal of the first EQ input signal EQIN1), thereby being sequentially turned on and off. That is, when the transistor M71 is turned on, the transistor M73 is not turned on, and vice versa. This mechanism ensures that during high V _DD operation, the first circuit branch 702, the second circuit branch 704, and the third circuit branch 706 are sequentially output to the EQ output terminal 708 to generate the first EQ signal EQ1 in the order of EQ high level (approximately V _DD ), EQ clamp level (approximately V _DD -V _SHARE ) and EQ low level (approximately 0V).

8B is a diagram showing the first EQ input signal EQIN1, the second signal PB2, the power control signal PWCTL, and the first EQ signal EQ1 when the illustrated EQ generating component 508 shown in FIG. 7 operates under high V _DD operating conditions. An exemplary waveform. In accordance with an embodiment of the present disclosure, the second signal PB2 is a waveform similar to the first signal PB1 and is generated by another segment of the timing and voltage control block 104. That is, the second signal PB2 is substantially an inverted signal of the second EQ input signal EQIN2. Figures 8A and 8B also show waveforms of the second EQ signal EQ2 during low V _DD operation and high V _DD operation, respectively, for comparison.

The waveforms as discussed above (ie, the first boost source signal BST1, the second boost source signal BST2, the first EQ signal EQ1, and the second EQ signal EQ2) are input to the voltage rise as shown in FIG. The nip 106 is configured to generate a first boosting clock signal CK1 and a second boosting clock signal CK2. Figures 9A and 9B illustrate a first EQ signal EQ1, a second EQ signal EQ2, a first boost source signal BST1, a second boost source signal BST2, and a first rise during low V _DD and high V _DD operations, respectively. An exemplary waveform of the pressure signal BT1, the second boosting signal BT2, the first boosting clock signal CK1, and the second boosting clock signal CK2. When the first boost signal BT1 is at the boost high level V _BOOST , the first boost clock signal CK1 is also located at the boost high clock level V _BOOST-CK , which is approximately equal to the boost high level V _BOOST . In fact, due to the parasitic resistance and capacitance of the transistor M33, the boosted high clock level V _BOOST-CK at the first boosting clock signal CK1 may be lower than the boost high level of the first boost signal BT1. V _BOOST . Similarly, when the second boosting signal BT2 is located at the boosting high level V _BOOST , the second boosting clock signal CK2 is also located at the boosting high clock level V _BOOST-CK , which is approximately equal to the boosting high level V _{BOOST .} . In fact, due to the parasitic resistance and capacitance of the transistor M34, the boosted high clock level V _BOOST-CK at the second boosting clock signal CK2 may be lower than the boost high level of the second boost signal BT2. V _BOOST .

As can be seen from FIG. 9B, during the high V _DD operation, the second EQ signal EQ2 is located in the EQ clamp level V _CLAMP for the time period, and the first boost clock signal CK1 is located at the boost high time. The time period of the pulse level V _BOOST-CK . Similarly, the time period during which the first EQ signal EQ1 is located at the EQ clamp level V _{CLAMP is} a time period in which the second boost clock signal CK2 is located at the boost high clock level V _BOOST-CK . That is, whenever the output boost signal is at a boosted high clock level that can cause the switching element (ie, the switching transistor in the example shown in FIG. 3) to collapse, a voltage equal to the EQ clamp level V _CLAMP It is applied to the gate of the switching transistor, which can reduce the voltage drop between the gate and the source of the switching transistor, so as to avoid the breakdown of the switching transistor. In accordance with an embodiment of the present disclosure, the EQ clamp level V _CLAMP can be controlled by controlling the voltage drop V _SHARE across a voltage clamping component (e.g., transistor M74 shown in FIG. 7). The voltage drop across the transistor M74, V _SHARE, can be controlled by controlling the reference voltage V _ref .

To simplify the illustration, each edge of each of the waveforms shown in the drawings of the present disclosure is depicted as a straight vertical line. I can notice that due to the example For delays caused by parasitic RC circuits, gate delays, or delays controlled by the clock counter, the edges cannot be straight vertical lines, but may be bent, bent, or slanted lines. Moreover, in the present disclosure, it is assumed that the voltage boosting block 106 is symmetrical, so that the output from the left and right halves of the voltage boosting block 106 are similar to each other except that their respective phases are different. For example, as shown in FIGS. 9A and 9B, the waveforms of the first boosting signal BT1 and the second boosting signal BT2 are identical to each other except for their respective phases, the first boosting clock signal CK1 and the second. The boosting clock signals CK2 are identical to each other except for their respective phases. In practice, however, since there is a difference between the same electronic components in the booster circuit 100, the outputs from the left and right halves of the voltage boost block 106 may be different from each other. For example, the boosting high level of the first boosting signal BT1 may be different from the boosting high level of the second boosting signal BT2, and the boosting high clocking level of the first boosting clock signal CK1 may be different. The boosting of the second boosting clock signal CK2 is at a high clock level.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

BST1‧‧‧First boost source signal

BST2‧‧‧second boost source signal

CK1‧‧‧First boost clock signal

CK2‧‧‧second boost clock signal

CLK‧‧‧ input clock signal

EQ1‧‧‧First EQ waveform

EQ2‧‧‧Second EQ waveform

PCLK1‧‧‧ first clock signal

PCLK2‧‧‧ second clock signal

100‧‧‧ boost circuit

102‧‧‧ Non-overlapping clock generation block

104‧‧‧Sequence and voltage control blocks

106‧‧‧Voltage boost block

Claims (9)

A boosting circuit comprising: a power rail for providing a supply voltage; a switching transistor for controlling an output of a boosting signal, the switching transistor having a gate; and a timing and voltage control circuit for Generating an equalization (EQ) signal, the EQ signal is applied to the gate of the switching transistor, the EQ signal has a level, the level is an EQ high level, an EQ low level, and a One of the EQ clamp levels, the EQ low level is lower than the EQ high level, and the EQ clamp level is between the EQ low level and the EQ high level; wherein the boost signal is at a first time The cycle has a boost high level, and the timing and voltage control circuit is configured to generate the EQ clamp level during a fourth time period, the fourth time period covering the first time period. The booster circuit of claim 1, wherein the boost signal has a low level during a second time period; wherein the timing and voltage control circuit comprises: a first circuit branch connected to the power source Between the rail and an output terminal, the output terminal is coupled to the gate of the switch transistor, the first circuit branch is configured to generate the EQ high level to the output terminal during a third time period; a second circuit branch connected between the power rail and the output terminal, the second circuit branch being configured to generate the EQ during the fourth time period Clamping a level to the output terminal; and a third circuit branch connected between a ground terminal and the output terminal, the third circuit branching for generating the EQ low level to a fifth time period The output terminal; wherein the switch transistor is non-conducting when the EQ signal is at the EQ high level, and is turned on when the EQ signal is at the EQ low level or the EQ clamp level. The booster circuit of claim 2, wherein the first circuit branch comprises a transistor, the transistor being turned on during the third time period, such that the output terminal is electrically coupled to the power rail And the EQ high level is approximately equal to the supply voltage. The booster circuit of claim 2, wherein: the second circuit branch comprises: a transistor, the transistor is turned on during the fourth time period; and a voltage clamping component electrically coupled To the transistor, the voltage clamping component clamps the voltage output from the output terminal to the EQ clamping level, and the EQ clamping level is lower than the supply voltage. The booster circuit of claim 4, wherein: the electro-crystal system is a first transistor, and the voltage clamping component comprises a second transistor controlled by a reference voltage to enable the The second transistor is partially turned on, and the voltage drop across one of the second transistors is high enough that the output of the output terminal is clamped at the EQ clamp level. The booster circuit of claim 1, further comprising a discharge path electrically coupled between the off-cell transistor and a ground, the discharge path comprising: a discharge transistor, electrically coupled Connected to the ground, the discharge transistor is turned on to pull the boost signal to a low level; and a low threshold transistor is electrically coupled between the discharge transistor and the switch transistor, the low One of the gates of the threshold transistor is electrically coupled to the power rail. The booster circuit of claim 1, wherein the boosting signal is a first boosting signal, and the first boosting signal has a first boosting high level during a first time period. Having a first low level during a second time period, the first boost high level is higher than a breakdown voltage of the switching transistor, and the switching transistor is further configured to control the output of a second boost signal The second boosting signal is outputted by a source of the switching transistor, the second boosting signal having a second boosting high level during a third time period and a second during a fourth time period The low level is lower than the breakdown voltage of the switching transistor. A method for controlling an output of a boost signal, comprising: generating a one-bit EQ signal, the level being one of an EQ high level, an EQ low level, and an EQ clamping level, the EQ The low level is lower than the EQ high level, and the EQ clamp level is between the EQ low level and the EQ high level; Applying the EQ signal to one of the gates of a switching transistor to control the output of the boosting signal; wherein the boosting signal has a boosting high level during a first time period, and generating the EQ signal includes: The EQ clamp level is generated during a fourth time period, wherein the fourth time period covers the first time period. The method of claim 8, further comprising: generating a boost source signal for being boosted to generate the boost signal; and generating an EQ input signal for generating the EQ signal.