TWI559466B - Packaging structure and manufacturing method thereof - Google Patents

Description

Package structure and manufacturing method thereof

The present application relates to a package structure and a method of fabricating the same, and more particularly to a chip package structure and a method of fabricating the same.

In recent years, due to the rapid development of multimedia, the use of digital images has become more frequent, and the demand for many image processing devices has increased. Many digital imaging products today, including web cameras, digital cameras, even optical scanners and video phones, are captured by image sensors. image. The image sensor includes a CCD image sensor chip and a complementary CMOS image sensor chip, and can sensitively receive light emitted by a scene. Convert this light into a digital signal. Since these image sensing wafers need to receive a light source, the packaging method is different from that of a general electronic product.

Traditional CMOS Image Sensor (CIS) crystal In the Chip Scale Package (CSP), a whole layer of barrier layer is formed on a wafer having a plurality of wafers, and then a patterning process is performed to remove a portion of the barrier layer covering the wafer to form a frame. A barrier structure (DAM) of the wafer. However, since the barrier structure must have a certain thickness to maintain its supporting force and structural strength, in this case, when a part of the barrier layer covering the wafer is removed, it is easy to be completely removed due to its thick thickness, and thus it is easy to have a residue. The residue remains between the barrier structure and the photosensitive region, affecting the yield of the process, or increasing the spacing between the barrier structure and the photosensitive region to maintain a certain safe distance. However, this method limits the width of the barrier structure and thus affects The reliability of the package structure.

The present application provides a package structure and a method of manufacturing the same that can improve process yield.

The package structure manufacturing method of the present application includes the following steps. First, a wafer is provided, the wafer comprising a plurality of arrays of wafers. A barrier layer is formed on the wafer and the barrier layer covers the plurality of wafers. Performing a patterning process on the barrier layer to form a barrier structure, wherein the barrier structure includes a plurality of first frame surrounding portions, a plurality of second frame surrounding portions, and a plurality of stepped openings, each of the first frame surrounding portions protruding correspondingly The second frame enclosure defines a stepped opening in conjunction with the corresponding second frame enclosure. The stepped openings expose the wafers, respectively. Finally, a substrate is disposed on the barrier structure to cover the wafer and the blocking structure.

In a package structure manufacturing method according to an embodiment of the present application, wherein the wafer is A plurality of dicing streets are included, and the plurality of dicing streets are disposed between the plurality of wafers to separate the respective wafers. In this embodiment, the method further includes cutting the wafer along the plurality of dicing streets after the substrate is disposed on the barrier structure to form a plurality of package structures independent of each other.

The package structure of the present application includes a wafer, a barrier structure, and a substrate. The wafer includes a substrate and a photosensitive portion, and the photosensitive portion is located on the substrate. The blocking structure is disposed on the wafer and includes a first frame surrounding portion, a second frame surrounding portion and a stepped opening. The first frame surrounding portion and the second frame surrounding portion collectively surround the photosensitive portion to define a stepped opening. The stepped opening exposes the photosensitive portion, and the first frame surrounding portion is located on the substrate and protrudes from the second frame surrounding portion. The substrate is disposed on the barrier structure and covers the wafer and the barrier structure.

In an embodiment of the present application, the step of the patterning process further includes: first, forming a patterned mask layer on the barrier layer, wherein the patterned mask layer comprises a plurality of patterned openings. The wafers are respectively located in an orthographic projection range of the patterned openings on the wafer, each patterned opening includes a first opening and a plurality of second openings respectively surrounding the first openings to respectively expose the corresponding partial barrier layers, And the opening area of the second opening gradually decreases toward the direction away from the first opening. Next, the barrier layer is subjected to an exposure development process to remove a portion of the barrier layer exposed by the patterned opening to form a stepped opening.

In an embodiment of the present application, the step of the patterning process further includes: forming a patterned mask layer on the barrier layer, wherein the patterned mask layer comprises a plurality of mask patterns respectively covering the wafer in the barrier layer The front projection range, the reticle pattern includes a photoresist portion and a plurality of first openings, and the first openings respectively surround the photoresist portion And correspondingly partially blocking the barrier layer, and the opening area of the first opening gradually increases away from the photoresist portion. Next, the barrier layer is subjected to an exposure and development process to remove a portion of the plurality of patterned openings that are not exposed by the plurality of first openings to form a plurality of stepped openings.

In a method of manufacturing a package structure according to an embodiment of the present application, a shortest distance from each of the first frame enclosures to the corresponding wafer is less than 200 micrometers.

In a method of manufacturing a package structure according to an embodiment of the present application, a shortest distance from each of the first frame enclosures to the corresponding wafer is less than a shortest distance from the corresponding second frame enclosure to the corresponding wafer.

In the method of manufacturing a package structure according to an embodiment of the present application, the barrier structure is integrally formed.

In the method of manufacturing a package structure according to an embodiment of the present application, the substrate is a transparent substrate.

In the package structure manufacturing method of one embodiment of the present application, the plurality of wafers are image sensing wafers.

In a method of fabricating a package structure according to an embodiment of the present application, a first circuit layer is disposed on an upper surface of the wafer, and the plurality of wafers are electrically connected to the first circuit layer. In addition, the manufacturing method of this embodiment further includes: forming a plurality of via holes in the wafer. Then, a second circuit layer is formed on the lower surface of the upper surface of the wafer, and the plurality of via holes are electrically connected to the first circuit layer and the second circuit layer. Finally, a plurality of solder balls are formed on the lower surface, and the plurality of solder balls are electrically connected to the second circuit layer.

In an embodiment of the present application, the foregoing package structure further includes a first line a road layer, a second circuit layer, a plurality of via holes, and a plurality of solder balls. The first circuit layer is disposed on an upper surface of the substrate, and the photosensitive portion is located on the upper surface and electrically connected to the first circuit layer. The second circuit layer is disposed on a lower surface of the opposite surface of the substrate. A plurality of via holes are disposed on the substrate and electrically connected to the first circuit layer and the second circuit layer. A plurality of solder balls are disposed on the lower surface and electrically connected to the second circuit layer.

Based on the above, the present application utilizes a patterning process to form a barrier structure having a stepped opening to reduce the thickness of the portion of the barrier structure closest to the photosensitive region, thereby reducing the barrier structure from being thick and thick and easily blocking after the patterning process. Residual structure or uneven removal. In addition, if the barrier structure still has a small amount of residue after the patterning process, the residue to be removed can be easily removed through its stepped opening. Therefore, the present application can effectively improve the process yield and improve the overall reliability of the package structure.

The above features and advantages of the present invention will become more apparent from the following description.

100‧‧‧Package structure

110‧‧‧ wafer

110a‧‧‧ cutting road

112‧‧‧First line layer

114, 214‧‧‧Substrate

118a‧‧‧through hole

118b‧‧‧Electroplating

120, 220‧‧‧Photosensitive Department

125, 225‧‧‧ wafer

130, 130'‧‧‧ barrier

132a, 134a, 136a, 138a‧‧‧ to be removed from the frame

140‧‧‧Block structure

142‧‧‧ first frame enclosure

144‧‧‧ Second frame enclosure

146‧‧‧ Third frame enclosure

148‧‧‧Fourth frame

160, 265‧‧‧ second circuit layer

170‧‧‧ solder mask

180, 280‧‧‧ substrate

190, 290‧‧‧ solder balls

230‧‧‧ first barrier

240‧‧‧First barrier structure

250‧‧‧second barrier

252‧‧‧Second opening area

260‧‧‧second barrier structure

A, A', B, C‧‧‧ patterned mask layer

A1, A2'‧‧‧ first opening

A1'‧‧‧Resistance Department

A2‧‧‧ second opening

S‧‧‧ stepped opening

1 is a block diagram showing a flow of a package structure manufacturing method according to an embodiment of the present application.

2A-2F are schematic views of a method of fabricating a package structure according to an embodiment of the present application.

3 is a cross-sectional view showing a method of fabricating a package structure according to another embodiment of the present application; intention.

4A-4E are schematic cross-sectional views showing a process of fabricating a package structure according to another embodiment of the present application.

The foregoing and other technical features, features, and advantages of the present invention will be apparent from the Detailed Description of the Detailed Description. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only directions referring to the additional schema. Therefore, the directional terms used are for illustrative purposes and are not intended to limit the application. Also, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.

1 is a block diagram showing a flow of a package structure manufacturing method according to an embodiment of the present application. 2A-2F are schematic views of a method of fabricating a package structure according to an embodiment of the present application. The manufacturing method of the package structure of this embodiment includes the following steps. Referring to FIG. 1 and FIG. 2A simultaneously, first, a wafer 110 as shown in FIG. 2A is provided, and the wafer 110 includes a plurality of wafers 125 arranged in an array (step S01). In the embodiment, the wafer 125 may be a CMOS Image Sensor (CIS). Of course, the present application does not limit the type of the wafer 125. In addition, the wafer 110 includes a plurality of dicing streets 110a that separate the individual wafers 125. It should be noted that, in order to keep the drawing clean, FIG. 2B to FIG. 2F only show the manufacturing flow chart of the section along line AA' in FIG. 2A, that is, the fabrication of one of the wafers 125 in the wafer 110. The flow details the method of manufacturing the package structure of the present application.

Please refer to FIG. 2B. Specifically, the wafer 125 includes a substrate 114 and a photosensitive portion 120. The photosensitive portion 120 is disposed on the substrate 114. The substrate 114 may include a first wiring layer 112 disposed on the substrate 114. On the upper surface, the photosensitive portion 120 can be disposed on the upper surface and electrically connected to the first wiring layer 112.

Next, a barrier layer 130 as shown in FIG. 2B is formed on the wafer 110 (step S02). Specifically, the barrier layer 130 may be integrally formed on the wafer 110 and cover the photosensitive portion 120 of each of the wafers 125 and the substrate 114. The barrier layer 130 of the present embodiment may have, for example, a property of exhibiting a cracked state after exposure ( Positive photosensitive material) or bondable properties (negative photosensitive material).

Referring to FIG. 2C and FIG. 2E, the barrier layer 130 is patterned to form the barrier structure 140 as shown in FIG. 2E (step S03). The aforementioned patterning process can be an exposure and development process. In detail, the patterning process of the embodiment may include the following steps. First, a patterned mask layer A is formed on the barrier layer 130 as shown in FIG. 2C, wherein the patterned mask layer A includes a plurality of patterns. The openings (only one patterned opening is illustrated in FIG. 2C), the plurality of wafers 125 as shown in FIG. 2A are respectively located in the orthographic projection range of the plurality of patterned openings on the wafer 110. In other words, the wafers 125 are each located within the vertical projection range of the patterned opening. Each patterned opening may include a first opening A1 and a plurality of second openings A2 that respectively expose the corresponding partial barrier layer 130 as shown in FIG. 2C. The photosensitive portion 120 of the wafer 125 is located within the orthographic projection range P1 of the first opening A1 on the substrate 114. The plurality of second openings A2 respectively surround the first opening A1, and the opening area of the second opening A2 gradually decreases toward the direction away from the first opening A1. Of course, this embodiment is for illustrative purposes only. The application does not limit the number of second openings as long as the opening area of the second opening A2 gradually decreases toward the direction away from the first opening A1.

Next, an exposure process is performed to illuminate the barrier layer 130 from the side of the patterned mask layer A away from the wafer 125 in the direction of the arrow in FIG. 2C. Since the present application designs the patterned mask layer A to have a plurality of openings of different sizes, after the light is irradiated onto the barrier layer 130, the first opening A1 and the plurality of the first plurality are caused by the resolution of the photosensitive material. The resolution of the partial barrier layer 130 corresponding to the two openings A2 is different, resulting in different depths after development.

Thereafter, a developing process may be performed to remove the partial barrier layer 130 exposed by the first opening A1 and the second opening A2 to form a stepped opening S as shown in FIG. 2E. In detail, the developing process is to form the above-described stepped opening S by using the barrier layer 130 on the developer removing wafer 125 which is in a cracked state due to exposure. Since the barrier layer 130 outside the stepped opening S is not exposed, the barrier layer 130 of this region is not soluble in the developer to form the barrier structure 140 as shown in FIG. 2E. In this embodiment, each of the blocking structures 140 can include at least a first frame surrounding portion 142, a second frame surrounding portion 144, and a stepped opening S. More specifically, the blocking structure 140 may sequentially include a first frame surrounding portion 142, a second frame surrounding portion 144, and a third frame from a side close to the substrate 114 to a side away from the substrate 114 as shown in FIG. 2C. a first frame surrounding portion 142 corresponding to the first opening A1 of the patterned mask layer A, and a second frame surrounding portion 144, a third frame surrounding portion 146, and a fourth frame surrounding portion 148 The four frame enclosures 148 respectively correspond to the plurality of second openings A2 whose opening areas gradually decrease toward the direction away from the first opening A1. The blocking structure 140 is integrally formed, and the first frame surround 142. The second frame surrounding portion 144, the third frame surrounding portion 146, and the fourth frame surrounding portion 148 can collectively surround the photosensitive portion 120 of the wafer 125 and collectively define a stepped opening S exposing the photosensitive portion 120. The shortest distance D1 of the first frame surrounding portion 142 to the photosensitive portion 120 may be less than 200 micrometers, and is also smaller than the shortest distance between the second frame surrounding portion 144 and the photosensitive portion 120. Similarly, the shortest distance between the second frame 144 and the photosensitive portion 120 is smaller than the shortest distance from the third frame 146 to the photosensitive portion 120, and the shortest distance from the third frame 146 to the photosensitive portion 120 is smaller than the fourth frame. The shortest distance from the portion 148 to the photosensitive portion 120.

Since the barrier structure usually needs to have a certain thickness to maintain its support and structural strength (the thickness of the current general barrier structure is about 45 microns). Therefore, the present embodiment utilizes the patterned mask layer A having a plurality of openings A1 and A2 of different sizes to pattern the barrier layer 130 to form a stepped opening S on the barrier layer 130 to define the barrier structure 140. Therefore, it is possible to reduce the possibility that the barrier structure 140 remains or is removed unevenly around the photosensitive portion 120 after the patterning process.

In addition, referring to FIG. 2D, if the barrier layer 130 still has a small amount of residue after the patterning process, there is still a frame to be removed 132a/134a/136a/138a to be removed among the stepped openings S. Alternatively, it is also possible to remove a portion of the barrier structure 140 located outside the stepped opening region S due to the need for fabrication, which can be easily removed by the following steps. For example, after the patterning process, there are respectively a first to-be-removed frame beside the first frame surrounding portion 142, the second frame surrounding portion 144, the third frame surrounding portion 146, and the fourth frame surrounding portion 148. The surrounding portion 132a, the second to-be-removed frame surrounding portion 134a, the third to-be-removed frame surrounding portion 136a, and the fourth to-be-removed frame surrounding portion 138a, since the barrier structure 140 is designed as a stepped structure, One to move The frame surrounding portion 132a can be easily moved from the first frame surrounding portion 142 to the second frame surrounding portion 144, moved to the third frame surrounding portion 146, and then moved to the fourth frame surrounding portion 148, and then The frame to be removed 132a is removed by development. However, the first to-be-removed frame enclosure 132a can also be removed by the development after being moved to the second frame enclosure 144 or the third frame enclosure 146. The present application does not use the first to-be-removed frame enclosure. The movement position of 132a is limited. In this way, the present application can effectively avoid the occurrence of residual or unrestricted barrier structure 140 around the photosensitive portion 120, thereby improving the process yield and shortening the spacing between the barrier structure 140 and the photosensitive portion 120. Similarly, in other embodiments, the second to-be-removed frame enclosure 134a, the third to-be-removed frame enclosure 136a, and the fourth to-be-removed frame enclosure 138a may also be removed in the same manner, and the present application is It is not limited to the order in which the frames to be removed are removed.

Thereafter, referring to FIG. 2F, the substrate 180 is disposed on the barrier structure 140 to cover the plurality of wafers 125 of the wafer 110 and the blocking structure 140 (step S04 of FIG. 1). In this embodiment, the photosensitive portion 120 may include an image sensing wafer, and the substrate 180 may be a transparent substrate. In this embodiment, the substrate 180 is a glass substrate. Of course, the embodiment is not limited thereto. More specifically, referring to FIG. 2F, the substrate 180 is overlying the barrier structure 140. It should be noted that, before this step, a material such as an encapsulant or a fluorescent material may be filled in the stepped opening region S as needed.

In addition, in this embodiment, a plurality of via holes 118a penetrating through the substrate 114 may be formed as shown in FIG. 2F. For example, the via hole 118a may be formed by mechanical drilling, and a plating layer 118b is formed on the inner wall of the via hole by electroplating to form a via hole. 118a. Then, a second circuit layer 160 is formed on the lower surface of the substrate 114 opposite to the upper surface thereof, and the via hole 118a is electrically connected to the first circuit layer 112 and the second circuit layer 160, and then the solder resist layer 170 is covered. A portion of the second wiring layer 160 is exposed on the second wiring layer 160. Finally, a plurality of solder balls 190 are formed on the lower surface of the substrate 114, and the solder balls 190 are electrically connected to the second circuit layer 160.

Finally, referring to step S05 of FIG. 1 and FIG. 2A, the wafer 110 is diced along the scribe line 110a, and the fabrication of the plurality of package structures 100 independent of each other is substantially completed.

3 is a cross-sectional view showing a method of fabricating a package structure according to another embodiment of the present application. It should be noted that the manufacturing method of the package structure of the present embodiment is similar to the manufacturing method of the package structure of the foregoing embodiment. Therefore, the present embodiment uses the component numbers and parts of the foregoing embodiments, wherein the same reference numerals are used. The same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, and the description is not repeated herein. The difference between the manufacturing method of the package structure of the present embodiment and the foregoing embodiment will be described below.

The difference between this embodiment and the foregoing embodiment is that the barrier layer 130 used in the foregoing embodiment is exemplified by a positive photoresist, and the barrier layer 130' used in this embodiment is a negative photoresist and is matched. The shape of the patterned mask layer A' of this embodiment may be opposite to that of the patterned mask layer A of the foregoing embodiment. Specifically, the patterned mask layer A' of the embodiment may be A plurality of reticle patterns are included that respectively cover the orthographic projection ranges of the plurality of wafers 125 on the barrier layer 130' as shown in FIG. 2A. Each of the reticle patterns may include a photoresist portion A1' and a plurality of first openings A2' as shown in FIG. 3, wherein the photoresist portion A1' covers an orthographic projection range of the wafer 120 on the barrier layer 130'. many The first openings A2' are respectively disposed around the photoresist portion A1', and the corresponding partial barrier layers 130 are exposed, and the opening areas of the plurality of first openings A2' are gradually increased in a direction away from the photoresist portion A1'.

Thereafter, the barrier layer 130 is subjected to an exposure and development process to remove a portion of the barrier layer 130 that is not exposed by the first opening A2' to form a stepped opening as shown in FIG. 2E. Therefore, in this embodiment, by forming the patterned photomask layer having the openings A2 of different sizes, the barrier layer 130 can be formed into a barrier structure having a similar step shape after the patterning process, thereby avoiding the conventional barrier layer 130. Thicker thicknesses result in uneven removal.

4A-4E are schematic cross-sectional views showing a method of fabricating a package structure according to another embodiment of the present application. The same or similar elements of the embodiment as those of the foregoing embodiments are denoted by the same or similar reference numerals, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, and the description is not repeated herein. This embodiment is different from the foregoing embodiment in that this embodiment uses a plurality of patterning processes to respectively form a plurality of barrier structures stacked in a stepped manner with each other. For example, this embodiment utilizes two patterning processes. And the first blocking structure 240 and the second blocking structure 260 which are stacked in a stepped manner with each other as shown in FIG. 4E are respectively formed. Of course, this application does not limit the number of blocking structures.

This embodiment is the same as the previous embodiment, and has a wafer including a plurality of arrays of wafers as shown in FIG. 2A. Finally, after the package structure is completed, a plurality of dicing lines are cut along the wafer. The manner of the package structure is the same as that of the foregoing embodiment, and details are not described herein again. The following will be for a single crystal in the wafer. The production process of the film is explained. In detail, referring to FIG. 4A and FIG. 4B , the wafer 225 in this embodiment also includes a substrate 214 and a photosensitive portion 220 , and the substrate 214 may further include a first wiring layer 212 . First, a first barrier structure 240 is formed. The first blocking structure 240 is formed by covering the first barrier layer 230 on the substrate 214, and then exposing the first barrier layer 230 by using the patterned mask layer B, and then in the first barrier layer 230. A first open area 232 is defined. This embodiment is exemplified by a positive photoresist, however, the present application is not limited thereto. Thereafter, the first barrier layer 230 is further subjected to a development process to remove the first barrier layer 230 in the first opening region 232 and expose the photosensitive portion 220 to form the first barrier structure 240. However, similar to the foregoing embodiment, there may also be a first to-be-removed blocking structure 230a to be removed among the first opening regions 232 at this time.

Referring to FIG. 4C and FIG. 4D, a second blocking structure 260 is formed. The second blocking structure 260 is formed in a manner similar to that of the first blocking structure 240, and thus is not described herein again. The opening structure of the patterned mask layer C of the two blocking structures 260 is larger than the opening structure of the patterned mask layer B to form the second blocking structure 260 stacked on the first blocking structure 240 in a stepped manner. This embodiment is exemplified by a positive photoresist, however, the present application is not limited thereto. Moreover, similar to the foregoing embodiment, there may also be a second to-be-removed blocking structure 250a to be removed among the second opening regions 252 of the second blocking structure 260.

In the embodiment, the first blocking structure 240 and the second blocking structure 260 can jointly define a stepped opening area exposing the photosensitive portion 220, and wherein the shortest distance between the first blocking structure 240 and the photosensitive portion 220 is smaller than the second blocking structure. 260 to the sense The shortest distance of the light portion 220 is such that the first barrier structure 240 and the second barrier structure 260 together form a structure similar to a step. Next, referring to FIG. 4E, the first to-be-removed blocking structure 230a and the second to-be-removed blocking structure 250a are removed by the method similar to the foregoing embodiment, and the substrate 280 is disposed on the second blocking structure. Above the 260, the second wiring layer 265 and the solder balls 290 are sequentially formed on the lower surface of the substrate 214. The present application is not limited to the order in which the blocking structures 230a and 250a are to be removed, and is not limited to the order in which the substrate 280 and the second wiring layer 265 are disposed. In addition, before the substrate 280 is disposed on the second barrier structure 260, the first opening region 232 and the second opening region 252 may be filled with an encapsulant or a fluorescent material as needed in the foregoing embodiment. And other materials. It should be noted that this embodiment is exemplified by a two-layer barrier structure, and each of the barrier structures has a thickness of about 22 micrometers. However, it may have more layers of barrier structures and different thicknesses. Not limited to this. With such a configuration, the thickness of each of the barrier structures can be reduced by the design of the multilayer barrier structure, and the problem of uneven removal due to the thickness of the barrier structure is not easy to be removed when the excess barrier structure is removed. .

In summary, the present application can form a barrier structure having a stepped opening by forming a patterned photomask layer having openings of different sizes to reduce the thickness of the portion of the barrier structure closest to the wafer. In addition, the barrier structure may be reduced in thickness due to thick thickness, and the barrier structure may remain or be removed unevenly after the patterning process. In addition, if the barrier structure still has a small amount of residue after the patterning process, the residue to be removed can be easily cleared through the stepped opening. except. Therefore, the present application can effectively improve the process yield and improve the overall reliability of the package structure.

Although the present application has been disclosed in the above embodiments, it is not intended to limit the present application, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present application. The scope of protection of this application is subject to the definition of the scope of the appended claims.

100‧‧‧Package structure

112‧‧‧First line layer

114‧‧‧Substrate

118a‧‧‧through hole

118b‧‧‧Electroplating

120‧‧‧Photosensitive Department

125‧‧‧ wafer

140‧‧‧Block structure

160‧‧‧Second circuit layer

170‧‧‧ solder mask

180‧‧‧Substrate

190‧‧‧ solder balls

S‧‧‧ stepped opening

Claims (20)

A package structure manufacturing method comprising: providing a wafer comprising a plurality of arrays of wafers; forming a barrier layer on the wafer and the barrier layer covering the wafers; performing a patterning process on the barrier layer to Forming a barrier structure, wherein the barrier structure includes a plurality of first frame portions, a plurality of second frame portions, and a plurality of stepped openings, each of the first frame portions protruding from the corresponding second frame portion to Corresponding second frame enclosures collectively define the stepped openings, the stepped openings respectively exposing the wafers; and a substrate disposed on the barrier structure to cover the wafers, the first frame enclosures and The second frame enclosing portion, wherein a bottom surface of the substrate covers a top surface of the blocking structure. The package structure manufacturing method of claim 1, wherein the wafer further comprises a plurality of dicing streets disposed between the wafers to separate the wafers. The method for manufacturing a package structure according to claim 2, further comprising: cutting the wafer along the scribe lines after the substrate is disposed on the barrier structure to form a plurality of package structures independent of each other. The method of fabricating a package structure according to claim 1, wherein the step of patterning further comprises: forming a patterned mask layer on the barrier layer, wherein the patterned mask layer comprises a plurality of patterns Opening, the wafers are respectively located on the patterned openings in the wafer Each of the patterned openings includes a first opening and a plurality of second openings respectively surrounding the first opening to respectively expose a corresponding portion of the barrier layer, and the plurality of Opening area of the two openings gradually decreases away from the first opening; and performing an exposure and development process on the barrier layer to remove portions of the barrier layer exposed by the patterned openings to form the stepped shapes Opening. The method of fabricating a package structure according to claim 1, wherein the step of patterning further comprises: forming a patterned mask layer on the barrier layer, wherein the patterned mask layer comprises a plurality of masks a pattern covering the orthographic projection ranges of the wafers on the barrier layer, each of the reticle patterns including a photoresist portion and a plurality of first openings respectively disposed around the photoresist portion and exposing corresponding portions a portion of the barrier layer, and an opening area of the first opening gradually increases away from the photoresist portion; and performing an exposure and development process on the barrier layer to remove the mask patterns from the portions A portion of the barrier layer exposed by the first opening forms the stepped openings. The package structure manufacturing method of claim 1, wherein a shortest distance from each of the first frame to the corresponding wafer is less than 200 micrometers. The package structure manufacturing method of claim 1, wherein a shortest distance from each of the first frame portions to the corresponding wafer is smaller than a shortest distance from the corresponding second frame portion to the corresponding wafer. The method of manufacturing a package structure according to claim 1, wherein the barrier structure is integrally formed. The method of manufacturing a package structure according to claim 1, wherein the substrate is a transparent substrate. The method of manufacturing a package structure according to claim 1, wherein the wafers are image sensing wafers. The method for manufacturing a package structure according to claim 1, further comprising: forming a first circuit layer on an upper surface of the wafer, the wafers being electrically connected to the first circuit layer. The method for manufacturing a package structure according to claim 11, further comprising: forming a plurality of via holes in the wafer; forming a second circuit layer on a lower surface of the wafer opposite the upper surface, and the conducting The hole is electrically connected to the first circuit layer and the second circuit layer; and a plurality of solder balls are formed on the lower surface, and the solder balls are electrically connected to the second circuit layer. The method for manufacturing a package structure according to claim 1, wherein each of the wafers comprises a substrate and a photosensitive portion, the photosensitive portion is located on the substrate, and the stepped openings respectively expose the photosensitive regions of the wafers . A package structure comprising: a wafer comprising a substrate and a photosensitive portion, the photosensitive portion is located on the substrate; a blocking structure disposed on the wafer and comprising a first frame surrounding portion and a second frame surrounding portion And a stepped opening, the first frame surrounding portion and the second frame surrounding portion being framed together Forming the stepped opening around the photosensitive portion, the stepped opening exposing the photosensitive portion, and the first frame surrounding portion is located on the substrate and protruding from the second frame surrounding portion; and a substrate disposed on the substrate Blocking the structure and covering the wafer, the first frame surrounding portion and the second frame surrounding portion, wherein a bottom surface of the substrate covers a top surface of the blocking structure. The package structure of claim 14, wherein a shortest distance from the first frame to the photosensitive portion is less than 200 microns. The package structure of claim 14, wherein a shortest distance from the first frame to the photosensitive portion is less than a shortest distance from the second frame to the wafer. The package structure of claim 14, wherein the barrier structure is integrally formed. The package structure of claim 14, wherein the substrate is a transparent substrate. The package structure of claim 18, wherein the wafer is an image sensing wafer. The package structure of claim 14, further comprising: a first circuit layer disposed on an upper surface of the substrate, the photosensitive portion being located on the upper surface and electrically connected to the first circuit layer; a second circuit layer disposed on a lower surface of the substrate opposite to the upper surface; a plurality of via holes disposed on the substrate and electrically connected to the first circuit layer and the second circuit layer; and a plurality of solder balls, The lower surface is electrically connected to the second circuit layer.