TWI559461B - Apparatus and method for embedding components in small-form-factor, system-on-packages - Google Patents

Apparatus and method for embedding components in small-form-factor, system-on-packages Download PDF

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TWI559461B
TWI559461B TW104120155A TW104120155A TWI559461B TW I559461 B TWI559461 B TW I559461B TW 104120155 A TW104120155 A TW 104120155A TW 104120155 A TW104120155 A TW 104120155A TW I559461 B TWI559461 B TW I559461B
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layer
electronic components
stacked
conformal
stacked layer
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TW201618239A (en
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戴巴貝尼 裘德豪伊
普拉薩德 阿魯里
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英特爾公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Description

用以嵌入組件於小形狀因數、系統整合封裝之設備與方法 Apparatus and method for embedding components in small form factor, system integrated package 發明領域 Field of invention

本發明大致上係有關於積體電路設計,及更明確言之,係有關於具有在一小形狀因數(SFF)-系統整合封裝(SOP)環境內部之改良效能、整合熱管理及干擾緩和中之一或多者的該SFF-SOP架構。 The present invention relates generally to integrated circuit design and, more specifically, to improved performance, integrated thermal management, and interference mitigation within a small form factor (SFF)-system integrated package (SOP) environment. One or more of the SFF-SOP architecture.

發明背景 Background of the invention

行動平台的尺寸益發縮小且結合更多電子無線功能用於有效通訊。為了將全部期望的電子功能皆含括入未來小形狀因數(SFF)行動平台內部,正在發展嵌入式系統整合封裝(SOP)架構。 The size of the mobile platform is reduced and combined with more electronic wireless capabilities for efficient communication. In order to incorporate all of the desired electronic functions into the future Small Form Factor (SFF) mobile platform, an Embedded System Integrated Package (SOP) architecture is being developed.

目前不同的主動組件以及被動組件嵌入技術正在利用多層基體材料及空腔發展。正在利用低成本材料發展裝置嵌入技術,該等低成本材料用於嵌入射頻(RF)功能並不佳。正在發展嵌入「整合被動裝置」之某些辦法,但可能提高製造成本與組裝成本,其可能使得運用低成本材料系統的用途變最小化。再者,針對多重標準無線系統仍然難以達成RF效能及尺寸縮小。射頻-整合被動裝置 (RF-IPD)也運用在矽、低溫共燒製陶瓷(LTCC)、玻璃或其它材料且嵌入低成本材料系統內用於RF連結。如此潛在地顯著提高了組裝成本及製造成本,且在其它組件於緊密鄰近嵌入或屏蔽之後,降級/改變了複雜的被動結構之效能。 Different active components and passive component embedding technologies are currently being developed using multilayer matrix materials and cavities. Device embedding technologies are being developed using low cost materials that are not well suited for embedding radio frequency (RF) functionality. Some approaches to embedding "integrated passive devices" are being developed, but may increase manufacturing and assembly costs, which may minimize the use of low cost material systems. Furthermore, it is still difficult to achieve RF performance and size reduction for multi-standard wireless systems. RF-integrated passive device (RF-IPD) is also used in 矽, low temperature co-fired ceramics (LTCC), glass or other materials and embedded in low cost material systems for RF bonding. This potentially significantly increases assembly and manufacturing costs, and degrades/changes the performance of complex passive structures after other components are embedded or shielded in close proximity.

另一方面,正在利用已知比較數位-基體材料具有更高成本的高效能材料。於多層材料環境中,此等材料可嵌入複雜的RF被動設計。目前SOP結構中的熱問題及雜訊管理問題尚未解決。在該SFF-SOP環境中用於雜訊緩和的習知電磁帶隙(EBG)結構將傾向於耗用大量空間,而將增加總體SOP的大小。此二辦法也有串擾熱問題。 On the other hand, high-performance materials with known higher-cost matrix materials are being utilized at higher cost. In a multi-layer material environment, these materials can be embedded in complex RF passive designs. The thermal issues and noise management issues in the current SOP structure have not been resolved. Conventional electromagnetic bandgap (EBG) structures for noise mitigation in this SFF-SOP environment will tend to consume a lot of space and will increase the overall SOP size. These two methods also have crosstalk heat problems.

依據本發明之一實施例,係特地提出一種裝置,其包含:一實體通訊模組經組配以至少接收及處理無線射頻(RF)信號,該實體通訊模組包含:配置成一堆疊層體之一小形狀因數平台包含:具有一第一適型材料之該堆疊層體中之一第一層;具有一第二適型材料之該堆疊層體中之一第二層;具有一第三材料之該堆疊層體中之一第三層,其中該第一適型材料及該第二適型材料係比該第三材料更具有可撓性;及一或多個電子組件嵌入該堆疊層體內部,其中該等一或多個電子組件係經組配以,在一接收的無線信號之一頻率在該裝置被轉換成一較低頻之前,處理該無線信號。 According to an embodiment of the present invention, an apparatus is specifically provided, comprising: a physical communication module configured to receive and process at least a radio frequency (RF) signal, the physical communication module comprising: configured as a stacked layer a small form factor platform comprising: a first layer of the stacked layer having a first conformal material; a second layer of the stacked layer having a second conforming material; having a third material a third layer of the stacked layer, wherein the first conformal material and the second conformal material are more flexible than the third material; and one or more electronic components are embedded in the stacked layer And wherein the one or more electronic components are configured to process the wireless signal at a frequency of a received wireless signal before the device is converted to a lower frequency.

100‧‧‧非同質堆疊體 100‧‧‧Non-homogeneous stack

105‧‧‧高效能材料 105‧‧‧High-performance materials

110‧‧‧低效能材料 110‧‧‧Inefficient materials

115‧‧‧主動IC組件 115‧‧‧Active IC components

120‧‧‧功率放大器(PA)、GaAs PA 120‧‧‧Power Amplifier (PA), GaAs PA

125‧‧‧RFIC及BB/MAC IC 125‧‧‧RFIC and BB/MAC IC

130、320‧‧‧被動組件 130, 320‧‧‧ Passive components

135‧‧‧天線 135‧‧‧Antenna

140‧‧‧金屬線 140‧‧‧Metal wire

150‧‧‧散熱器材料 150‧‧‧ radiator material

205‧‧‧模塑層 205‧‧‧Molding layer

305‧‧‧IC1 305‧‧‧IC1

310‧‧‧IC2 310‧‧‧IC2

315‧‧‧IC3 315‧‧‧IC3

325、335‧‧‧隔離結構 325, 335‧‧ ‧ isolation structure

330‧‧‧微通孔結構 330‧‧‧Microvia structure

圖1顯示依據本發明之各個實施例具有高效能及 低效能聚合物層兩者以形成一材料堆疊體之SOP之剖面圖。 1 shows high performance and performance in accordance with various embodiments of the present invention Both of the low performance polymer layers are formed into a cross-sectional view of the SOP of a stack of materials.

圖2顯示依據本發明之各個實施例具有高效能及低效能聚合物層兩者以形成一材料堆疊體之SOP之另一幅剖面圖。 2 shows another cross-sectional view of an SOP having both high performance and low performance polymer layers to form a stack of materials in accordance with various embodiments of the present invention.

圖3a顯示SOP之剖面圖,其包括依據本文揭示之各種面向的嵌入式隔離結構。 Figure 3a shows a cross-sectional view of the SOP including embedded isolation structures in accordance with the various aspects disclosed herein.

圖3b顯示沿圖3a之線A及線B所取的垂直週期性微通孔結構A及B。 Figure 3b shows vertical periodic microvia structures A and B taken along line A and line B of Figure 3a.

圖3c顯示沿圖3a之線C所取的水平週期性結構。 Figure 3c shows the horizontal periodic structure taken along line C of Figure 3a.

圖4顯示依據本文揭示之各種面向的包括具有一SOP堆疊體之一通訊模組的一裝置之具體實施例。 4 shows a specific embodiment of a device including a communication module having a SOP stack in accordance with various aspects disclosed herein.

較佳實施例之詳細說明 Detailed description of the preferred embodiment

定義 definition

高效能材料:高效能材料為相較於低效能材料之性質,提供優異電氣性質包括低損耗及低熱膨脹係數(CTE)的一種材料。 High-performance materials: High-performance materials are materials that provide superior electrical properties, including low loss and low coefficient of thermal expansion (CTE), compared to the properties of low-efficiency materials.

依據本文揭示之各種面向,揭示一種設備其包括含一系統整合封裝架構之一小形狀因數行動平台,該系統整合封裝架構配置為一堆疊層體包括:具有一第一適型材料之一第一層;具有一第二適型材料或任何其它剛性有機材料之一第二層;具有一第三材料之一第三層;及嵌入該堆疊層體內部的一或多個電子組件,其中該第一適型材 料、該第二適型材料、或二者係經組配以許可高頻信號路徑安排。 In accordance with various aspects disclosed herein, a device is disclosed that includes a small form factor mobile platform including a system integrated package architecture, the system integrated package architecture configured as a stacked layer body including: a first conformal material first a second layer having a second conformal material or any other rigid organic material; a third layer having a third material; and one or more electronic components embedded within the stacked layer, wherein the first One profile The material, the second conformable material, or both are assembled to permit high frequency signal path arrangements.

依據本文揭示之各種面向,該設備可進一步包括一散熱元件經組配以耗散自該等一或多個電子組件產生的熱,其中該散熱元件係配置於該第一層與該第二層間。該散熱元件可包括高傳導係數材料,諸如金屬、或方向性導體。該高傳導係數材料可選自於由下列所組成之該組群:銅、鋁、柯法(KOVAR)此乃一種散熱器材料、黃銅、碳化矽或其它材料諸如金或銀,及方向性導體可包括石墨,其係經組配以沿二維平面散熱。再者,該設備可包括後述特性件,其中該第一適型材料及該第二適型材料為相同材料或為不同材料。又,該設備可包括後述特性件,其中該第一適型材料、該第二適型材料、或兩者包括聚合物,諸如液晶聚合物或可為剛性有機物或聚合物料。 In accordance with various aspects disclosed herein, the apparatus can further include a heat dissipating component configured to dissipate heat generated by the one or more electronic components, wherein the heat dissipating component is disposed between the first layer and the second layer . The heat dissipating component can comprise a high conductivity material such as a metal, or a directional conductor. The high conductivity material may be selected from the group consisting of: copper, aluminum, KOVAR, a heat sink material, brass, tantalum carbide or other materials such as gold or silver, and directionality. The conductors can include graphite that is assembled to dissipate heat along a two-dimensional plane. Furthermore, the device may include a characteristic member described later, wherein the first conformal material and the second conformable material are the same material or different materials. Also, the apparatus may include a characteristic member described later, wherein the first conformable material, the second conformable material, or both comprise a polymer such as a liquid crystal polymer or may be a rigid organic or polymeric material.

依據本文揭示之各種面向,該設備可進一步包括配置在該等一或多個電子組件間之一垂直過濾結構。該垂直過濾結構可包括堆疊通孔圖樣,排列成垂直過濾結構的週期性排列,其可界定濾波特性。該設備可包括後述特性件,其中該垂直過濾結構係經組配以過濾或隔離由該等一或多個電子組件產生的射頻雜訊、數位雜訊之諧波、或二者。該設備可包括後述特性件,其中該第三材料係與該第一及第二適型材料不同。 In accordance with various aspects disclosed herein, the apparatus can further include a vertical filtering structure disposed between the one or more electronic components. The vertical filtering structure can include stacked via patterns arranged in a periodic arrangement of vertical filtering structures that can define filtering characteristics. The apparatus can include features as described below, wherein the vertical filtering structure is configured to filter or isolate radio frequency noise, harmonics of digital noise, or both generated by the one or more electronic components. The apparatus may include a characteristic member described later, wherein the third material is different from the first and second conformal materials.

依據本文揭示之各種面向,揭示一種方法其包括形成含一系統整合封裝架構之一小形狀因數行動平台,該 系統整合封裝架構配置為一堆疊層體包括:提供具有一第一適型材料之一第一層;提供具有一第二適型材料或任何其它剛性有機材料之一第二層;提供具有一第三材料之一第三層;及嵌入一或多個電子組件於該堆疊層體內部,其中該第一適型材料、該第二適型材料、或二者係經組配以許可高頻信號路徑安排。 In accordance with various aspects disclosed herein, a method is disclosed that includes forming a small form factor mobile platform including a system integrated package architecture, Configuring the system integrated package structure as a stacked layer includes: providing a first layer having a first conformal material; providing a second layer having a second conformal material or any other rigid organic material; providing a first a third layer of three materials; and embedding one or more electronic components within the stacked layer, wherein the first conformable material, the second conformable material, or both are assembled to permit high frequency signals Path arrangement.

依據本文揭示之各種面向,該方法可包括配置一散熱元件於該第一與該第二適型材料間,其中該散熱元件可配置於該第一層與該第二層間。該第一適型材料及該第二適型材料可為相同材料或不同材料。舉例言之,該第一或第二適型材料或兩者可包括聚合物諸如液晶聚合物,或可為剛性有機材料或聚合物料。該散熱元件可包括高傳導係數材料,諸如金屬、或方向性導體,其中該高傳導係數材料可選自於由銅及鋁所組成之該組群,及方向性導體可包括石墨,其係經組配以沿二維平面散熱。 In accordance with various aspects disclosed herein, the method can include disposing a heat dissipating component between the first and second conformal materials, wherein the heat dissipating component can be disposed between the first layer and the second layer. The first conformable material and the second conformable material may be the same material or different materials. For example, the first or second conformable material or both may comprise a polymer such as a liquid crystal polymer, or may be a rigid organic material or a polymeric material. The heat dissipating component may comprise a high conductivity material, such as a metal, or a directional conductor, wherein the high conductivity material may be selected from the group consisting of copper and aluminum, and the directional conductor may comprise graphite, which is It is assembled to dissipate heat along a two-dimensional plane.

依據本文揭示之各種面向,該方法可包括配置一垂直過濾結構於該等一或多個電子組件間,其中該垂直週期性過濾結構包括堆疊的通孔圖樣。該垂直過濾結構之配置可為週期性,及界定過濾特性,其中該垂直過濾結構係經組配以過濾或隔離由該等一或多個電子組件產生的射頻雜訊、數位雜訊之諧波、或二者。如由關注的小形狀因數SOP許可,垂直過濾可組合水平週期性過濾。 In accordance with various aspects disclosed herein, the method can include configuring a vertical filter structure between the one or more electronic components, wherein the vertical periodic filter structure comprises a stacked via pattern. The vertical filter structure can be configured to be periodic and define a filter characteristic, wherein the vertical filter structure is configured to filter or isolate harmonics of radio frequency noise and digital noise generated by the one or more electronic components. Or both. Vertical filtering can combine horizontal periodic filtering as permitted by the small form factor SOP of interest.

本發明之此等及其它目的、特徵及特性,以及相關結構元件之操作方法及功能,及製造部件與製造經濟學 之組合當參考附圖考慮後文詳細說明部分及隨附之申請專利範圍時將更為彰顯,全部皆構成本文說明書之一部分,附圖中相似的元件符號標示各幅圖中相對應的部件。但須明確地瞭解附圖僅係用於例示及描述目的,而非意圖限制本發明。如本說明書中及申請專利範圍各項中使用,除非另行載明否則「一(a)」、「一(an)」及「該」之單數形包括複數形。 These and other objects, features and characteristics of the present invention, as well as methods and functions of the related structural elements, and manufacturing parts and manufacturing economics Combinations of the present invention will become more apparent when referring to the appended claims. It is to be understood that the drawings are only for the purpose of illustration and description The singular forms "a", "an" and "the" are used in the singular.

圖1顯示依據本文揭示之各個面向的具有高效能及低效能聚合物層兩者以形成一材料堆疊體之SOP之剖面圖。大致顯示於100的非同質堆疊體包括一或多層之高效能材料105,及一或多層之低效能材料110。舉個非限制性實例,高效能材料105可為聚合物,諸如液晶聚合物(LCP)、羅傑士(Rogers)RXP,或於寬廣頻率範圍比較低效能材料110之電氣性質具有優異電氣性質之任何其它材料。低損耗正切為用於高效能材料105之一因數,且係與電路信號損耗及品質或Q因數直接相關。由於此等特性故,高效能材料諸如LCP許可高頻信號路徑安排及被動元件。低效能材料110可包括聚合物,諸如味之素堆積膜(ABF)、FR4、BT或任何其它有機材料。 1 shows a cross-sectional view of an SOP having both high performance and low performance polymer layers to form a stack of materials in accordance with the various aspects disclosed herein. The non-homogeneous stack, generally shown at 100, includes one or more layers of high performance material 105, and one or more layers of low performance material 110. By way of non-limiting example, the high performance material 105 can be a polymer, such as a liquid crystal polymer (LCP), Rogers RXP, or have superior electrical properties over the electrical properties of the low performance material 110 over a wide frequency range. Any other material. The low loss tangent is a factor for the high performance material 105 and is directly related to circuit signal loss and quality or Q factor. Due to these characteristics, high performance materials such as LCP permit high frequency signal routing and passive components. The low performance material 110 can comprise a polymer such as Ajinomoto deposited film (ABF), FR4, BT or any other organic material.

高效能材料105諸如LCP可比低效能材料110更具可撓性或可彎性。高效能材料105之此種可撓性讓此等層環繞電氣組件隨形,使得電氣組件可嵌入兩層高效能材料間。於有些面向中,堆疊體之一特定層可包括高效能材料105及低效能材料110兩者。於此種情況下,電氣組件及/或 RF組件可配置於兩層高效能材料間且相鄰於SOP之一特定層上的低效能材料。 The high performance material 105, such as an LCP, can be more flexible or bendable than the low performance material 110. This flexibility of the high performance material 105 allows the layers to conform to the electrical components such that the electrical components can be embedded between the two layers of high performance materials. In some aspects, a particular layer of the stack can include both the high performance material 105 and the low performance material 110. In this case, electrical components and / or The RF component can be configured between two layers of high performance materials and adjacent to a low performance material on a particular layer of the SOP.

舉個非限制性實例,如圖1中顯示之堆疊體的厚度可小於0.5毫米。SOP的縱維度可藉基體減薄而予縮小。於此種情況下,若有所需,嵌入式IC設計可經優化以包括薄基體及聚合物材料環境的效果。 By way of non-limiting example, the thickness of the stack as shown in Figure 1 can be less than 0.5 mm. The vertical dimension of the SOP can be reduced by thinning the substrate. In this case, the embedded IC design can be optimized to include the effects of a thin substrate and polymer material environment, if desired.

於有些面向中,堆疊體可以是只包括一個類型之層的非同質堆疊體。舉例言之,堆疊體可包括高效能材料層或低效能材料層。 In some aspects, the stack can be a non-homogeneous stack that includes only one type of layer. For example, the stack can include a layer of high performance material or a layer of low performance material.

堆疊體可包括不同主動IC組件115,包括不同電氣組件及/或射頻(RF)組件,其可配置於兩層高效能材料105間。舉個非限制性實例,不同的電氣IC可包括功率放大器(PA)120,諸如GaAs PA。再者,不同的射頻IC可包括兩個高度整合IC之一組合晶片組,諸如RFIC及BB/MAC IC 125,其可遵照ICCC 802.11n及IEEE 802.11a/b/g標準操作。也可使用依從不同的無線標準操作的其它晶片組。此等IC並非限於用在無線應用的IC,反而可包括諸如記憶體、通用處理器、或特定應用IC及單晶片系統(SOC)等IC。堆疊體也可含有一或多個被動組件130,其可為消耗能量(但不產生能量)的射頻(RF)組件,或為無法有功率增益的組件。RF被動組件之例子可包括電容器、電感器、電阻器、變壓器、高阻礙多頻帶RF濾波器、多工器及平衡轉換器。其它被動組件諸如天線135可嵌入多層金屬層間以達成更高RF效能。來自矽整合單晶片諸如RFIC 125之RF信號可使用高效 能材料105之層路徑安排,而數位信號可使用低效能材料110之層通過金屬線140路徑安排。 The stack may include different active IC components 115, including different electrical components and/or radio frequency (RF) components, which may be disposed between two layers of high performance material 105. By way of non-limiting example, different electrical ICs may include a power amplifier (PA) 120, such as GaAs PA. Furthermore, different RF ICs may include one of two highly integrated ICs, such as RFIC and BB/MAC IC 125, which operate in accordance with ICCC 802.11n and IEEE 802.11a/b/g standards. Other chipsets that operate in accordance with different wireless standards can also be used. Such ICs are not limited to ICs used in wireless applications, but may include ICs such as memory, general purpose processors, or application specific ICs and single chip systems (SOCs). The stack may also contain one or more passive components 130, which may be radio frequency (RF) components that consume energy (but do not generate energy), or components that do not have power gain. Examples of RF passive components may include capacitors, inductors, resistors, transformers, high-impedance multi-band RF filters, multiplexers, and baluns. Other passive components such as antenna 135 can be embedded between multiple layers of metal to achieve higher RF performance. RF signals from 矽 integrated single-chips such as RFIC 125 can be used efficiently The layer routing of the material 105 can be arranged, and the digital signal can be routed through the metal line 140 using layers of the low performance material 110.

於本文揭示之各種面向中,高效能液晶聚合物(LCP)材料之成捲版本可用於嵌入RF主動組件,且使用LCP多金屬基體層狀結構發展嵌入式RF被動組件。LCP之成捲版本典型地係比原先的LCP材料價廉。如此藉由設計優化於環繞嵌入式主動組件於LCP類型層內的高效能被動組件,使用SOP形狀因數(全部x、y、z方向)最小化。LCP類型材料將使得基體材料隨形環繞嵌入式主動組件,且減少環繞嵌入式主動組件的任何表面保護之需要。LCP類型材料之薄層(厚度25微米)可用作為重新分配層,用於有效RF、類比、及數位信號分配以達成小形狀因數。較低成本ABF類型材料可用在堆疊體以嵌入額外數位功能。 In various aspects of the present disclosure, a roll-up version of a high performance liquid crystal polymer (LCP) material can be used to embed an RF active component and develop an embedded RF passive component using an LCP multi-metal matrix layered structure. The roll-up version of the LCP is typically less expensive than the original LCP material. The SOP form factor (all x, y, z directions) is minimized by designing a high performance passive component that is optimized to surround the embedded active component within the LCP type layer. The LCP type material will allow the base material to wrap around the embedded active component and reduce the need for any surface protection around the embedded active component. Thin layer of LCP type material (thickness 25 micron) can be used as a redistribution layer for efficient RF, analog, and digital signal distribution to achieve a small form factor. Lower cost ABF type materials can be used in the stack to embed additional digital functions.

於本文揭示之有些面向中,若總體SOP堆疊體的至少一維小於或等於約0.5毫米,則多層的一SOP堆疊體(例如,如圖1顯示)可視為具有「小形狀因數」。於本文揭示之有些面向中,若高效能材料層及/或低效能材料層各自之厚度係小於或等於約25微米,則多層的一SOP堆疊體(例如,如圖1顯示)可視為具有「小形狀因數」。但前述堆疊體維度及層維度並不限制建立被視為「小」形狀因數。於若干實施例中,SOP堆疊體的「小」可以SOP堆疊體在其中體現的裝置(或裝置類別)定義。舉例言之,有關桌上型電腦或膝上型電腦,若可體現在「小筆電」電腦內部,則SOP堆疊體可視為具有小形狀因數。同理,用於行動裝置,若可體現 在小區式電話或穿戴式裝置(例如,眼鏡、腕錶等)內部,則SOP堆疊體可視為具有小形狀因數。 In some aspects disclosed herein, if at least one dimension of the overall SOP stack is less than or equal to about 0.5 mm, then a multi-layered SOP stack (e.g., as shown in Figure 1) can be considered to have a "small form factor." In some aspects disclosed herein, if the thickness of each of the high performance material layer and/or the low performance material layer is less than or equal to about 25 microns, then a multilayer SOP stack (eg, as shown in FIG. 1) can be considered as having " Small form factor." However, the aforementioned stack dimensions and layer dimensions do not limit the establishment to be considered a "small" form factor. In several embodiments, the "small" of the SOP stack can be defined by the device (or device class) in which the SOP stack is embodied. For example, if the desktop or laptop computer is embodied inside a "small laptop" computer, the SOP stack can be considered to have a small form factor. For the same reason, for mobile devices, if it can be embodied Within a cell phone or wearable device (eg, glasses, wristwatch, etc.), the SOP stack can be considered to have a small form factor.

於本文揭示之有些面向中,於(SOP的)堆疊體100中之高效能材料105層及/或低效能材料110層可具有足夠可撓性,使得該等層於一或多維(例如,於x、y、z維中之一或多者)為全然可摺疊或部分可摺疊,不因摺疊而破碎或斷裂。於此等實施例中,排列在SOP堆疊體之層間的主動組件及/或被動組件(例如,組件115、130等)可以該等層本身的相似方式組配成摺疊配置。於摺疊配置排列於內部的多層及配置於層間之組件之操作功能可保持與非摺疊配置(例如,如圖1中顯示)相同。具有摺疊層及摺疊組件組態之一實施例可用在電子裝置諸如行動裝置(智慧型電話、平板電腦等)內部,其本身可經組配成具有不同尺寸或形狀因數。舉例言之,此種電子裝置可具有作為平板電腦(螢幕尺寸約8-10吋)的第一形狀因數,且可經組配有可撓性/可摺疊螢幕及外體,使得裝置可被重新組配成作為智慧型電話(螢幕尺寸約4吋或6吋)的第二形狀因數。於本舉例說明之電子裝置內部,SOP堆疊體可經配置成於第一「平板」形狀因數中,該等多層及配置於層間之組件係於非摺疊組態(例如,如圖1中顯示),於第二「智慧型電話」形狀因數中,該等多層及配置於層間之組件係於摺疊組態以因應及在裝置之較小形狀因數內部為可操作(具有相同功能)。 In some of the aspects disclosed herein, the layer of high performance material 105 and/or the layer of low performance material 110 in the (SOP) stack 100 may be sufficiently flexible such that the layers are in one or more dimensions (eg, One or more of the x, y, and z dimensions are fully foldable or partially foldable and do not break or break due to folding. In such embodiments, the active components and/or passive components (e.g., components 115, 130, etc.) arranged between the layers of the SOP stack may be assembled into a folded configuration in a similar manner to the layers themselves. The operational functions of the multi-layered and inter-layered components arranged in the folded configuration may remain the same as the unfolded configuration (eg, as shown in FIG. 1). One embodiment having a folded layer and folding assembly configuration can be used within an electronic device such as a mobile device (smart phone, tablet, etc.), which itself can be assembled to have different sizes or form factors. For example, such an electronic device can have a first form factor as a tablet (a screen size of about 8-10 inches) and can be assembled with a flexible/foldable screen and an outer body so that the device can be re The second form factor is assembled as a smart phone (screen size about 4 or 6 inches). Within the electronic device illustrated herein, the SOP stack can be configured in a first "flat" form factor that is tied to the unfolded configuration (eg, as shown in FIG. 1). In the second "smart phone" form factor, the multiple layers and the components disposed between the layers are in a folded configuration to be operable (with the same function) within and corresponding to the smaller form factor of the device.

於本文揭示之有些面向中,SOP堆疊體(例如,如圖1中顯示)可體現於無線電接收器及/或其它發射器IC的 RF前端內部(或通訊模組),如圖4中顯示。舉例言之,SOP堆疊體可嵌入無線裝置之(多-)無線電接收器的RF前端內部或通訊模組,諸如平板電腦、穿戴式計算裝置、小區式電話(基於眾所周知之小區式技術,諸如CDMA、EDGE、UMTS、OFDM、LTE等)、Wi-Fi接收器(基於眾所周知之各種IEEE 802.11標準)等。一般而言,於無線電接收器電路/模組中,射頻前端可包括天線與第一中頻(IF)階段間之電路。射頻前端可包括接收器中之組件,在信號被轉換成較低中頻之前,該組件於原先輸入射頻處理信號。舉例言之,射頻前端可包括阻抗匹配電路、帶通濾波器(BPF)、RF濾波器、RF放大器、本機振盪器(LO)、混合器、及/或其它組件。又,在無線裝置諸如平板電腦、穿戴式計算裝置、小區式電話、Wi-Fi接收器等內部體現的無線電接收器中,射頻前端可包括自裝置的天線至類比至數位轉換器(ADC)的組件,其數位化例如IF濾波、解調等信號。據此,於若干實施例中,此等射頻前端組件(例如,於多-無線電接收器中)可在SOP堆疊體之各層內部體現,如前文就圖1之討論。 In some aspects of the disclosure disclosed herein, a SOP stack (eg, as shown in FIG. 1) may be embodied in a radio receiver and/or other transmitter IC. The RF front end (or communication module) is shown in Figure 4. For example, the SOP stack can be embedded within an RF front end or communication module of a (multi-) radio receiver of a wireless device, such as a tablet, wearable computing device, cell phone (based on well-known cell technology, such as CDMA) , EDGE, UMTS, OFDM, LTE, etc.), Wi-Fi receivers (based on the well-known various IEEE 802.11 standards), and the like. In general, in a radio receiver circuit/module, the radio frequency front end can include circuitry between the antenna and the first intermediate frequency (IF) stage. The RF front end can include components in the receiver that previously input the RF processing signal before the signal is converted to a lower intermediate frequency. For example, the RF front end can include an impedance matching circuit, a band pass filter (BPF), an RF filter, an RF amplifier, a local oscillator (LO), a mixer, and/or other components. Moreover, in a radio receiver embodied in a wireless device such as a tablet computer, a wearable computing device, a cell phone, a Wi-Fi receiver, etc., the radio frequency front end may include an antenna from the device to an analog to digital converter (ADC). A component that digitizes signals such as IF filtering, demodulation, and the like. Accordingly, in several embodiments, such radio front end components (e.g., in a multi-radio receiver) can be embodied within layers of the SOP stack, as discussed above with respect to FIG.

依據本文揭示之各種面向中,如顯示於100之SOP可藉含括一或多個散熱元件加以修改。一或多個散熱元件可排列在同質材料堆疊體內部,諸如只有高效能材料或只有低效能材料。一或多個散熱元件也可排列在異質材料堆疊體內部,諸如有高效能材料或低效能材料兩者之一堆疊體。如圖1中顯示,一或多個散熱元件諸如散熱器材料150可排列接近高功率主動組件以耗散由該主金鑰所產生 的熱。於一非限制性實施例中,散熱元件係在主動組件上方層內,或位在主動組件正上方。散熱元件可配置於兩層高效能材料間,或可配置於兩層高與低效能材料間。可配置於兩層高效能材料間可為高傳導係數材料,諸如金屬,且可包括銅、鋁、柯法(KOVAR)(柯法為卡本特技術公司(Carpenter Technology Corporation)的商品名,乃鎳-鈷鐵合金,設計成與硼矽酸鹽玻璃之熱膨脹特性可相容,以便許可於一定溫度範圍之直接機械連結)或碳化矽(SiC)、或方向性導體諸如石墨其於二維(x-、y-)平面散熱。容後詳述,不同散熱器及透過圖樣堆疊體之組合可運用以實現優化散熱結構。藉由在小形狀因數SOP內部配置的一或多個散熱元件,可減少或消除外部散熱器的需要。 In accordance with the various aspects disclosed herein, an SOP as shown at 100 may be modified by including one or more heat dissipating elements. One or more heat dissipating elements may be arranged inside a stack of homogenous materials, such as only high performance materials or only low performance materials. One or more heat dissipating elements may also be arranged inside the stack of heterogeneous materials, such as a stack of either high performance materials or low performance materials. As shown in FIG. 1, one or more heat dissipating elements, such as heat sink material 150, may be arranged proximate to the high power active component to dissipate the generated by the master key. hot. In one non-limiting embodiment, the heat dissipating component is within the upper layer of the active component or is positioned directly above the active component. The heat dissipating component can be placed between two layers of high performance materials or can be placed between two layers of high and low performance materials. It can be disposed between two layers of high-performance materials, such as metal, and can include copper, aluminum, and KOVAR (Corfa is the trade name of Carpenter Technology Corporation). Nickel-cobalt iron alloy, designed to be compatible with the thermal expansion characteristics of borosilicate glass to permit direct mechanical bonding over a range of temperatures) or tantalum carbide (SiC), or directional conductors such as graphite in two dimensions (x -, y-) Plane heat dissipation. As detailed later, the combination of different heat sinks and through the pattern stack can be used to achieve an optimized heat dissipation structure. The need for an external heat sink can be reduced or eliminated by one or more heat dissipating components disposed within the small form factor SOP.

依據本文揭示之各種面向中,因高效能LCP之適型性質故,熱材之薄片可嵌入LCP類型材料內。具有良好熱性質的銅、石墨、柯法、碳化矽、黃銅及其它材料可嵌入具有高功率耗散的IC(諸如功率放大器PA)下方以許可SOP架構內部之熱管理而仍然維持SFF性質。LCP可被設定環繞該等材料以隨形且形成SOP而無任何空隙或間隙。石墨材料於X-Y方向散逸熱,於某些情況下,可嵌入石墨材料以散布熱量至散熱器/金屬通孔,容後詳述,以將熱從嵌入式SOP結構帶出。 According to the various aspects disclosed herein, the sheet of hot material can be embedded in the LCP type material due to the conformal nature of the high performance LCP. Copper, graphite, coF, tantalum carbide, brass, and other materials with good thermal properties can be embedded under an IC with high power dissipation, such as power amplifier PA, to permit thermal management within the SOP architecture while still maintaining SFF properties. The LCP can be set to surround the materials to conform to the shape and form the SOP without any voids or gaps. The graphite material dissipates heat in the X-Y direction. In some cases, the graphite material can be embedded to dissipate heat to the heat sink/metal vias, as detailed later, to remove heat from the embedded SOP structure.

圖2顯示依據本文揭示之各種面向具有高效能及低效能聚合物層兩者的SOP以形成一材料堆疊體之另一剖面圖。圖2係類似圖1,但顯示功率放大器120,GaAs PA安 裝於基體頂上。針對小型IC組件諸如GaAs PA,其無需嵌入,原因在於其在基體上不會占據大面積。模塑層205可配置於頂安裝組件上方以封裝及保護該SOP。 2 shows another cross-sectional view of various SOPs having both high performance and low performance polymer layers to form a stack of materials in accordance with the disclosure herein. Figure 2 is similar to Figure 1, but showing power amplifier 120, GaAs PA Mounted on top of the base. For small IC components such as GaAs PA, it does not need to be embedded because it does not occupy a large area on the substrate. Molding layer 205 can be disposed over the top mounting assembly to encapsulate and protect the SOP.

圖3a顯示依據本文揭示之各種面向的SOP之剖面圖,其包括嵌入式隔離結構。嵌入式隔離結構係經組配及配置以減少極小形狀因數SOP中的雜訊耦合及串擾問題。類似前文討論的散熱結構,隔離結構可被配置於材料之一均質堆疊體內部,諸如只有高效能材料或只有低效能材料之一材料堆疊體。又,隔離結構也可被配置於材料之一非均質堆疊體內部,諸如具有高及低效能材料兩者的堆疊體。IC顯示於圖3a,IC1(305)、IC2(310)及IC3(315)配置於SOP的高效能材料間。又,一或多個被動組件320顯示嵌入高效能材料層內部。隔離結構325可嵌入SOP內部以減少SOP中的雜訊耦合及串擾。 Figure 3a shows a cross-sectional view of various oriented SOPs in accordance with the disclosure herein, including an embedded isolation structure. Embedded isolation structures are assembled and configured to reduce noise coupling and crosstalk issues in very small form factor SOPs. Like the heat dissipation structure discussed above, the isolation structure can be disposed within a homogenous stack of materials, such as a material stack of only one of high performance materials or only low performance materials. Again, the isolation structure can also be disposed within one of the heterogeneous stacks of materials, such as a stack of both high and low performance materials. The IC is shown in Figure 3a, and IC1 (305), IC2 (310), and IC3 (315) are placed between the high-performance materials of the SOP. Again, one or more passive components 320 are shown embedded within the layer of high performance material. The isolation structure 325 can be embedded inside the SOP to reduce noise coupling and crosstalk in the SOP.

圖3b顯示沿圖3a之線A及線B所取的垂直週期性微通孔結構A及B。微通孔結構330係經組配及配置以減少元件對元件雜訊耦合/串擾。串擾隔離之特性可藉改變垂直結構之週期性調整。圖3c顯示沿圖3a之線C所取的水平週期性隔離結構335。垂直及水平結構兩者可組合而於完整SOP環境內形成改良的隔離。此等隔離結構可用以環繞無線電或數位功能區塊以便隔離RF雜訊以及數位雜訊之諧波。 Figure 3b shows vertical periodic microvia structures A and B taken along line A and line B of Figure 3a. The microvia structure 330 is assembled and configured to reduce component-to-element noise coupling/crosstalk. The characteristics of crosstalk isolation can be adjusted by changing the periodicity of the vertical structure. Figure 3c shows the horizontal periodic isolation structure 335 taken along line C of Figure 3a. Both vertical and horizontal structures can be combined to form improved isolation in a complete SOP environment. These isolation structures can be used to surround radio or digital functional blocks to isolate RF noise and harmonics of digital noise.

於本文揭示之有些面向中,法拉第籠及利用圖樣化金屬的水平電子帶隙(EBG)結構可用於隔離結構。再者,垂直週期性結構也可組合水平EBG金屬圖樣以形成環繞 SOP之期望部分的有效雜訊減少器。 In some of the aspects disclosed herein, Faraday cages and horizontal electronic band gap (EBG) structures that utilize patterned metals can be used to isolate structures. Furthermore, the vertical periodic structure can also combine horizontal EBG metal patterns to form a surround An effective noise reducer for the desired portion of the SOP.

雖然已經基於目前視為最實用且較佳實施例以細節描述本發明用於例示說明目的,但須瞭解此種細節係僅用於例示目的,本發明並不限於揭示的實施例,反而相反地意圖涵蓋落入於隨附之申請專利範圍的精髓及範圍內部之修改及相當配置。舉例言之,須瞭解本發明預期任何實施例之一或多個特徵可組合任何其它實施例之一或多個特徵至可能程度。 Although the present invention has been described in detail for the purpose of illustration and description of the embodiments of the present invention, it is to be understood that the details of the present invention are intended for illustrative purposes only, and the invention is not limited to the disclosed embodiments, but instead It is intended to cover modifications and equivalent arrangements that fall within the spirit and scope of the appended claims. For example, it is contemplated that one or more features of any embodiment can be combined with one or more features of any other embodiments to the extent possible.

100‧‧‧非同質堆疊體 100‧‧‧Non-homogeneous stack

105‧‧‧高效能材料 105‧‧‧High-performance materials

110‧‧‧低效能材料 110‧‧‧Inefficient materials

115‧‧‧主動IC組件 115‧‧‧Active IC components

120‧‧‧功率放大器(PA) 120‧‧‧Power Amplifier (PA)

125‧‧‧RFIC及BB/MAC IC 125‧‧‧RFIC and BB/MAC IC

130‧‧‧被動組件 130‧‧‧ Passive components

135‧‧‧天線 135‧‧‧Antenna

140‧‧‧金屬線 140‧‧‧Metal wire

150‧‧‧散熱器材料 150‧‧‧ radiator material

Claims (15)

一種通訊裝置,其包含:一實體通訊模組,其經組配以至少接收及處理無線射頻(RF)信號,該實體通訊模組包含:配置成一堆疊層體之一小形狀因數平台,其包含:具有一第一適型材料之該堆疊層體中之一第一層;具有一第二適型材料之該堆疊層體中之一第二層;具有一第三材料之該堆疊層體中之一第三層,其中該第一適型材料及該第二適型材料係比該第三材料更具有可撓性;以及一或多個電子組件,其嵌入於該堆疊層體內部,其中該等一或多個電子組件係經組配以在一無線信號之一頻率在該裝置處被轉換成一較低頻之前,處理經接收之該無線信號。 A communication device comprising: a physical communication module configured to receive and process at least a radio frequency (RF) signal, the physical communication module comprising: a small form factor platform configured as a stacked layer, comprising a first layer of the stacked layer body having a first conformal material; a second layer of the stacked layer body having a second conformal material; and the stacked layer body having a third material a third layer, wherein the first conformal material and the second conformal material are more flexible than the third material; and one or more electronic components embedded in the stacked layer body, wherein The one or more electronic components are configured to process the received wireless signal prior to being converted to a lower frequency at the device at a frequency of the wireless signal. 如請求項1之裝置,其進一步包含:一散熱元件,其經組配以耗散產生自該等一或多個電子組件的熱。 The device of claim 1, further comprising: a heat dissipating component assembled to dissipate heat generated from the one or more electronic components. 如請求項2之裝置,其中該散熱元件係配置於該第一層與該第二層間。 The device of claim 2, wherein the heat dissipating component is disposed between the first layer and the second layer. 如請求項1之裝置,其中該第一適型材料及該第二適型 材料為相同材料。 The device of claim 1, wherein the first conformable material and the second conformal type The materials are the same material. 如請求項1之裝置,其中該第一適型材料及該第二適型材料為不同材料。 The device of claim 1, wherein the first conformable material and the second conformable material are different materials. 如請求項1之裝置,其中該第一適型材料、該第二適型材料或兩者包括一聚合物。 The device of claim 1, wherein the first conformable material, the second conformable material, or both comprise a polymer. 如請求項1之裝置,其中該第一層、或該第二層、或二者之厚度係小於或等於25微米。 The device of claim 1, wherein the first layer, or the second layer, or both are less than or equal to 25 microns in thickness. 如請求項1之裝置,其中該堆疊層體之一厚度係小於0.5毫米。 The device of claim 1, wherein one of the stacked layers has a thickness of less than 0.5 mm. 如請求項1之裝置,其進一步包含:一隔離結構,其配置於該堆疊層體內部,且經組配以減少由該等一或多個電子組件中之任一者所產生的雜訊、該等一或多個電子組件中之至少兩者間之串擾、或兩者。 The device of claim 1, further comprising: an isolation structure disposed within the stacked layer and configured to reduce noise generated by any one of the one or more electronic components, Crosstalk between at least two of the one or more electronic components, or both. 如請求項9之裝置,其中該隔離結構包括配置成一週期性組態之多個元件,其中該隔離結構之一操作特性係基於該等多個元件之該週期性組態的一週期為可調適。 The device of claim 9, wherein the isolation structure comprises a plurality of components configured to be periodically configured, wherein an operational characteristic of the isolation structure is adapted based on a periodicity of the periodic configuration of the plurality of components . 如請求項1之裝置,其中該等一或多個電子組件包含一天線、一阻抗匹配電路、一帶通濾波器(BPF)、一RF濾波器、一RF放大器、一本機振盪器(LO)及一混合器中之至少一者。 The device of claim 1, wherein the one or more electronic components comprise an antenna, an impedance matching circuit, a band pass filter (BPF), an RF filter, an RF amplifier, and a local oscillator (LO) And at least one of the mixers. 一種用於通訊之方法,其包含:於一實體通訊模組接收及處理無線射頻(RF)信號,其中該實體通訊模組包含: 配置成一堆疊層體之一小形狀因數平台,其包含:具有一第一適型材料之該堆疊層體中之一第一層;具有一第二適型材料之該堆疊層體中之一第二層;具有一第三材料之該堆疊層體中之一第三層,其中該第一適型材料及該第二適型材料係比該第三材料更具有可撓性;以及一或多個電子組件,其嵌入於該堆疊層體內部,其中該等一或多個電子組件係經組配以在一無線信號之一頻率在裝置處被轉換成一較低頻之前,處理經接收之該無線信號。 A method for communication, comprising: receiving and processing a radio frequency (RF) signal in a physical communication module, wherein the physical communication module comprises: a small form factor platform configured as a stacked layer body, comprising: a first layer of the stacked layer body having a first conformal material; and one of the stacked layer bodies having a second conformal material a second layer; a third layer of the stacked layer having a third material, wherein the first conformable material and the second conformable material are more flexible than the third material; and one or more An electronic component embedded in the stacked layer, wherein the one or more electronic components are assembled to receive the received signal at a frequency of one of the wireless signals before being converted to a lower frequency at the device wireless signal. 如請求項12之方法,其中該等一或多個電子組件包含一天線、一阻抗匹配電路、一帶通濾波器(BPF)、一RF濾波器、一RF放大器、一本機振盪器(LO)及一混合器中之至少一者。 The method of claim 12, wherein the one or more electronic components comprise an antenna, an impedance matching circuit, a band pass filter (BPF), an RF filter, an RF amplifier, and a local oscillator (LO) And at least one of the mixers. 如請求項12之方法,其中該第一層、或該第二層、或二者之厚度係小於或等於25微米。 The method of claim 12, wherein the first layer, or the second layer, or both are less than or equal to 25 microns thick. 如請求項12之方法,其中該堆疊層體之一厚度係小於0.5毫米。 The method of claim 12, wherein one of the stacked layers has a thickness of less than 0.5 mm.
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