TWI559305B - Resistive memory with multiple resistive states - Google Patents
Resistive memory with multiple resistive states Download PDFInfo
- Publication number
- TWI559305B TWI559305B TW104125798A TW104125798A TWI559305B TW I559305 B TWI559305 B TW I559305B TW 104125798 A TW104125798 A TW 104125798A TW 104125798 A TW104125798 A TW 104125798A TW I559305 B TWI559305 B TW I559305B
- Authority
- TW
- Taiwan
- Prior art keywords
- electrode
- ion
- resistive memory
- ion conducting
- conducting layer
- Prior art date
Links
Landscapes
- Semiconductor Memories (AREA)
Description
本發明是有關於一種非揮發記憶體,特別是指一種具有多重電阻態的電阻式記憶體。 The present invention relates to a non-volatile memory, and more particularly to a resistive memory having multiple resistance states.
記憶體可概分為揮發性記憶體(volatile memory)與非揮發記憶體(non-volatile memory),其中又以非揮發記憶體中的電阻式記憶體(resistive random access memory,RRAM)具有結構簡單、低操作電壓,及製備容易等優點而被廣泛地研究中。 Memory can be divided into volatile memory and non-volatile memory, and the resistive memory (RRAM) in non-volatile memory has a simple structure. Widely studied, low operating voltage, and ease of preparation.
電阻式記憶體的基本結構是以金屬/介電層/金屬為主,並藉由外加偏壓使該介電層形成電流導通路徑,讓該電阻式記憶體產生不同電阻的切換特性,而具有高、低電阻狀態,以作為數位訊號中的「0」與「1」。 The basic structure of the resistive memory is mainly metal/dielectric layer/metal, and the dielectric layer forms a current conduction path by applying a bias voltage, so that the resistive memory generates switching characteristics of different resistances, and has The high and low resistance states are used as "0" and "1" in the digital signal.
為了提高電阻式記憶體的儲存密度及降低生產成本,發展多重電阻態(resistance state)的記憶體是必要的。一般而言,於電阻式記憶體中實現多重電阻態(RS)時,其中一種方式是透過調控導通路徑的粗細,也就是,透過調控導通路徑寬度產生不同電阻值,以達成多重電阻態;另一種方式則是藉由調控導通路徑的數量,以達成多重電 組態。然而,上述達成多重電阻態的方式,在操作上面具有不易控制的缺點。 In order to increase the storage density of resistive memory and reduce the production cost, it is necessary to develop a memory with multiple resistance states. In general, when implementing multiple resistance states (RS) in resistive memory, one way is to control the thickness of the conduction path, that is, to generate different resistance values by adjusting the width of the conduction path to achieve multiple resistance states; One way is to achieve multiple power by regulating the number of conduction paths. configuration. However, the above-described manner of achieving multiple resistance states has the disadvantage of being difficult to control in operation.
因此,本發明之目的,即在提供一種能簡易的達成具有多重電阻態的電阻式記憶體。 Accordingly, it is an object of the present invention to provide a resistive memory having a multi-resistance state that can be easily achieved.
於是本發明具有多重電阻態的電阻式記憶體,包含一第一電極、一第二電極,及一離子傳導單元。 Therefore, the present invention has a resistive memory having multiple resistance states, comprising a first electrode, a second electrode, and an ion conducting unit.
該第二電極與該第一電極間隔設置,該第二電極的氧化電位小於該第一電極,於該第一電極施加一正電壓後能產生多個金屬陽離子。 The second electrode is spaced apart from the first electrode, and the second electrode has an oxidation potential smaller than the first electrode, and a plurality of metal cations can be generated after the positive voltage is applied to the first electrode.
該離子傳導單元夾置於該第一電極與該第二電極之間,並包括一鄰近該第一電極的第一離子傳導層,及一位於該第一離子傳導層與該第二電極之間的第二離子傳導層,該等金屬陽離子在該第一離子傳導層中的擴散速率大於在該第二離子傳導層中的擴散速率。 The ion conducting unit is interposed between the first electrode and the second electrode, and includes a first ion conducting layer adjacent to the first electrode, and a first ion conducting layer and the second electrode a second ion conducting layer, the metal cations having a higher diffusion rate in the first ion conducting layer than in the second ion conducting layer.
本發明的功效在於,利用該等金屬陽離子在該第一離子傳導層中的擴散速率大於在該第二離子傳導層中的擴散速率的特性,在對該第一電極施加不同大小的正電壓時,能使該電阻式記憶體產生多重電阻態。 The effect of the present invention is to utilize the characteristics that the diffusion rate of the metal cations in the first ion conducting layer is greater than the diffusion rate in the second ion conducting layer, when a positive voltage of a different magnitude is applied to the first electrode The resistive memory can be made to generate multiple resistance states.
2‧‧‧電阻式記憶體 2‧‧‧Resistive memory
21‧‧‧第一電極 21‧‧‧First electrode
22‧‧‧第二電極 22‧‧‧second electrode
23‧‧‧離子傳導單元 23‧‧‧Ion Conduction Unit
231‧‧‧第一離子傳導層 231‧‧‧First ion conducting layer
232‧‧‧第二離子傳導層 232‧‧‧Second ion conducting layer
24‧‧‧金屬接觸層 24‧‧‧Metal contact layer
25‧‧‧金屬陽離子 25‧‧‧ metal cation
本發明之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中:圖1是一示意圖,說明本發明具有多重電阻態的電阻 式記憶體的一具體例1;圖2是一示意圖,說明本發明具有多重電阻態的電阻式記憶體的一具體例2;圖3是一示意圖,說明本發明具有多重電阻態的電阻式記憶體的一具體例3;圖4是一能量散射光譜儀關係圖,說明本發明該具體例1的一第一離子傳導層與一第二離子傳導層的組成比例;圖5是一電流與電壓關係圖,說明本發明該具體例1與一具體例2~3電壓切換與電流的關係圖;圖6是一示意圖,說明本發明該具體例1的四個電阻態;圖7是一示意圖,說明本發明該等具體例1~3的一第一中間阻態;圖8是一示意圖,說明本發明該等具體例1~3的一第二中間阻態;圖9是一電壓圖,說明本發明該等具體例1~3切換至不同電阻態所需的電壓值;圖10是一電阻值對溫度關係圖,說明本發明該具體例1於不同溫度之不同電阻態的電阻值;圖11是一電阻值對切換循環次數關係圖,說明本發明該具體例1於不同切換循環次數的於不同電阻態的電阻值。 Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a schematic diagram illustrating the resistance of the present invention having multiple resistance states. A specific example 1 of the memory; FIG. 2 is a schematic view showing a specific example 2 of the resistive memory having multiple resistance states of the present invention; and FIG. 3 is a schematic view showing the resistive memory of the present invention having multiple resistance states A specific example 3 of the body; FIG. 4 is a relationship diagram of an energy scattering spectrometer, illustrating a composition ratio of a first ion conducting layer and a second ion conducting layer of the specific example 1 of the present invention; FIG. 5 is a current-voltage relationship FIG. 6 is a schematic diagram showing the four resistance states of the specific example 1 of the present invention; FIG. 7 is a schematic diagram illustrating the relationship between voltage switching and current of the specific example 1 and the specific example 2 to 3 of the present invention; A first intermediate resistance state of the specific examples 1 to 3 of the present invention; FIG. 8 is a schematic view showing a second intermediate resistance state of the specific examples 1 to 3 of the present invention; and FIG. 9 is a voltage diagram illustrating the present invention. The voltage values required for the specific examples 1 to 3 to switch to different resistance states are shown; FIG. 10 is a graph of resistance versus temperature, illustrating the resistance values of the different resistance states of the specific example 1 of the present invention at different temperatures; FIG. Is a resistance value versus switching cycle number relationship diagram, indicating The specific example 1 of the present invention has different resistance values in different resistance states for different switching cycles.
在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。 Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.
參閱圖1,本發明具有多重電阻態的電阻式記憶體2的一實施例包含一第一電極21、一第二電極22,及一離子傳導單元23。 Referring to FIG. 1, an embodiment of a resistive memory 2 having multiple resistance states of the present invention includes a first electrode 21, a second electrode 22, and an ion conducting unit 23.
該第二電極22與該第一電極21間隔設置,該離子傳導單元23夾置於該第一電極21與該第二電極22之間,且該第二電極22的氧化電位小於該第一電極21,換句話說,該第一電極21的活性大於該第二電極22,因此,對該第一電極21施加一正電壓後,該第一電極21會進行氧化反應,而能產生多個金屬陽離子。 The second electrode 22 is spaced apart from the first electrode 21, the ion conducting unit 23 is interposed between the first electrode 21 and the second electrode 22, and the oxidation potential of the second electrode 22 is smaller than the first electrode. 21, in other words, the activity of the first electrode 21 is greater than that of the second electrode 22. Therefore, after a positive voltage is applied to the first electrode 21, the first electrode 21 undergoes an oxidation reaction to generate a plurality of metals. cation.
適用於本發明該第一電極21的材料是選自銀、銅、鎳等易於進行氧化反應的金屬材料,而該第二電極22則是選自鉑、正摻雜的矽等鈍性材料。 The material suitable for the first electrode 21 of the present invention is a metal material selected from silver, copper, nickel or the like which is susceptible to oxidation reaction, and the second electrode 22 is a passive material selected from platinum or a doped germanium.
該離子傳導單元23包括一鄰近該第一電極21的第一離子傳導層231,及一位於該第一離子傳導層231與該第二電極22之間的第二離子傳導層232,且其中,該等金屬陽離子在該第一離子傳導層231中的擴散速率大於在該第二離子傳導層232中的擴散速率,因此,當對該第一電極21施加該正電壓時,該第一電極21所產生的該等金屬陽離子會依序經由該第一離子傳導層231與該第二離子傳導層232,而向該第二電極22擴散傳導,而形成導通該第一電極21與該第二電極22的導電通路;而當對該第 一電極21施加不同的負電壓時,金屬陽離子則會往該負電壓方向移動而還原,因此,該導電通路會於不同界面中斷,以產生不同的阻態。 The ion conducting unit 23 includes a first ion conducting layer 231 adjacent to the first electrode 21, and a second ion conducting layer 232 between the first ion conducting layer 231 and the second electrode 22, and wherein The diffusion rate of the metal cations in the first ion conductive layer 231 is greater than the diffusion rate in the second ion conductive layer 232, and therefore, when the positive voltage is applied to the first electrode 21, the first electrode 21 The generated metal cations are sequentially diffused and conducted to the second electrode 22 via the first ion conductive layer 231 and the second ion conductive layer 232, thereby forming the first electrode 21 and the second electrode. 22 conductive path; and when the When a different negative voltage is applied to an electrode 21, the metal cation will move toward the negative voltage to be reduced. Therefore, the conductive path will be interrupted at different interfaces to generate different resistance states.
具體地說,該第一離子傳導層231與該第二離子傳導層232的目的在於造成金屬陽離子的擴散速度差,因此,只要能讓該等金屬陽離子在該第一離子傳導層231中的擴散速率大於在該第二離子傳導層232中的擴散速率即可,而該等擴散速率的差異可利用該第一離子傳導層231與該第二離子傳導層232的結構緻密度或搭配材料來加以控制,結構緻密度高(即薄膜品質佳),金屬陽離子擴散速率小;反之,結構緻密度低(即薄膜品質較差),金屬陽離子擴散速率就較大。因此,該第一離子傳導層231與該第二離子傳導層232所選用的材料並無特別限制,且可彼此相同或不同。較佳地,該兩層材料可選用例如氧化矽、氧化鉿,或氧化鋁等高介電材料。 Specifically, the purpose of the first ion conducting layer 231 and the second ion conducting layer 232 is to cause a diffusion speed difference of the metal cations, so that the diffusion of the metal cations in the first ion conducting layer 231 can be performed. The rate may be greater than the diffusion rate in the second ion conducting layer 232, and the difference in the diffusion rates may be determined by the structural density or matching material of the first ion conducting layer 231 and the second ion conducting layer 232. Control, structure density is high (ie, film quality is good), metal cation diffusion rate is small; conversely, structure density is low (ie, film quality is poor), metal cation diffusion rate is larger. Therefore, the materials selected for the first ion conductive layer 231 and the second ion conductive layer 232 are not particularly limited and may be the same or different from each other. Preferably, the two layers of material may be selected from high dielectric materials such as yttria, yttria, or alumina.
當該第一離子傳導層231與該第二離子傳導層232彼此為選用不同材料構成時,可藉由材料的選用,以達成該等金屬陽離子於該兩層傳導層中具有相異擴散速率的目的。而當該第一離子傳導層231與該第二離子傳導層232分別選用相同材料構成時,則可透過製程的控制來改變材料的品質(即結構緻密度)差異,以達成讓該等金屬陽離子於該第一離子傳導層231與該第二離子傳導層232中擴散傳輸時,能具有相異的擴散速率目的。也就是說,無論選用的材料是相同或不同,又或是透過製程來改變材料的品質 差異,其目的都是要讓該等金屬陽離子於該離子傳導單元23中,具有不同的擴散速率。 When the first ion conducting layer 231 and the second ion conducting layer 232 are made of different materials, the materials may be selected to achieve different diffusion rates of the metal cations in the two conductive layers. purpose. When the first ion conducting layer 231 and the second ion conducting layer 232 are respectively made of the same material, the difference in material quality (ie, structural density) can be changed through the control of the process to achieve the metal cations. When the first ion conducting layer 231 and the second ion conducting layer 232 are diffused and transported, they can have different diffusion rate purposes. In other words, whether the materials used are the same or different, or the process is used to change the quality of the material. The purpose of the difference is to have the metal cations in the ion conducting unit 23 having different diffusion rates.
詳細地說,當該第一離子傳導層231與該第二離子傳導層232選用相同材料而藉由製程的控制來改變兩者的品質差異時,可分別藉由、濺鍍(sputtering)、蒸鍍(evaporation)、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、原子沉積(atomic layer deposition),或熱氣相沉積等不同的製程來達成,只要令該第二離子傳導層232的薄膜品質高於該第一離子傳導層231,從而使該等金屬陽離子於該第一離子傳導層231中的擴散速率大於在該第二離子傳導層232中的擴散速率即可。 In detail, when the first ion conducting layer 231 and the second ion conducting layer 232 are made of the same material and the quality difference between the two is changed by the control of the process, respectively, by sputtering, sputtering, steaming Evaporation, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition, or thermal vapor deposition, etc., as long as the second ion conducting layer The film quality of 232 is higher than that of the first ion conducting layer 231, so that the diffusion rate of the metal cations in the first ion conducting layer 231 is greater than the diffusion rate in the second ion conducting layer 232.
另外要說明的是,該第一離子傳導層231與該第二離子傳導層232的厚度差異並無特別限制,只要該第一離子傳導層231與該第二離子傳導層232符合前述差異即可,但是,其中一者的厚度過薄時,形成導電通路或斷路時的阻值差異性會較低,因此,較佳地,該第一離子傳導層231與該第二離子傳導層232的厚度比值介於0.3~3。 It should be noted that the difference in thickness between the first ion conductive layer 231 and the second ion conductive layer 232 is not particularly limited as long as the first ion conductive layer 231 and the second ion conductive layer 232 meet the aforementioned difference. However, when the thickness of one of them is too thin, the difference in resistance when forming a conductive path or an open circuit may be low, and therefore, preferably, the thickness of the first ion conductive layer 231 and the second ion conductive layer 232 The ratio is between 0.3 and 3.
本發明該電阻式記憶體2實施例的離子傳導單元,為具有雙層結構(第一離子傳導層231與該第二離子傳導層232),因此,該電阻式記憶體2除了本身所具有因施加大於臨界值電壓形成導電通路,而產生的低阻態(LRS),及施加一反向電壓,使導電通路形成斷路,所產生的高阻態(HRS)之外,透過該第一離子傳導層231與該第二離子傳 導層232的設置,在施加不同大小的電壓時,還能產生額外的一第一中間阻態(MRS1)及一第二中間阻態(MRS2),而使得該電阻式記憶體2可產生多重(4重)電阻態。 The ion conducting unit of the resistive memory 2 embodiment of the present invention has a two-layer structure (the first ion conducting layer 231 and the second ion conducting layer 232), and therefore, the resistive memory 2 has its own Applying a voltage greater than a threshold voltage to form a conductive path, and generating a low resistance state (LRS), and applying a reverse voltage, causing the conductive path to form an open circuit, and generating a high resistance state (HRS), through the first ion conduction Layer 231 and the second ion pass The conductive layer 2 is configured to generate an additional first intermediate resistance state (MRS1) and a second intermediate resistance state (MRS2) when different voltages are applied, so that the resistive memory 2 can generate multiple (4 heavy) resistance state.
值得一提的是,本發明的該電阻式記憶體2是以雙層結構為例作說明,但不限於此,還可視情況進一步的利用兩層以上的多層結構,而達成更多重電阻態的目的。 It is to be noted that the resistive memory 2 of the present invention is described by taking a two-layer structure as an example, but is not limited thereto, and it is also possible to further utilize a multilayer structure of two or more layers to achieve more heavy resistance states. the goal of.
為了可更清楚的說明本發明具有多重電阻態的電阻式記憶體,以下以三個具體例及其實驗分析進行說明。 In order to more clearly illustrate the resistive memory of the present invention having multiple resistance states, the following description will be made with three specific examples and experimental analysis thereof.
<具體例1> <Specific example 1>
參閱圖1,準備經清洗的正摻雜(n-type)矽晶圓作為該第二電極22,接著,於高溫擴散爐(horizontal furnace)中,在該第二電極22上沉積厚度為15nm的二氧化矽(SiO2)作為該第二離子傳導層232,隨後再透過電漿增強化學氣相沉積法(PECVD)於該第二離子傳導層232上沉積厚度為15nm的氧化矽(SiOx,x<2)作為該第一離子傳導層231,最後再以熱蒸鍍(thermal evaporation)配合遮罩於該第一離子傳導層231上蒸鍍形成厚度為50nm的銀(Ag)薄膜作為該第一電極21,並進一步的於該第一電極21上以熱蒸鍍方式形成厚度為300nm的鋁(Al)薄膜作為金屬接觸層24。要說明的是,由於該第一電極21是選用銀金屬,因此,在該第一電極21上施加該正電壓時,產生的金屬陽離子即為銀離子。 Referring to FIG. 1, a cleaned n-type germanium wafer is prepared as the second electrode 22, and then a thickness of 15 nm is deposited on the second electrode 22 in a high temperature diffusion furnace. As the second ion conductive layer 232, cerium oxide (SiO 2 ) is subsequently deposited on the second ion conductive layer 232 by a plasma enhanced chemical vapor deposition (PECVD) to deposit cerium oxide (SiO x ) having a thickness of 15 nm. x<2) as the first ion conductive layer 231, and finally, a silver (Ag) film having a thickness of 50 nm is formed by vapor deposition on the first ion conductive layer 231 by thermal evaporation as the first An electrode 21 is further formed on the first electrode 21 by thermal evaporation to form an aluminum (Al) film having a thickness of 300 nm as the metal contact layer 24. It should be noted that since the first electrode 21 is made of silver metal, when the positive voltage is applied to the first electrode 21, the generated metal cation is silver ions.
<具體例2> <Specific example 2>
參閱圖2,本發明具有多重電阻態的電阻式記憶體的一具體例2的實施條件大致上是相同於該具體例1,其不同之處在於,該第二離子傳導層232的厚度為8nm,該第一離子傳導層231的厚度則為22nm。 Referring to FIG. 2, the implementation condition of a specific example 2 of the resistive memory having multiple resistance states of the present invention is substantially the same as that of the specific example 1, except that the thickness of the second ion conductive layer 232 is 8 nm. The thickness of the first ion conductive layer 231 is 22 nm.
<具體例3> <Specific example 3>
參閱圖3,本發明具有多重電阻態的電阻式記憶體的一具體例3的實施條件大致上是相同於該具體例1,其不同之處在於,該第二離子傳導層232的厚度為22nm,該第一離子傳導層231的厚度則為8nm。 Referring to FIG. 3, the implementation condition of a specific example 3 of the resistive memory having multiple resistance states is substantially the same as that of the specific example 1, except that the thickness of the second ion conductive layer 232 is 22 nm. The thickness of the first ion conductive layer 231 is 8 nm.
<數據分析> <Data Analysis>
參閱圖4,顯示該具體例1的電阻式記憶體2經由能量散射光譜儀(EDS)所量測的影像分析圖。由此分析圖可得知,以電漿增強化學氣相沉積法(PECVD)形成的氧化矽(該第一離子傳導層231)的氧(O)與矽(Si)的平均比值為1.68;而於高溫擴散爐(horizontal furnace)中生成的氧化矽(該第二離子傳導層232)的氧(O)與矽(Si)的平均比值則為1.96。由此可知,該第一離子傳導層231與該第二離子傳導層232以氧化矽作為材料時,確實能藉由不同的製程,而產生不同比例的氧化矽,當氧(O)與矽(Si)的比值越接近於2時,則具有較佳的緻密度,也就是說,於該具體例1~3中,以在高溫擴散爐中形成的氧化矽作為該第二離子傳導層232的緻密度是高於以電漿增強化學氣相沉積法形成的氧化矽作為該第一離子傳導層231的緻密度,因此,該等金 屬陽離子(銀離子)於緻密度較低的該第一離子傳導層231中傳導時,相較於在緻密度較高的該第二離子傳導層232中傳導,會具有較快的擴散速率。 Referring to Fig. 4, an image analysis chart of the resistive memory 2 of the specific example 1 measured by an energy scatter spectrometer (EDS) is shown. From this analysis, it can be seen that the average ratio of oxygen (O) to cerium (Si) of cerium oxide (the first ion conducting layer 231) formed by plasma enhanced chemical vapor deposition (PECVD) is 1.68; The average ratio of oxygen (O) to cerium (Si) generated by cerium oxide (the second ion conducting layer 232) generated in a high temperature diffusion furnace was 1.96. It can be seen that when the first ion conducting layer 231 and the second ion conducting layer 232 are made of cerium oxide, different ratios of cerium oxide can be generated by different processes, when oxygen (O) and strontium ( The closer the ratio of Si) is to 2, the better the density is obtained. That is, in the specific examples 1 to 3, yttrium oxide formed in a high-temperature diffusion furnace is used as the second ion-conducting layer 232. The density is higher than the density of the first ion conducting layer 231 formed by the plasma enhanced chemical vapor deposition method. Therefore, the gold When the cation (silver ion) is conducted in the first ion-conducting layer 231 having a lower density, it has a faster diffusion rate than the conduction in the second ion-conducting layer 232 having a higher density.
參閱圖5~8,在讓該等具體例1~3的電阻式記憶體2運作之前,會先對該第一電極21施加一足夠大的正電壓,使該第一電極21產生的金屬陽離子25(銀離子)能由該第一電極21經由該離子傳導單元23擴散傳導至該第二電極22,產生一由多個金屬陽離子25形成的導電通道而使該電阻式記憶體2呈一低阻態(LRS)(見圖6,以該具體例1為例作說明),此即該領域所周知的成形過程(forming)。由圖5中的成形過程(forming)所施加的電壓及其電流曲線圖可知,由於該具體例3的該第二離子傳導層232的厚度為該等具體例1~3中最厚的,因此,需要較大的電壓(約15V)才得以完成成形過程(forming)。 Referring to FIGS. 5-8, before the resistive memory 2 of the specific examples 1 to 3 is operated, a sufficient positive voltage is applied to the first electrode 21 to cause the metal cation generated by the first electrode 21. 25 (silver ions) can be diffused and conducted by the first electrode 21 to the second electrode 22 via the ion conducting unit 23, generating a conductive path formed by the plurality of metal cations 25 to make the resistive memory 2 low. Resistance state (LRS) (see Fig. 6, taking this specific example 1 as an example), which is a forming process well known in the art. From the voltage applied by the forming process in FIG. 5 and the current graph thereof, since the thickness of the second ion conductive layer 232 of the specific example 3 is the thickest among the specific examples 1 to 3, A large voltage (about 15V) is required to complete the forming process.
接著,在該電阻式記憶體2為低阻態(LRS)時,可藉由施加足夠大的負電壓,使該等金屬陽離子25由該第二電極22經由該離子傳導單元23還原至該第一電極21,使得該導電通道中斷,從而使該電阻式記憶體2呈一高阻態(HRS)(見圖6,以該具體例1為例作說明),此即該領域所周知的重置(reset)過程。值得一提的是,由圖5的電流與電壓曲線圖可知,本發明的該電阻式記憶體2於重置(reset)的過程中,可透過先施加適當的負電壓(reset 1),先使該電阻式記憶體2產生一第一中間阻態(MRS1)(見圖6的MRS1及圖7的該具體例1~3的MRS1),然後再持續施加更大的 負電壓(reset 2)才重回該高阻態(HRS)。 Then, when the resistive memory 2 is in a low resistance state (LRS), the metal cations 25 can be reduced from the second electrode 22 to the first electrode 22 via the ion conducting unit 23 by applying a sufficiently large negative voltage. An electrode 21 interrupts the conductive path, so that the resistive memory 2 assumes a high resistance state (HRS) (see FIG. 6, which is exemplified by the specific example 1), which is a well-known weight in the art. Reset process. It should be noted that, according to the current and voltage graphs of FIG. 5, the resistive memory 2 of the present invention can be first applied with a suitable negative voltage (reset 1) during the reset process. The resistive memory 2 is caused to generate a first intermediate resistance state (MRS1) (see MRS1 of FIG. 6 and MRS1 of the specific example 1 to 3 of FIG. 7), and then continue to apply a larger The negative voltage (reset 2) returns to the high resistance state (HRS).
造成該第一中間阻態(MRS1)的原因,即是透過本發明該第一離子傳導層231與該第二離子傳導層232的設計,使該等金屬陽離子25於該第一離子傳導層231與該第二離子傳導層232中具有相異的擴散速率來達成。也就是說,當施加適當的負電壓時(reset 1),該等金屬陽離子25於該第一離子傳導層231的擴散速率較快,而於該第二離子傳導層232的擴散速率較慢,因此,位於該第一離子傳導層231中的該等金屬陽離子25會較快的往該第一電極21方向移動,從而使該第一離子傳導層231與該第二離子傳導層232的界面不具有該等金屬陽離子25(見圖6的MRS1及圖7的該具體例1~3的MRS1),即形成該第一中間阻態(MRS1)。當對該第一中間阻態(MRS1)持續施加更大的負電壓時(reset 2),則大部分的該等金屬陽離子25會進一步的往該第一電極21方向移動,使該電阻式記憶體2呈不導通的高阻態(HRS)(見圖6)。 The reason for causing the first intermediate resistance state (MRS1) is that the first ion conductive layer 231 and the second ion conductive layer 232 are designed to pass the metal cations 25 to the first ion conductive layer 231. This is achieved by having a different diffusion rate from the second ion conducting layer 232. That is, when a suitable negative voltage is applied (reset 1), the diffusion rate of the metal cations 25 to the first ion conductive layer 231 is faster, and the diffusion rate of the second ion conductive layer 232 is slower. Therefore, the metal cations 25 located in the first ion conducting layer 231 move toward the first electrode 21 faster, so that the interface between the first ion conducting layer 231 and the second ion conducting layer 232 is not The first intermediate resistance state (MRS1) is formed by having the metal cations 25 (see MRS1 of FIG. 6 and MRS1 of the specific examples 1-3 of FIG. 7). When a larger negative voltage (reset 2) is continuously applied to the first intermediate resistance state (MRS1), most of the metal cations 25 are further moved toward the first electrode 21, so that the resistive memory Body 2 is a non-conducting high resistance state (HRS) (see Figure 6).
最後,可再藉由施加足夠大的正電壓,使該電阻式記憶體2由高阻態(HRS)重回低阻態(LRS),即該領域所周知的重新形成(set)過程。同樣地,由圖5的電流與電壓曲線圖可知,本發明的該電阻式記憶體2於重新形成(set)的過程中,可透過先施加適當的正電壓(set 1),從而使該電阻式記憶體2產生一第二中間阻態(MRS2)(見圖6的MRS2及圖8的該具體例1~3的MRS2),然後再持續施加更大的正電壓(set 2)才重回該低阻態(LRS)。 Finally, the resistive memory 2 can be returned from the high resistance state (HRS) back to the low resistance state (LRS) by applying a sufficiently large positive voltage, a well-known set process in the art. Similarly, it can be seen from the current and voltage graphs of FIG. 5 that the resistive memory 2 of the present invention can be applied by applying an appropriate positive voltage (set 1) during the set-up process. The memory 2 generates a second intermediate resistance state (MRS2) (see MRS2 of FIG. 6 and MRS2 of the specific example 1 to 3 of FIG. 8), and then continues to apply a larger positive voltage (set 2) to return. The low resistance state (LRS).
造成該第二中間阻態(MRS2)的原因,也是透過該第一離子傳導層231與該第二離子傳導層232的設計來達成。當施加適當的正電壓時(set 1),該等金屬陽離子25會較快的經由該第一離子傳導層231往該第二離子傳導層232方向移動,而該等金屬陽離子25於該第二離子傳導層232中的移動速率較慢,因此在該適當的正電壓下,於該第二離子傳導層232與該第二電極22的界面不具有該等金屬陽離子(見圖6的MRS2及圖8的該具體例1~3的MRS2),即形成該第二中間阻態(MRS2)。持續施加更大的正電壓時,該等金屬陽離子25會進一步的往該第二電極22方向移動,使該電阻式記憶體呈導通的低阻態(LRS)(見圖6)。 The reason for causing the second intermediate resistance state (MRS2) is also achieved by the design of the first ion conductive layer 231 and the second ion conductive layer 232. When a suitable positive voltage is applied (set 1), the metal cations 25 move faster through the first ion conducting layer 231 toward the second ion conducting layer 232, and the metal cations 25 are in the second The rate of movement in the ion conducting layer 232 is slower, so at the appropriate positive voltage, the interface between the second ion conducting layer 232 and the second electrode 22 does not have the metal cations (see MRS2 and Figure 6). The MRS 2) of the specific examples 1 to 3 of 8 forms the second intermediate resistance state (MRS2). When a larger positive voltage is continuously applied, the metal cations 25 are further moved toward the second electrode 22, causing the resistive memory to conduct a low resistance state (LRS) (see FIG. 6).
配合地參閱圖9,隨著該等具體例1~3增加該第二離子傳導層232的厚度,無論是重置(reset)過程或是重新形成(set)的過程,其所需施加的電壓也隨之增加。主要是因為該第二離子傳導層232的化學計量(stoichiometric)趨近於SiO2而具有較緻密的狀態(見圖4),因此需要較高的電壓予以驅動。 Referring to FIG. 9 in combination, as the specific examples 1-3 increase the thickness of the second ion conducting layer 232, whether it is a reset process or a set process, the required voltage is applied. It also increases. Mainly because the stoichiometric of the second ion conducting layer 232 is closer to SiO 2 and has a denser state (see FIG. 4), so a higher voltage is required to drive.
配合地參閱圖10,以該具體例1為例作說明,使用0.2V的讀取電壓並在不同溫度(25℃、85℃,及125℃)對該具體例1量測約104s,以測試該具體例1的維持性。經過上述長時間的測試且將溫度提高至125℃時,該具體例1的每一個阻態之間還能維持在兩個數量級的差異,而能有效的辨別各阻態。本發明該電阻式記憶體2具有此良好的維持性,主要是歸因於該離子傳導單元23使用了高品質的 氧化矽層,相較於其他材料,銀離子在堆疊的氧化矽層中具有較低的擴散率,因而能在測試期間減緩該第一電極21的銀離子再生,以提高整體維持性。 Referring to FIG. 10, the specific example 1 is taken as an example, and a specific voltage of 25 V is used, and the specific example 1 is measured at different temperatures (25° C., 85° C., and 125° C.) for about 10 4 s. The maintenance of this specific example 1 was tested. After the long-term test described above and the temperature is raised to 125 ° C, the difference between the two resistance states of the specific example 1 can be maintained at two orders of magnitude, and the respective resistance states can be effectively distinguished. The resistive memory 2 of the present invention has such good maintenance, mainly due to the use of a high-quality yttrium oxide layer by the ion-conducting unit 23, which has silver ions in the stacked yttrium oxide layer compared to other materials. The lower diffusion rate allows the silver ion regeneration of the first electrode 21 to be slowed down during the test to improve overall maintenance.
配合地參閱圖11,以該具體例1為例作說明,對該具體例1進行循環測試(cycling test),對該具體例1於set 1、set 2、reset 1,及reset 2所施加的電壓分別為+3.5V、+6V、-4.5V,及-9V。該具體例1進行連續的切換測試(LRS→MRS1→HRS→MRS2→LRS)可超過五次循環以上,且能使其每一個阻態之間能保持有兩個數量級的差異。 Referring to FIG. 11 in cooperation, the specific example 1 is taken as an example, and the specific example 1 is subjected to a cycling test, and the specific example 1 is applied to set 1, set 2, reset 1, and reset 2. The voltages are +3.5V, +6V, -4.5V, and -9V. The specific example 1 performs a continuous switching test (LRS→MRS1→HRS→MRS2→LRS) over five cycles, and can maintain a difference of two orders of magnitude between each of the resistance states.
綜上所述,本發明具有多重電阻態的電阻式記憶體,透過製程來形成結構品質具有差異的該第一離子傳導層231與該第二離子傳導層232,從而使該第一電極21產生的金屬陽離子於該第一離子傳導層231中的擴散速率大於在該第二離子傳導層232中的擴散速率,令該電阻式記憶體2除了原本具有的高阻態(HRS)與低阻態(LRS)之外,還能透過此擴散速率的差異,藉由施加適當的電壓使該電阻式記憶體2具有不同電阻值,而產生該第一中間阻態(MRS1)及該第二中間阻態(MRS2),使該電阻式記憶體2具有多重的電阻態,故確實能達成本發明之目的。 In summary, the present invention has a resistive memory having multiple resistance states, and the first ion conductive layer 231 and the second ion conductive layer 232 having different structural qualities are formed through a process, thereby causing the first electrode 21 to be generated. The diffusion rate of the metal cation in the first ion conducting layer 231 is greater than the diffusion rate in the second ion conducting layer 232, so that the resistive memory 2 has a high resistance state (HRS) and a low resistance state. In addition to (LRS), the first intermediate resistance state (MRS1) and the second intermediate resistance can be generated by applying a suitable voltage to cause the resistive memory 2 to have different resistance values by applying a difference in the diffusion rate. The state (MRS2) makes the resistive memory 2 have multiple resistance states, so that the object of the present invention can be achieved.
惟以上所述者,僅為本發明之較佳實施例而已,當不能以此限定本發明實施之範圍,即大凡依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。 The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and patent specification content of the present invention, All remain within the scope of the invention patent.
2‧‧‧電阻式記憶體 2‧‧‧Resistive memory
21‧‧‧第一電極 21‧‧‧First electrode
22‧‧‧第二電極 22‧‧‧second electrode
23‧‧‧離子傳導單元 23‧‧‧Ion Conduction Unit
231‧‧‧第一離子傳導層 231‧‧‧First ion conducting layer
232‧‧‧第二離子傳導層 232‧‧‧Second ion conducting layer
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104125798A TWI559305B (en) | 2015-08-07 | 2015-08-07 | Resistive memory with multiple resistive states |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104125798A TWI559305B (en) | 2015-08-07 | 2015-08-07 | Resistive memory with multiple resistive states |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI559305B true TWI559305B (en) | 2016-11-21 |
TW201706996A TW201706996A (en) | 2017-02-16 |
Family
ID=57851739
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104125798A TWI559305B (en) | 2015-08-07 | 2015-08-07 | Resistive memory with multiple resistive states |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI559305B (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5517065B1 (en) * | 1970-11-04 | 1980-05-08 | ||
US7786459B2 (en) * | 2004-11-15 | 2010-08-31 | Sony Corporation | Memory element and memory device comprising memory layer positioned between first and second electrodes |
US8476614B2 (en) * | 2009-10-26 | 2013-07-02 | Sony Corporation | Memory device and fabrication process thereof |
US20140183437A1 (en) * | 2011-03-18 | 2014-07-03 | Sony Corporation | Memory element and memory device |
US20140376301A1 (en) * | 2011-06-10 | 2014-12-25 | Sony Corporation | Memory element and memory device |
US20150083987A1 (en) * | 2012-03-14 | 2015-03-26 | Tokyo Institute Of Technology | Resistance change memory device |
TWI489622B (en) * | 2007-08-06 | 2015-06-21 | Sony Corp | Memory elements and memory devices |
-
2015
- 2015-08-07 TW TW104125798A patent/TWI559305B/en not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5517065B1 (en) * | 1970-11-04 | 1980-05-08 | ||
US7786459B2 (en) * | 2004-11-15 | 2010-08-31 | Sony Corporation | Memory element and memory device comprising memory layer positioned between first and second electrodes |
TWI489622B (en) * | 2007-08-06 | 2015-06-21 | Sony Corp | Memory elements and memory devices |
US8476614B2 (en) * | 2009-10-26 | 2013-07-02 | Sony Corporation | Memory device and fabrication process thereof |
US20140183437A1 (en) * | 2011-03-18 | 2014-07-03 | Sony Corporation | Memory element and memory device |
US20140376301A1 (en) * | 2011-06-10 | 2014-12-25 | Sony Corporation | Memory element and memory device |
US20150083987A1 (en) * | 2012-03-14 | 2015-03-26 | Tokyo Institute Of Technology | Resistance change memory device |
Non-Patent Citations (1)
Title |
---|
Michael N. Kozicki, "Cation-based resistive memory", Nanoelectronics Conference (INEC), 2011 IEEE 4th International, 21-24 June 2011 * |
Also Published As
Publication number | Publication date |
---|---|
TW201706996A (en) | 2017-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Wang et al. | Performance improvement of resistive switching memory achieved by enhancing local-electric-field near electromigrated Ag-nanoclusters | |
Kumar et al. | High-performance TiN/Al 2 O 3/ZnO/Al 2 O 3/TiN flexible RRAM device with high bending condition | |
US9525133B2 (en) | Resistive random access memory with high uniformity and low power consumption and method for fabricating the same | |
Chuang et al. | Impact of the stacking order of HfO x and AlO x dielectric films on RRAM switching mechanisms to behave digital resistive switching and synaptic characteristics | |
WO2008038365A1 (en) | Variable-resistance element | |
Lee et al. | Improvement of Synaptic Properties in Oxygen‐Based Synaptic Transistors Due to the Accelerated Ion Migration in Sub‐Stoichiometric Channels | |
Choi et al. | Structural engineering of Li-based electronic synapse for high reliability | |
US8907314B2 (en) | MoOx-based resistance switching materials | |
Ismail et al. | Electronic synaptic plasticity and analog switching characteristics in Pt/TiOx/AlOx/AlTaON/TaN multilayer RRAM for artificial synapses | |
Chen et al. | Forming-free HfO 2 bipolar RRAM device with improved endurance and high speed operation | |
TWI548127B (en) | Resistive random access memory | |
Sahu et al. | Studies on transient characteristics of unipolar resistive switching processes in TiO2 thin film grown by atomic layer deposition | |
Liu et al. | Interfacial resistive switching properties in Ti/La0. 7Ca0. 3MnO3/Pt sandwich structures | |
He et al. | Interconversion between bipolar and complementary behavior in nanoscale resistive switching devices | |
Zhou et al. | Study of the bipolar resistive‐switching behaviors in Pt/G d O x/T a N x structure for RRAM application | |
Chen et al. | Electrode/oxide interface engineering by inserting single-layer graphene: Application for HfO x-based resistive random access memory | |
Banerjee et al. | Investigation of retention behavior of TiO x/Al 2 O 3 resistive memory and its failure mechanism based on Meyer–Neldel rule | |
TWI553636B (en) | Resistance random access memory and fabrication method thereof | |
TWI559305B (en) | Resistive memory with multiple resistive states | |
Zhou et al. | HfOx bipolar resistive memory with robust endurance using ZrNx as buttom electrode | |
Li et al. | Asymmetric resistive switching effect in Au/Nb: SrTiO3 Schottky junctions | |
Okamoto et al. | Improved resistive switching characteristics of NiO resistance random-access memory using post-plasma-oxidation process | |
Li et al. | Studies on structural and resistive switching properties of Al/ZnO/Al structured resistive random access memory | |
Yu et al. | Characterization and modeling of the conduction and switching mechanisms of HfOx based RRAM | |
JP5690635B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |