TWI558097B - Balanced up - frequency mixing circuit - Google Patents
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本發明是有關於一種混頻電路，特別是指一種平衡式升頻混頻電路。 The invention relates to a mixing circuit, in particular to a balanced up-conversion mixing circuit.
現有的升頻混頻電路主要是以吉伯特混頻電路(Gilbert Cell)或次諧波混頻電路為主體架構，以進行混頻，且習知通常是藉由增加一混頻電路所需的功率來提升該混頻電路的轉換增益，導致該混頻電路的功率損耗增加。反之，若欲降低功率損耗則須降低該混頻電路所需的功率，導致該混頻電路的轉換增益無法提升。 The existing up-conversion mixing circuit is mainly based on a Gilbert Cell or a sub-harmonic mixing circuit for mixing, and is usually required by adding a mixing circuit. The power is increased to increase the conversion gain of the mixer circuit, resulting in an increase in power loss of the mixer circuit. Conversely, if the power loss is to be reduced, the power required by the mixing circuit must be reduced, and the conversion gain of the mixing circuit cannot be improved.
因此，本發明之第一目的，即在提供一種可提升轉換增益的平衡式升頻混頻電路。 Accordingly, a first object of the present invention is to provide a balanced up-conversion mixing circuit that can increase conversion gain.
於是本發明平衡式升頻混頻電路，包含一混頻器及一負載器。 Therefore, the balanced up-converting mixing circuit of the present invention comprises a mixer and a loader.
該混頻器接收一差動振盪電壓及一差動中頻電壓，並將該差動振盪電壓及該差動中頻電壓進行混頻以產生一具有正、負相的差動射頻電流，且該差動射頻電流的一頻率相關於該差動振盪電壓及該差動中頻電壓的頻率，且該混頻器包括一增益放大單元及一混頻單元。 The mixer receives a differential oscillating voltage and a differential intermediate frequency voltage, and mixes the differential oscillating voltage and the differential intermediate frequency voltage to generate a differential RF current having positive and negative phases, and A frequency of the differential RF current is related to the differential oscillating voltage and a frequency of the differential intermediate frequency voltage, and the mixer includes a gain amplifying unit and a mixing unit.
該增益放大單元具有一第一與第二電感及一第一至第四電晶體，該第一及第二電晶體連接成一差動對，用以將該差動中頻電壓轉換成一差動中頻電流，串接的該第三電晶體及該第一電感、串接的該第四電晶體及該第二電感各自疊接於所對應的該第一及第二電晶體，用以提高該增益放大單元的轉換增益。 The gain amplifying unit has a first and a second inductor and a first to fourth transistors, and the first and second transistors are connected to form a differential pair for converting the differential intermediate frequency voltage into a differential a frequency current, the serially connected third transistor and the first inductor, the serially connected fourth transistor, and the second inductor are respectively overlapped with the corresponding first and second transistors for improving the The conversion gain of the gain amplification unit.
該混頻單元電連接該增益放大單元以接收該差動中頻電流，且接收該差動振盪電壓，並根據該差動中頻電流及該差動振盪電壓進行混頻，以產生該差動射頻電流。 The mixing unit is electrically connected to the gain amplifying unit to receive the differential intermediate frequency current, and receives the differential oscillating voltage, and performs mixing according to the differential intermediate frequency current and the differential oscillating voltage to generate the differential RF current.
該負載器電連接該混頻器之該混頻單元以接收該差動射頻電流，並根據該差動射頻電流與一阻抗值來產生一具有正、負相的第一差動射頻電壓。 The loader is electrically connected to the mixing unit of the mixer to receive the differential RF current, and generates a first differential RF voltage having positive and negative phases according to the differential RF current and an impedance value.
本發明之第二目的，即在提供一種可提升轉換增益的平衡式升頻混頻電路。 A second object of the present invention is to provide a balanced up-conversion mixing circuit that can increase conversion gain.
該平衡式升頻混頻電路，包含一混頻器、一負載器及一信號放大器。 The balanced up-conversion mixing circuit comprises a mixer, a loader and a signal amplifier.
該混頻器接收一差動振盪電壓及一差動中頻電壓，並將該差動振盪電壓及該差動中頻電壓進行混頻以產生一具有正、負相的差動射頻電流，且該差動射頻電流的一頻率相關於該差動振盪電壓及該差動中頻電壓的頻率。 The mixer receives a differential oscillating voltage and a differential intermediate frequency voltage, and mixes the differential oscillating voltage and the differential intermediate frequency voltage to generate a differential RF current having positive and negative phases, and A frequency of the differential RF current is related to the differential oscillating voltage and a frequency of the differential intermediate frequency voltage.
該負載器電連接該混頻器以接收該差動射頻電流，並根據該差動射頻電流與一阻抗值來產生一具有正、負相之第一差動射頻電壓。 The loader is electrically connected to the mixer to receive the differential RF current, and generates a first differential RF voltage having positive and negative phases according to the differential RF current and an impedance value.
該信號放大器電連接該負載器及該混頻器以接收來自該負載器之該第一差動射頻電壓，並據以將該第一差動射頻電壓進行增益放大，來產生一具有正、負相的第二差動射頻電壓。 The signal amplifier is electrically connected to the loader and the mixer to receive the first differential RF voltage from the loader, and according to the gain amplification of the first differential RF voltage, to generate a positive and negative The second differential RF voltage of the phase.
1‧‧‧單端轉差動器 1‧‧‧ single-ended rotary differential
2‧‧‧負阻提升器 2‧‧‧Negative resistance riser
21‧‧‧第一負阻電晶體 21‧‧‧First negative resistance transistor
22‧‧‧第二負阻電晶體 22‧‧‧Second negative resistance transistor
3‧‧‧混頻器 3‧‧‧ Mixer
31‧‧‧電流源 31‧‧‧current source
311‧‧‧電阻 311‧‧‧resistance
312‧‧‧電晶體 312‧‧‧Optoelectronics
32‧‧‧增益放大單元 32‧‧‧ Gain amplification unit
321‧‧‧第一電晶體 321‧‧‧First transistor
322‧‧‧第二電晶體 322‧‧‧Second transistor
323‧‧‧第三電晶體 323‧‧‧ Third transistor
324‧‧‧第四電晶體 324‧‧‧4th transistor
325‧‧‧第一電感 325‧‧‧First inductance
326‧‧‧第二電感 326‧‧‧second inductance
327‧‧‧第一電阻 327‧‧‧First resistance
328‧‧‧第二電阻 328‧‧‧second resistance
329‧‧‧負阻補償器 329‧‧‧Negative resistance compensator
70‧‧‧第一補償電晶體 70‧‧‧First compensation transistor
71‧‧‧第二補償電晶體 71‧‧‧Second compensation transistor
33‧‧‧混頻單元 33‧‧‧mixing unit
331‧‧‧第一混頻電晶體 331‧‧‧First Mixing Transistor
332‧‧‧第二混頻電晶體 332‧‧‧Second mixing transistor
333‧‧‧第三混頻電晶體 333‧‧‧third mixing transistor
334‧‧‧第四混頻電晶體 334‧‧‧fourth mixing transistor
4‧‧‧負載器 4‧‧‧Loader
41‧‧‧第一電感 41‧‧‧First inductance
42‧‧‧第二電感 42‧‧‧second inductance
5‧‧‧信號放大器 5‧‧‧Signal Amplifier
51‧‧‧第一放大電晶體 51‧‧‧First magnifying transistor
52‧‧‧第二放大電晶體 52‧‧‧Second amplified transistor
53‧‧‧第三放大電晶體 53‧‧‧ Third amplified transistor
54‧‧‧第四放大電晶體 54‧‧‧ fourth magnifying transistor
55‧‧‧第一放大電阻 55‧‧‧First amplification resistor
56‧‧‧第二放大電阻 56‧‧‧second amplification resistor
6‧‧‧差動轉單端器 6‧‧‧Differential to single-ended
VDD‧‧‧直流偏壓 VDD‧‧‧DC bias
VG1‧‧‧第一偏壓 VG1‧‧‧First bias
VG2‧‧‧第二偏壓 VG2‧‧‧second bias
I1‧‧‧輸出電流 I1‧‧‧ output current
本發明之其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中：圖1是一電路圖，說明本發明平衡式升頻混頻電路之一較佳實施例；圖2是一電路圖，說明該較佳實施例的一輸出電流；圖3是一電路圖，說明該較佳實施例之一變形；及圖4是一頻率變化關係圖，說明該較佳實施例、該較佳實施例之該變形及習知吉伯特混頻電路的轉換增益對一頻率變化。 Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a circuit diagram illustrating a preferred embodiment of the balanced upconversion mixing circuit of the present invention; A circuit diagram illustrating an output current of the preferred embodiment; FIG. 3 is a circuit diagram illustrating a variation of the preferred embodiment; and FIG. 4 is a frequency variation diagram illustrating the preferred embodiment and the preferred embodiment. This variation of the embodiment and the conversion gain of the conventional Gilbert mixer circuit vary for a frequency.
在本發明被詳細描述之前，應當注意在以下的說明內容中，類似的元件是以相同的編號來表示。 Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.
參閱圖1，本發明平衡式升頻混頻電路之較佳實施例包含一單端轉差動器(Balun)1、一負阻提升器2、一混頻器3、一負載器4、一信號放大器5，及一差動轉單端器6。 Referring to FIG. 1, a preferred embodiment of the balanced up-conversion mixing circuit of the present invention comprises a single-ended differential (Balun) 1, a negative-resistance riser 2, a mixer 3, a loader 4, and a The signal amplifier 5, and a differential to single-ended unit 6.
該單端轉差動器1用來接收一單端振盪電壓，並將該單端振盪電壓轉換成一具有正、負相的差動振盪電 壓。 The single-ended rotating differential 1 is configured to receive a single-ended oscillating voltage and convert the single-ended oscillating voltage into a differential oscillating electric current having positive and negative phases. Pressure.
該負阻提升器2具有一轉導值，用來接收一直流偏壓VDD，並據以產生一第一及第二輸入電流，且該負阻提升器2具有一第一及第二負阻電晶體21、22。 The negative resistance riser 2 has a transconductance value for receiving the DC bias voltage VDD, and accordingly generating a first and second input current, and the negative resistance riser 2 has a first and second negative resistance Transistors 21, 22.
該第一及第二負阻電晶體21、22分別具有一接收該直流偏壓VDD的第一端、一第二端，及一控制端，該第一及第二負阻電晶體21、22的控制端分別電連接該第二及第一負阻電晶體22、21的第二端，且該第一及第二負阻電晶體21、22的第二端分別提供該第一及第二輸入電流，該第一及第二輸入電流的大小相關於該負阻提升器2的轉導值，該負阻提升器2的轉導值相關於該第一及第二負阻電晶體21、22的轉導值。 The first and second negative-resistance transistors 21 and 22 respectively have a first end, a second end, and a control end for receiving the DC bias voltage VDD, and the first and second negative-resistance transistors 21 and 22 The control terminals are electrically connected to the second ends of the second and first negative-resistance transistors 22, 21, respectively, and the second ends of the first and second negative-resistance transistors 21, 22 respectively provide the first and second ends Input current, the magnitude of the first and second input currents is related to the transconductance value of the negative resistance riser 2, and the transduction value of the negative resistance riser 2 is related to the first and second negative resistance transistors 21, The transduction value of 22.
該混頻器3電連接該單端轉差動器1及該負阻提升器2，以接收來自該單端轉差動器1的該差動振盪電壓及來自該負阻提升器2的該第一及第二輸入電流，且接收一具有正、負相的差動中頻電壓，並將該差動中頻電壓、該差動振盪電壓及該第一與第二輸入電流進行混頻以產生一具有正、負相的差動射頻電流，且該差動射頻電流的大小正比於該第一及第二輸入電流的大小，該差動射頻電流的一頻率相關於該差動振盪電壓及該差動中頻電壓的頻率。舉例說明，但不以此為限，當該差動振盪電壓的頻率為59.9GHz，該差動中頻電壓的頻率為0.1GHz，則該差動射頻電流的頻率為60GHz。 The mixer 3 is electrically connected to the single-ended rotating differential 1 and the negative resistance riser 2 to receive the differential oscillating voltage from the single-ended rotating differential 1 and the same from the negative resistance riser 2 First and second input currents, and receiving a differential intermediate frequency voltage having positive and negative phases, and mixing the differential intermediate frequency voltage, the differential oscillation voltage, and the first and second input currents Generating a differential RF current having positive and negative phases, and the magnitude of the differential RF current is proportional to the magnitude of the first and second input currents, a frequency of the differential RF current being related to the differential oscillating voltage and The frequency of the differential intermediate frequency voltage. For example, but not limited thereto, when the frequency of the differential oscillating voltage is 59.9 GHz and the frequency of the differential intermediate frequency voltage is 0.1 GHz, the frequency of the differential RF current is 60 GHz.
該混頻器3包括一電流源31、一增益放大單元 32，及一混頻單元33。 The mixer 3 includes a current source 31 and a gain amplifying unit 32, and a mixing unit 33.
該電流源31用以接收一第一偏壓VG1，並據以提供一偏壓電流，且該電流源31具有一電阻311及一電晶體312。 The current source 31 is configured to receive a first bias voltage VG1 and provide a bias current, and the current source 31 has a resistor 311 and a transistor 312.
該電阻311具有一第一端及一接收該第一偏壓VG1的第二端。該電晶體312具有一第一端、一接地的第二端，及一電連接該電阻311的第一端的控制端，且流經該電晶體312的第一及第二端的電流作為該偏壓電流。 The resistor 311 has a first end and a second end receiving the first bias voltage VG1. The transistor 312 has a first end, a grounded second end, and a control end electrically connected to the first end of the resistor 311, and the current flowing through the first and second ends of the transistor 312 serves as the bias. Voltage current.
該增益放大單元32電連接該電流源31之該電晶體312的第一端以接收該偏壓電流，且接收該差動中頻電壓，並將該差動中頻電壓轉換成一具有正、負相的差動中頻電流，且該增益放大單元32具有一第一至第四電晶體321~324、一第一及第二電感325、326、一第一及第二電阻327、328，及一負阻補償器329。 The gain amplifying unit 32 is electrically connected to the first end of the transistor 312 of the current source 31 to receive the bias current, and receives the differential intermediate frequency voltage, and converts the differential intermediate frequency voltage into a positive and negative a differential intermediate frequency current, and the gain amplifying unit 32 has a first to fourth transistors 321 to 324, a first and second inductors 325 and 326, a first and second resistors 327 and 328, and A negative resistance compensator 329.
該第一及第二電晶體321、322連接成一差動對，用以將該差動中頻電壓轉換成一差動中頻電流。串接的該第三電晶體323及該第一電感325、串接的該第四電晶體324及該第二電感326各自疊接於所對應的該第一及第二電晶體321、322而成一共源共柵(Cascode)的電路架構，用以提高該增益放大單元32的轉換增益。 The first and second transistors 321 and 322 are connected to form a differential pair for converting the differential intermediate frequency voltage into a differential intermediate frequency current. The third transistor 323 and the first inductor 325, the serially connected fourth transistor 324 and the second inductor 326 are respectively connected to the corresponding first and second transistors 321 and 322. A circuit structure of a common source cascode is used to increase the conversion gain of the gain amplifying unit 32.
在此將進一步說明上述元件的具體連接方式，每一電晶體321、322具有一第一端、一第二端，及一控制端，該第一及第二電晶體321、322的第二端相連接且電連接該電流源31之該電晶體312的第一端以接收該偏壓電 流，該第一及第二電晶體321、322的控制端接收各自所對應的該差動中頻電壓的正、負相。每一電感325、326具有一第一及第二端，該第一及第二電感325、326的第二端電連接各自所對應的該第一及第二電晶體321、322的第一端。每一電晶體323、324具有一第一端、一第二端，及一控制端，該第三及第四電晶體323、324的第一端分別提供該差動中頻電流的負、正相，該第三及第四電晶體323、324的第二端電連接各自所對應的該第一及第二電感325、326的第一端。該第一電阻327具有一電連接該第三電晶體323之控制端的第一端，及一接收一第二偏壓VG2的第二端。該第二電阻328具有一接收該第二偏壓VG2的第一端，及一電連接該第四電晶體324之控制端的第二端。 The specific connection manner of the above components will be further described. Each of the transistors 321 and 322 has a first end, a second end, and a control end, and the second ends of the first and second transistors 321, 322 Connecting and electrically connecting the first end of the transistor 312 of the current source 31 to receive the bias voltage The control terminals of the first and second transistors 321 and 322 receive the positive and negative phases of the differential intermediate frequency voltage corresponding thereto. Each of the first and second inductors 325, 326 has a first end and a second end. The second ends of the first and second inductors 325, 326 are electrically connected to the first ends of the first and second transistors 321 and 322 respectively. . Each of the transistors 323, 324 has a first end, a second end, and a control end, and the first ends of the third and fourth transistors 323, 324 respectively provide negative and positive currents of the differential intermediate frequency The second ends of the third and fourth transistors 323, 324 are electrically connected to respective first ends of the first and second inductors 325, 326. The first resistor 327 has a first end electrically connected to the control end of the third transistor 323, and a second end receiving a second bias VG2. The second resistor 328 has a first end receiving the second bias voltage VG2 and a second end electrically connected to the control end of the fourth transistor 324.
該負阻補償器329電連接該第一及第二電晶體321、322，且具有一負阻值，該差動中頻電流的大小相關於該負阻值，且該負阻補償器329具有一第一及第二補償電晶體70、71。該第一補償電晶體70具有一電連接該第二電感326之第二端的第一端、一電連接該第一電晶體321之第二端的第二端，及一接收該差動中頻電壓之負相的控制端。該第二補償電晶體71具有一電連接該第一電感325之第二端的第一端、一電連接該第一補償電晶體70之第二端的第二端，及一接收該差動中頻電壓之正相的控制端。其中，該負阻值相關於該第一及第二補償電晶體70、71的轉導值。 The negative resistance compensator 329 is electrically connected to the first and second transistors 321 and 322 and has a negative resistance value, the magnitude of the differential intermediate frequency current is related to the negative resistance value, and the negative resistance compensator 329 has A first and second compensation transistors 70, 71. The first compensation transistor 70 has a first end electrically connected to the second end of the second inductor 326, a second end electrically connected to the second end of the first transistor 321 , and a differential intermediate frequency voltage received The control end of the negative phase. The second compensation transistor 71 has a first end electrically connected to the second end of the first inductor 325, a second end electrically connected to the second end of the first compensation transistor 70, and a differential intermediate frequency is received. The control side of the positive phase of the voltage. The negative resistance value is related to the transconductance values of the first and second compensation transistors 70, 71.
該混頻單元33電連接該增益放大單元32、該 單端轉差動器1及該負阻提升器2，以接收來自該增益放大單元32的該差動中頻電流，接收來自該單端轉差動器1的該差動振盪電壓，及接收來自該負阻提升器2的該第一及第二輸入電流，並根據該差動中頻電流、該差動振盪電壓及該第一與第二輸入電流進行混頻，以產生該差動射頻電流，且該差動射頻電流的頻率等同於該差動振盪電壓的頻率加該差動中頻電流的頻率，該差動射頻電流的大小正比於該第一及第二輸入電流的大小，且該混頻單元33具有一第一至第四混頻電晶體331~334。 The mixing unit 33 is electrically connected to the gain amplifying unit 32, and the The single-ended rotary differential 1 and the negative resistance riser 2 receive the differential intermediate frequency current from the gain amplifying unit 32, receive the differential oscillating voltage from the single-ended rotating differential 1, and receive The first and second input currents from the negative resistance riser 2 are mixed according to the differential intermediate frequency current, the differential oscillating voltage, and the first and second input currents to generate the differential RF a current, and the frequency of the differential RF current is equal to a frequency of the differential oscillating voltage plus a frequency of the differential intermediate frequency current, the magnitude of the differential RF current being proportional to a magnitude of the first and second input currents, and The mixing unit 33 has a first to fourth mixing transistors 331 to 334.
該第一混頻電晶體331具有一第一端、一電連接該第一負阻電晶體21的第二端及該第三電晶體323的第一端以接收該第一輸入電流及該差動中頻電流之負相的第二端，及一接收該差動振盪電壓之正相的控制端。該第二混頻電晶體332具有一第一端、一電連接該第一混頻電晶體331之第二端的第二端，及一接收該差動振盪電壓之負相的控制端。該第三混頻電晶體333具有一第一端、一電連接該第二負阻電晶體22的第二端及該第四電晶體324的第一端以接收該第二輸入電流及該差動中頻電流之正相的第二端，及一電連接該第二混頻電晶體332之控制端的控制端。該第四混頻電晶體334具有一第一端、一電連接該第三混頻電晶體333之第二端的第二端，及一電連接該第一混頻電晶體331之控制端的控制端。其中，該第一及第三混頻電晶體331、333之第一端相連接並提供該差動射頻電流之負相，且該第二及第四混頻電晶體332、334之第一 端相連接並提供該差動射頻電流之正相。 The first mixing transistor 331 has a first end, a second end electrically connected to the first negative resistive transistor 21, and a first end of the third transistor 323 to receive the first input current and the difference a second end of the negative phase of the intermediate frequency current and a control terminal receiving the positive phase of the differential oscillating voltage. The second mixing transistor 332 has a first end, a second end electrically connected to the second end of the first mixing transistor 331, and a control end receiving the negative phase of the differential oscillating voltage. The third mixing transistor 333 has a first end, a second end electrically connected to the second negative resistive transistor 22, and a first end of the fourth transistor 324 to receive the second input current and the difference A second end of the positive phase of the intermediate frequency current and a control terminal electrically coupled to the control terminal of the second mixing transistor 332. The fourth mixing transistor 334 has a first end, a second end electrically connected to the second end of the third mixing transistor 333, and a control end electrically connected to the control end of the first mixing transistor 331 . The first ends of the first and third mixing transistors 331, 333 are connected and provide a negative phase of the differential RF current, and the first of the second and fourth mixing transistors 332, 334 The terminals are connected and provide the positive phase of the differential RF current.
該負載器4電連接該混頻器3以接收該差動射頻電流，並根據該差動射頻電流與一阻抗值來產生一具有正、負相之第一差動射頻電壓，且該負載器4具有一第一及第二電感41、42。 The loader 4 is electrically connected to the mixer 3 to receive the differential RF current, and generates a first differential RF voltage having positive and negative phases according to the differential RF current and an impedance value, and the loader 4 has a first and second inductance 41, 42.
該第一電感41具有一接收該直流偏壓VDD的第一端，及一電連接該第一及第三混頻電晶體331、333之第一端以接收該差動射頻電流之負相的第二端。該第二電感42具有一接收該直流偏壓VDD的第一端，及一電連接該第二及第四混頻電晶體332、334之第一端以接收該差動射頻電流之正相的第二端。其中，該阻抗值相關於該第一及第二電感41、42的阻值，該負載器4根據該阻抗值及該差動射頻電流於該第一及第二電感41、42的第二端分別產生該第一差動射頻電壓的正、負相。 The first inductor 41 has a first end receiving the DC bias voltage V DD and a first end electrically connected to the first and third mixing transistors 331, 333 to receive the negative phase of the differential RF current The second end. The second inductor 42 has a first end receiving the DC bias voltage V DD and a first end electrically connected to the second and fourth mixing transistors 332, 334 to receive the positive phase of the differential RF current The second end. The impedance value is related to the resistance values of the first and second inductors 41 and 42. The loader 4 is based on the impedance value and the differential RF current at the second ends of the first and second inductors 41 and 42. Positive and negative phases of the first differential RF voltage are generated, respectively.
該信號放大器5電連接該負載器4及該電流源31以接收來自該負載器4之該第一差動射頻電壓，並據以將該第一差動射頻電壓進行增益放大，來產生一具有正、負相的第二差動射頻電壓，且該第二差動射頻電壓相對於該差動中頻電壓的比值實質上為一轉換增益，且該信號放大器5具有一第一至第四放大電晶體51~54，及一第一及第二放大電阻55、56。 The signal amplifier 5 is electrically connected to the loader 4 and the current source 31 to receive the first differential RF voltage from the loader 4, and according to the gain amplification of the first differential RF voltage, to generate a a second differential RF voltage of the positive and negative phases, and a ratio of the second differential RF voltage to the differential intermediate frequency voltage is substantially a conversion gain, and the signal amplifier 5 has a first to fourth amplification The transistors 51 to 54 and a first and second amplification resistors 55 and 56.
該第一放大電晶體51具有一第一端、一提供該第二差動射頻電壓之正相的第二端，及一接收該第一差動射頻電壓之負相的控制端。該第二放大電晶體52具有一第 一端、一提供該第二差動射頻電壓之負相的第二端，及一接收該第一差動射頻電壓之正相的控制端。該第三放大電晶體53具有一電連接該第一放大電晶體51之第二端的第一端、一第二端，及一電連接該電流源31的控制端。該第四放大電晶體54具有一電連接該第二放大電晶體52之第二端的第一端、一第二端，及一電連接該第三放大電晶體53之控制端的控制端。該第一及第二放大電阻55、56分別具有一電連接各自所對應之該第三及第四放大電晶體53、54之第二端的第一端，及一接地的第二端。其中，該第三放大電晶體53與該第一放大電阻55的跨壓作為該第二差動射頻電壓之正相，該第四放大電晶體54與該第二放大電阻56的跨壓作為該第二差動射頻電壓之負相。 The first amplifying transistor 51 has a first end, a second end providing a positive phase of the second differential RF voltage, and a control end receiving the negative phase of the first differential RF voltage. The second amplifying transistor 52 has a first One end, a second end providing a negative phase of the second differential RF voltage, and a control end receiving a positive phase of the first differential RF voltage. The third amplifying transistor 53 has a first end electrically connected to the second end of the first amplifying transistor 51, a second end, and a control end electrically connected to the current source 31. The fourth amplifying transistor 54 has a first end electrically connected to the second end of the second amplifying transistor 52, a second end, and a control end electrically connected to the control end of the third amplifying transistor 53. The first and second amplifying resistors 55, 56 respectively have a first end electrically connected to the second ends of the third and fourth amplifying transistors 53, 54 respectively, and a grounded second end. The voltage across the third amplifying transistor 53 and the first amplifying resistor 55 is the positive phase of the second differential RF voltage, and the voltage across the fourth amplifying transistor 54 and the second amplifying resistor 56 is used as the The negative phase of the second differential RF voltage.
該差動轉單端器6電連接該信號放大器5以接收該第二差動射頻電壓，並將該第二差動射頻電壓轉換成一呈單端輸出形式的單端射頻電壓。 The differential to single-ended unit 6 is electrically coupled to the signal amplifier 5 to receive the second differential RF voltage and convert the second differential RF voltage into a single-ended RF voltage in the form of a single-ended output.
於本較佳實施例中，該等電感325、326、41、42皆為傳輸線電感，且該電晶體312、該第一至第四電晶體321~324、該第一及第二補償電晶體70、71、該第一至第四混頻電晶體331~334，及該第一至第四放大電晶體51~54中的每一者是一N型金氧半場效電晶體，且第一端是汲極，第二端是源極，控制端是閘極，該第一及第二負阻電晶體21、22中的每一者是一P型金氧半場效電晶體，且第一端是源極，第二端是汲極，控制端是閘極。 In the preferred embodiment, the inductors 325, 326, 41, and 42 are transmission line inductances, and the transistor 312, the first to fourth transistors 321 to 324, and the first and second compensation transistors are 70, 71, the first to fourth mixing transistors 331 to 334, and each of the first to fourth amplifying transistors 51 to 54 are an N-type MOS field-effect transistor, and the first The end is a drain, the second end is a source, the control end is a gate, and each of the first and second negative resistive transistors 21, 22 is a P-type MOS half-field effect transistor, and the first The terminal is the source, the second terminal is the drain, and the control terminal is the gate.
以下進一步說明該平衡式升頻混頻電路的運作 方式。 The operation of the balanced up-conversion mixing circuit is further explained below. the way.
當該差動振盪電壓使該第一及第四混頻電晶體331、334導通時，該第二及第三混頻電晶體332、333不導通，而當該差動振盪電壓使該第二及第三混頻電晶體332、333導通時，該第一及第四混頻電晶體331、334不導通。 When the differential oscillating voltage turns on the first and fourth mixing transistors 331, 334, the second and third mixing transistors 332, 333 are not turned on, and when the differential oscillating voltage makes the second When the third mixing transistors 332 and 333 are turned on, the first and fourth mixing transistors 331, 334 are not turned on.
於交流分析時，藉由利用負電阻補償效果，導致轉導級之等效轉導最大化，有效提升轉換增益。 In the AC analysis, by using the negative resistance compensation effect, the equivalent transduction of the transconductance stage is maximized, and the conversion gain is effectively improved.
參閱圖2，舉例來說，該第一及第二負阻電晶體21、22的第一端所提供的一輸出電流I1如示(1)：
其中，參數Gms,LO是該第一混頻電晶體331或該第三混頻電晶體333的第二端的一等效輸入阻抗的倒數，參數gm21,22是該第一及第二負阻電晶體21、22的轉導值，參數gm321,322是該第一及第二電晶體321、322的轉導值，參數VIF是該差動中頻電壓。 The parameter G ms, LO is the reciprocal of an equivalent input impedance of the second end of the first mixing transistor 331 or the third mixing transistor 333, and the parameters g m21, 22 are the first and second negative The transconductance values of the resistive crystals 21, 22, the parameters g m321, 322 are the transconductance values of the first and second transistors 321, 322, and the parameter V IF is the differential intermediate frequency voltage.
由該輸出電流I1的公式得知，當該第一及第二負阻電晶體21、22的轉導值gm21,22(在不大Gms,LO之情況下)越大時，該輸出電流I1越大，又該平衡式升頻混頻電路的轉換增益的大小正比於該輸出電流I1，導致該平衡式升頻混頻電路的轉換增益提升。 According to the formula of the output current I1, when the transconductance values g m21, 22 (in the case of not much G ms, LO ) of the first and second negative-resistance transistors 21, 22 are larger, the output is larger. The larger the current I1 is, the larger the conversion gain of the balanced up-conversion mixing circuit is proportional to the output current I1, resulting in an increase in the conversion gain of the balanced up-conversion mixing circuit.
於直流分析時，藉由利用該負阻提升器2所提 供之該第一及第二輸入電流的注入效果，降低流經該第一至第四混頻電晶體331~334之第一端所需的電流，導致該第一至第四混頻電晶體331~334之輸入路徑的功率損耗降低。 In the case of DC analysis, by using the negative resistance riser 2 Injecting the first and second input currents to reduce the current required to flow through the first ends of the first to fourth mixing transistors 331-334, resulting in the first to fourth mixing transistors The power loss of the input path of 331~334 is reduced.
需注意的是，圖1為本發明之平衡式升頻混頻電路的較佳實施例，但不限於此。 It should be noted that FIG. 1 is a preferred embodiment of the balanced up-conversion mixing circuit of the present invention, but is not limited thereto.
舉例來說，圖3為該較佳實施例之一變形，其與該較佳實施例相似，二者不同之處在於：此實施例省略了該較佳實施例中的該負阻提升器2(見圖1)，導致該混頻單源33並未根據該第一及第二電流進行混頻。在此實施例中，該較佳實施例之變形藉由利用該增益放大單元32及該信號放大器5同樣也具有較高於習知吉伯特混頻電路的轉換增益。 For example, FIG. 3 is a modification of the preferred embodiment, which is similar to the preferred embodiment. The difference between the two is that the negative resistance riser 2 of the preferred embodiment is omitted in this embodiment. (See Fig. 1), causing the mixing single source 33 not to be mixed according to the first and second currents. In this embodiment, the variant of the preferred embodiment also has a higher conversion gain than the conventional Gilbert mixer circuit by using the gain amplifying unit 32 and the signal amplifier 5.
參閱圖4，是該較佳實施例、該較佳實施例之變形，及習知吉伯特混頻電路的轉換增益對頻率變化的比較圖。圖3顯示該較佳實施例的轉換增益明顯大於該較佳實施例之變形的轉換增益，且該較佳實施例之變形的轉換增益又明顯大於該吉伯特混頻電路的轉換增益，驗證該負阻提升器2、該負阻補償器329、該第一至第四電晶體321~324，及該信號放大器5確實具有提升轉換增益的功效。 Referring to Figure 4, there is shown a comparison of the preferred embodiment, variations of the preferred embodiment, and the conversion gain versus frequency variation of a conventional Gilbert mixer circuit. 3 shows that the conversion gain of the preferred embodiment is significantly greater than the distortion of the preferred embodiment, and the converted conversion gain of the preferred embodiment is significantly greater than the conversion gain of the Gilbert mixer circuit. The negative resistance riser 2, the negative resistance compensator 329, the first to fourth transistors 321 to 324, and the signal amplifier 5 do have the effect of increasing the conversion gain.
綜上所述，上述實施例具有以下優點： In summary, the above embodiment has the following advantages:
1.該平衡式升頻混頻電路的轉換增益較高。利用連接方式呈疊接架構的第一至第四電晶體321~324，可 無需額外增加功耗，即能提升該平衡式升頻混頻電路的轉換增益，可有效的解決先前技術所遭遇的問題。又無論是負阻提升器2或該負阻補償器329皆能進行負電阻補償，使該平衡式升頻混頻電路之等效轉導最大化，也可在不增加功耗同時有助其轉換增益的增加。加上信號放大器5更可進一步提升其轉換增益。 1. The balanced up-conversion mixing circuit has a high conversion gain. The first to fourth transistors 321 to 324 of the stacked structure are connected by a connection method, The conversion gain of the balanced up-conversion mixing circuit can be improved without additional power consumption, and the problems encountered in the prior art can be effectively solved. Whether the negative resistance riser 2 or the negative resistance compensator 329 can perform negative resistance compensation, the equivalent transduction of the balanced up-conversion mixing circuit can be maximized, and the power consumption can be improved without increasing power consumption. The increase in conversion gain. Plus the signal amplifier 5 can further increase its conversion gain.
2.降低功率損耗。藉由利用該負阻提升器2所提供的該等輸入電流來達到電流注入效果，同時降低流經該第一至第四混頻電晶體之第一端的電流，導致該平衡式升頻混頻電路的功率損耗降低。 2. Reduce power loss. The current injection effect is achieved by using the input currents provided by the negative resistance riser 2, while reducing the current flowing through the first ends of the first to fourth mixing transistors, resulting in the balanced up-mixing The power loss of the frequency circuit is reduced.
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。 The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and patent specification content of the present invention, All remain within the scope of the invention patent.
1‧‧‧單端轉差動器 1‧‧‧ single-ended rotary differential
2‧‧‧負阻提升器 2‧‧‧Negative resistance riser
21‧‧‧第一負阻電晶體 21‧‧‧First negative resistance transistor
22‧‧‧第二負阻電晶體 22‧‧‧Second negative resistance transistor
3‧‧‧混頻器 3‧‧‧ Mixer
31‧‧‧電流源 31‧‧‧current source
311‧‧‧電阻 311‧‧‧resistance
312‧‧‧電晶體 312‧‧‧Optoelectronics
32‧‧‧增益放大單元 32‧‧‧ Gain amplification unit
321‧‧‧第一電晶體 321‧‧‧First transistor
322‧‧‧第二電晶體 322‧‧‧Second transistor
323‧‧‧第三電晶體 323‧‧‧ Third transistor
324‧‧‧第四電晶體 324‧‧‧4th transistor
325‧‧‧第一電感 325‧‧‧First inductance
326‧‧‧第二電感 326‧‧‧second inductance
327‧‧‧第一電阻 327‧‧‧First resistance
328‧‧‧第二電阻 328‧‧‧second resistance
329‧‧‧負阻補償器 329‧‧‧Negative resistance compensator
70‧‧‧第一補償電晶體 70‧‧‧First compensation transistor
71‧‧‧第二補償電晶體 71‧‧‧Second compensation transistor
33‧‧‧混頻單元 33‧‧‧mixing unit
331‧‧‧第一混頻電晶體 331‧‧‧First Mixing Transistor
332‧‧‧第二混頻電晶體 332‧‧‧Second mixing transistor
333‧‧‧第三混頻電晶體 333‧‧‧third mixing transistor
334‧‧‧第四混頻電晶體 334‧‧‧fourth mixing transistor
4‧‧‧負載器 4‧‧‧Loader
41‧‧‧第一電感 41‧‧‧First inductance
42‧‧‧第二電感 42‧‧‧second inductance
5‧‧‧信號放大器 5‧‧‧Signal Amplifier
51‧‧‧第一放大電晶體 51‧‧‧First magnifying transistor
52‧‧‧第二放大電晶體 52‧‧‧Second amplified transistor
53‧‧‧第三放大電晶體 53‧‧‧ Third amplified transistor
54‧‧‧第四放大電晶體 54‧‧‧ fourth magnifying transistor
55‧‧‧第一放大電阻 55‧‧‧First amplification resistor
56‧‧‧第二放大電阻 56‧‧‧second amplification resistor
6‧‧‧差動轉單端器 6‧‧‧Differential to single-ended
VDD‧‧‧直流偏壓 VDD‧‧‧DC bias
VG1‧‧‧第一偏壓 VG1‧‧‧First bias
VG2‧‧‧第二偏壓 VG2‧‧‧second bias
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103100375A TWI558097B (en) | 2014-01-06 | 2014-01-06 | Balanced up - frequency mixing circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103100375A TWI558097B (en) | 2014-01-06 | 2014-01-06 | Balanced up - frequency mixing circuit |
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|---|---|
| TW201528680A TW201528680A (en) | 2015-07-16 |
| TWI558097B true TWI558097B (en) | 2016-11-11 |
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| TW103100375A TWI558097B (en) | 2014-01-06 | 2014-01-06 | Balanced up - frequency mixing circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW201714401A (en) * | 2015-10-15 | 2017-04-16 | Nat Chi Nan Univ | Balanced up-conversion mixer comprising a single-ended to differential circuit, a negative resistance compensation circuit, a load circuit, and a frequency mixing circuit to increase conversion gain and power consumption |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6275688B1 (en) * | 1998-04-22 | 2001-08-14 | Fujitsu Limited | Double balanced mixer |
| US7142014B1 (en) * | 2004-11-16 | 2006-11-28 | Xilinx, Inc. | High frequency XOR with peaked load stage |
| US20080042726A1 (en) * | 2006-06-20 | 2008-02-21 | Stmicroelectronics Sa | Mixer amplifier and radiofrequency front-end circuit |
-
2014
- 2014-01-06 TW TW103100375A patent/TWI558097B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6275688B1 (en) * | 1998-04-22 | 2001-08-14 | Fujitsu Limited | Double balanced mixer |
| US7142014B1 (en) * | 2004-11-16 | 2006-11-28 | Xilinx, Inc. | High frequency XOR with peaked load stage |
| US20080042726A1 (en) * | 2006-06-20 | 2008-02-21 | Stmicroelectronics Sa | Mixer amplifier and radiofrequency front-end circuit |
Non-Patent Citations (3)
| Title |
|---|
| A. Y. K. Chen, Y. Baeyens, Y. K. Chen and J. Lin, "An 80 GHz High Gain Double-Balanced Active Up-Conversion Mixer Using 0.18 \mu{\rm m} SiGe BiCMOS Technology," in IEEE Microwave and Wireless Components Letters, vol. 21, no. 6, pp. 326-328, June 2011. * |
| F. Eshghabadi, M. Dousti, F. Temcamani, B. Delacressoniere and J. L. Gautier, "A 2.4-GHz Front-end System Design for WLAN Applications using 0.35μm SiGe BiCMOS Technology," Information and Communication Technologies: From Theory to Applications, 2008. ICTTA 2008. 3rd International Conference on, Damascus, 2008, pp. 1-5. * |
| Y. S. Lin, C. C. Wang, T. M. Tsai and W. C. Wen, "A low power and high conversion gain 60-GHz CMOS up-conversion mixer using current injection and dual negative resistance compensation techniques," Electromagnetic Compatibility (EMC), 2013 IEEE International Symposium on, Denver, CO, 2013, pp. 97-100. * |
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| Publication number | Publication date |
|---|---|
| TW201528680A (en) | 2015-07-16 |
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