TWI555024B - Memory device and data erasing method thereof - Google Patents

Description

Memory device and data erasing method thereof 【0001】

The invention relates to a memory device and a data erasing method thereof.

【0002】

NAND flash memory has been widely used in various devices such as mobile phones, personal computers, notebook computers, tablets, and the like. A typical erasing mechanism for NAND flash memory is usually in units of memory blocks. In other words, even if the user only needs to erase a small number of pages, all the data pages in the memory block need to be erased. Therefore, before performing block erase, the typical erase mechanism needs to write the remaining page data in the memory block to another memory block, and all the data pages in the memory block are erased. After that, the remaining page data is written back to the original memory block. However, this practice takes a lot of time in the garbage collection and the wear leveling of the memory.

[0003]

The present invention relates to a memory device and a data erasing method thereof.

[0004]

According to an aspect of the invention, a memory device is proposed. The memory device includes a first memory cell string and a second memory cell string. The first memory cell string is coupled to a first bit line and a plurality of word lines. The second memory cell string is coupled to a second bit line and the word lines. When the word lines are applied with a erase voltage, the first bit line is applied with a first voltage to erase the data stored on the first memory string, and the second bit line is applied with a second The voltage causes the second memory cell string to be set to float.

[0005]

According to another aspect of the invention, a memory device is presented. The memory device includes a plurality of first memory cell strings and a plurality of second memory cell strings. The first memory cell strings are coupled to the plurality of first bit lines. The second memory cell strings are coupled to the plurality of second bit lines. When a voltage is applied to the first memory cell string and the second memory cell string through the plurality of word lines, the first bit lines are applied with a first voltage to be erased and stored in the first The data on the memory string, the second bit lines are applied with a second voltage, so that the second memory cell strings are set to be floating.

[0006]

According to the present invention, a data erasing method for a memory device is provided, wherein the memory device includes a first memory cell coupled to a first bit line and a second memory cell coupled to a first Two bit line. The data erasing method includes the steps of: applying a wipe voltage to the first memory cell string and the second memory cell string through a plurality of word lines; applying a first voltage to the first bit line to erase Data stored on the first memory cell string; and applying a second voltage to the second bit line such that the second memory cell string is set to be floating.

【0007】

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0029]

100, 300‧‧‧ memory devices
102(1)-102(M), 302(1)-302(K), 302(K+1)-302(M), 502, 502', 602, 602'‧‧‧ memory strings
104(1)-104(M), 304(1)-304(K), 304(K+1)-304(M)‧‧‧ string selection transistor
SSL, SSL(1)-SSL(M), SSL(1)'-SSL(K)', SSL(K+1)'-SSL (M)'‧‧‧ string selection line
106(1)-106(M), 306(1)-306(K), 306(K+1)-306(M)‧‧‧ Ground Selective Crystal
202, 204, 206‧‧‧ steps
GSL‧‧‧ Grounding selection line
CSL‧‧‧Common source line
BL(1)-BL(M), BL(1)'-BL(K)', BL(K+1)'-BL(M)'‧‧‧ bit line
BL(sel)‧‧‧Selecting location line
BL (unsel) ‧ ‧ non-selected positioning line
WL, WL(1)-WL(N), WL(1)'-WL(N)'‧‧‧ character line
MC‧‧‧ memory cell
EV‧‧‧ erase voltage
V1‧‧‧ first voltage
V2‧‧‧second voltage
CV‧‧‧Common voltage
Vdd‧‧‧ voltage
The first period of T1‧‧
Second period of T2‧‧
R1‧‧‧ first area
R2‧‧‧ second area

[0008]

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.
2 is a flow chart of a data erasing method of a memory device according to one embodiment of the present invention.
FIG. 3A illustrates an exemplary bias configuration of a plurality of selected memory cell strings of the memory device.
FIG. 3B illustrates an exemplary bias configuration of a plurality of unselected memory cell strings of the memory device.
Figure 4 is a diagram showing an exemplary waveform of an erase mechanism in accordance with an embodiment of the present invention.
Figure 5 illustrates an exemplary memory cell string packet configuration in accordance with an embodiment of the present invention.
FIG. 6 is a schematic diagram showing a memory cell string grouping configuration according to another embodiment of the present invention.

【0009】

The following is a detailed description of the embodiments, which are intended to be illustrative only and not to limit the scope of the disclosure. In addition, the drawings in the embodiments omit unnecessary elements to clearly show the technical features of the disclosure.

[0010]

1 is a schematic diagram of a memory device 100 in accordance with an embodiment of the present invention. The memory device 100 includes a plurality of memory cell strings 102(1)-102(M). The memory strings 102(1)-102(M) are coupled to the bit lines BL(1)-BL(M) and coupled to the plurality of word lines WL(1)-WL(N). The intersection of the memory strings 102(1)-102(M) and the word lines WL(1)-WL(N) defines a plurality of memory cells MC for storing data. The memory device 100 can be a three-dimensional NAND flash memory, a 2-dimensional NAND flash memory, a NOR flash memory, or a One Time Program (OTP) memory. In one embodiment, the memory strings 102(1)-102(M) belong to a same memory block in the memory device 100.

[0011]

Each memory cell string 102(i) includes a string of selection transistors 104(i), where i = 1, 2, ..., M. The first end and the second end of each string selection transistor 104(i) are respectively coupled to a corresponding string selection line SSL(i) and a corresponding bit line BL(i).

[0012]

Each memory cell string 102(i) further includes a ground selection transistor 106(i). The first end and the second end of each of the ground selection transistors 106(i) are respectively coupled to a ground selection line GSL and a common source line CSL. In one embodiment, the ground selection transistors 106(1)-106(M) are all coupled to the same ground selection line GSL and the same common source line CSL.

[0013]

2 is a flow chart of a data erasing method of the memory device 100 in accordance with one embodiment of the present invention. At step 202, the erase voltage EV is applied through the word lines WL(1)-WL(N) to the memory cell strings 102(1)-102(M). At step 204, the first voltage V1 is applied to the selected bit line to erase the data stored on the corresponding selected cell string. At step 206, a second voltage V2 is applied to the unselected location line such that the corresponding non-selected memory cell string is set to float.

[0014]

It is assumed that the memory cell string 102(1) is a selected memory cell string, and the memory cell string 102(2) is a non-selected memory cell string. For the selected memory cell string 102(1), when the erase voltage EV (eg, -10 volts) is applied to the word lines WL(1)-WL(N) and the first voltage V1 is applied to the corresponding bit line BL(1), string select transistor 104(1) can generate a gate-induced drain-leakage (Gate-Induced Drain Leakage) current. Next, the channel voltage of the memory string 102(1) will be charged to about the first voltage V1, and the data on the memory string 102(1) will be erased. In an embodiment, the voltage of the string select line SSL(1) (eg, 2 to 3.3 volts) is less than the first voltage V1 (eg, 8 volts).

[0015]

For the unselected memory cell string 102(2), when the erase voltage EV (eg, -10 volts) is applied to the word lines WL(1)-WL(N) and the second voltage V2 is applied to the corresponding bit cell Line BL(2), string selection transistor 104(2) is turned off. Next, the unselected memory cell string 102(2) is floated and does not induce a GIDL current.

[0016]

In an embodiment, the voltage of the string select line SSL(2) is equal to the second voltage V2 (eg, 2 to 3.3 volts). In another embodiment, the voltage of the string selection line SSL(2) may be less than the second voltage V2, but the voltage difference between the voltage of the string selection line SSL(2) and the second voltage V2 is insufficient to make the string selection transistor 104(2) generates a GIDL current.

[0017]

In the example of FIG. 1, the selected memory cell string 102(1) is coupled to the unselected memory cell string 102(2) to the same ground select line GSL and common source line CSL. When the erase voltage EV is applied to the word lines WL(1)-WL(N), the ground selection transistor 106(1) of the selected memory cell string 102(1) is grounded to the unselected memory cell string 102(2). The selection transistor 106(2) will be turned off. In one embodiment, the voltage of the common source line CSL is the same as the voltage of the ground select line GSL.

[0018]

Therefore, in one embodiment, the GIDL current is generated at one end of the selected memory string (SSL end), and neither the two ends of the selected memory string (the SSL end and the GSL end) generate GIDL current.

[0019]

FIG. 3A illustrates an exemplary bias configuration of a plurality of selected memory cell strings 302(1)-302(K) of memory device 300. In the example of Fig. 3A, during data erasing, the erase voltage EV is applied to the memory cell strings 302(1)-302(K) through the word lines WL(1)'-WL(N)'. The bit line BL(1)'-BL(K)' is applied with the first voltage V1. The string select line SSL(1)'-SSL(K)', the ground select GSL coupled to the ground select transistors 306(1)-306(K), and the common source line CSL are all biased to a voltage Vdd (eg, 2 to 3.3 volts). Since the high voltage difference between the gate terminal and the 汲 terminal of the string selection transistor 304(1)-304(K), the SSL terminal of the memory cell string 302(1)-302(K) can generate a GIDL current, so that it is stored in The data of the memory cell string 302(1)-302(K) is erased.

[0020]

FIG. 3B illustrates an exemplary bias configuration of a plurality of unselected memory cell strings 302(K+1)-302(M) of memory device 300. The unselected memory cell strings 302(K+1)-302(M) and the memory cell strings 302(1)-302(K) of FIG. 3A belong to the same memory block, for example. During data erasing, the erase voltage EV is applied to the memory block through the word line WL(1)'-WL(N)'. Bit line BL(K+1)'-BL(M)', string selection line SSL(K+1)'-SSL (M) coupled to string selection transistor 304(K+1)-304(M) The grounding selection GSL and the common source line CSL of the ground selection transistor 306(K+1)-306(M) are applied with the same voltage Vdd, which is applied to the bit line BL (K+1). The voltage Vdd of '-BL(M)' can be regarded as the aforementioned second voltage V2. Similar to the self-boosting in the stylized program, the ground selection transistors 306(K+1)-306(M) are turned off and do not induce GIDL current. At this time, the memory cell string 302(K+1)-302(M) is floating, and the channel voltage of the memory cell string 302(K+1)-302(M) is determined by the coupling amount of the erase voltage EV. . Assume that the coupling coefficient of the erase voltage EV is Cr and the initial channel voltage of the memory cell string 302(K+1)-302(M) is Vini, and the channel voltage of the memory cell string 302(K+1)-302(M) can be Expressed as follows

[0021]

Vini+EV*Cr

[0022]

If the initial channel voltage Vini is 1.8 volts (Vdd-0.7 volts), the erase voltage EV is -10 volts, and the coupling coefficient Cr is 0.9, the channel voltage of the memory cell string 302(K+1)-302(M) can be obtained. It is about -6.2 volts. Since the voltage difference between the channel of the memory cell string 302(K+1)-302(M) and the word line WL(1)'-WL(N)' is very small (10-6.2=3.8 volts), it is stored in The data on the memory string 302(K+1)-302(M) will not be erased.

[0023]

Figure 4 is a diagram showing an exemplary waveform of an erase mechanism in accordance with an embodiment of the present invention. As shown in FIG. 4, in the first period T1, the string selection line SSL, the ground selection line GSL, the common source line CSL, and the unselected positioning element line BL (unsel) are applied with the second voltage V2 (for example, 2 to 3.3). Volt). The corresponding selected bit line BL(sel) is biased to a first voltage V1 (e.g., 8 volts) for the memory cell selected to be erased by the data.

[0024]

In the second period T2, the erase voltage EV (for example, -10 volts) is applied to the word line WL. For the selected memory cell string, the data in the memory cell is erased due to the GIDL current relationship. For a non-selected memory cell string, the memory cell channel is floating, and the channel voltage is determined by the strong coupling amount of the erase voltage EV. Therefore, even if the erase voltage EV is applied to the word line WL, the data stored on the unselected memory cell string is not erased.

[0025]

Figure 5 illustrates an exemplary memory cell string packet configuration in accordance with an embodiment of the present invention. In the example of Fig. 5, the memory cell string 502 and the memory cell string 502' are staggered. The odd bit lines connected to the memory cell string 502 and the even bit line lines connected to the memory cell string 502' are grouped separately. As described above, for the selected group of memory cells, the corresponding bit line can be applied with the first voltage V1 for data erasing; for the unselected group of memory cells, the corresponding bit line can be applied. The second voltage V2 is set to float by setting a non-selected memory cell string.

[0026]

FIG. 6 is a schematic diagram showing a memory cell string grouping configuration according to another embodiment of the present invention. As shown in Fig. 6, the memory cell string 602 and the memory cell string 602' are located in a first region R1 and a second region R2, respectively. The first region R1 is adjacent to the second region R2, for example. The bit lines connected to the memory cell string 602 and the bit line lines connected to the memory cell string 602' are grouped separately. As described above, for the selected group of memory cells, the corresponding bit line can be applied with the first voltage V1 for data erasing; for the unselected group of memory cells, the corresponding bit line can be applied. The second voltage V2 is set to float by setting a non-selected memory cell string. However, the present invention is not limited to the above examples, and bit lines can be grouped into selected groups or non-selected groups in any manner.

[0027]

In summary, the memory device and the data erasing method of the embodiment of the present invention divide the bit lines in the memory block into two groups: a selected group and a non-selected group. For the selected group, a first voltage is applied to the selected location line for data erasure. For non-selected groups, a second voltage is applied to the unselected location lines to set it to float, and data for unselected memory strings is prevented from being erased. Therefore, the memory device and the data erasing method thereof according to the embodiments of the present invention can save memory recovery and the average erase time of the memory, and improve the product specifications of the erase operation.

[0028]

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

202, 204, 206‧‧‧ steps

Claims (10)

[Item 1] A memory device comprising:
a first memory cell string coupled to a first bit line and a plurality of word line lines; and a second memory cell string coupled to a second bit line and the word line lines; The word lines are applied with a wipe voltage, the first bit line is applied with a first voltage to erase the data stored on the first memory cell string, and the second bit line is applied with a second voltage. The second memory cell string is set to float. [Item 2] The memory device of claim 1, wherein the first memory cell string comprises a first string selection transistor, the first string selection transistor is coupled to the first bit line, the second The memory cell string includes a second string selection transistor, and the second string selection transistor is coupled to the second bit line, wherein
When the erase voltage is applied to the word lines, the first string selection transistor generates a gate-induced drain-leakage current, and the second string selection transistor is turned off. [Item 3] The memory device of claim 1, wherein when the erase voltage is applied to the word lines, a channel voltage of the second memory cell is determined by a coupling amount of the erase voltage. [Item 4] The memory device of claim 1, wherein the first memory cell string and the second memory cell string belong to a memory block, and the erase voltage is applied to the memory cell through the word line. Memory block. [Item 5] A memory device comprising:
a plurality of first memory cell strings coupled to the plurality of first bit lines; and a plurality of second memory cell strings coupled to the plurality of second bit lines; wherein when a voltage is erased through the plurality of word lines Applied to the first memory cell string and the second memory cell strings, the first bit lines are applied with a first voltage to erase data stored on the first memory cell strings, the The second bit line is applied with a second voltage such that the second memory cell strings are set to float. [Item 6] The memory device of claim 5, wherein each of the first memory cell strings comprises a first string selection transistor, the first string selection transistor being coupled to a corresponding first bit line, Each of the second memory cell strings includes a second string selection transistor coupled to a corresponding second bit line, wherein
When the erase voltages are applied to the word lines, the first string selection transistors generate gate-induced Drain Leakage currents, and the second string selection transistors are turned off. [Item 7] The memory device of claim 5, wherein when the erase voltage is applied to the word lines, the channel voltage of each of the second memory cells is determined by a coupling amount of the erase voltage. [Item 8] The memory device of claim 5, wherein the first memory cell string and the second memory cell string belong to a memory block, and the erase voltage is applied through the word lines. To the memory block. [Item 9] The memory device of claim 5, wherein the first memory cell strings and the second memory cell strings are staggered. [Item 10] The memory device of claim 5, wherein the first memory cell string and the second memory cells are respectively located in a first area and a second area, and the first area is adjacent to the second area. .