TWI551361B - Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and ic-substrates and the products prepared therefrom - Google Patents

Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and ic-substrates and the products prepared therefrom Download PDF

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TWI551361B
TWI551361B TW100148422A TW100148422A TWI551361B TW I551361 B TWI551361 B TW I551361B TW 100148422 A TW100148422 A TW 100148422A TW 100148422 A TW100148422 A TW 100148422A TW I551361 B TWI551361 B TW I551361B
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palladium
layer
copper
wire bonding
alloy
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TW201244836A (en
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莫斯塔法 奧茲科奇
古史塔維 雷莫斯
亞德 奇連
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德國艾托特克公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]

Description

獲得用於在印刷電路板及積體電路基材上之銅打線接合之鈀表面處理之方法及由其製備之製品 Method for obtaining palladium surface treatment for copper wire bonding on printed circuit boards and integrated circuit substrates, and articles prepared therefrom

本發明係關於銅打線接合於基材,特別是印刷電路板及積體電路基材的方法,該印刷電路板及該積體電路基材具有包含銅接合部分及鈀或鈀合金層之層總成及其中銅打線接合於上述層總成之基材。The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an integrated circuit substrate, the printed circuit board and the integrated circuit substrate having a layer comprising a copper joint portion and a palladium or palladium alloy layer. The copper wire is bonded to the substrate of the above layer assembly.

在印刷電路板(PCB)及積體電路(IC)基材製造中,需要使電子組件接合於在基材之一側或兩側上產生之銅結構之所選接合區域(作為接合部分之接合墊)。該互連就接合強度而言必須可靠,亦即施加於接合互連之熱應力決不應引起此互連損壞。In the manufacture of printed circuit board (PCB) and integrated circuit (IC) substrates, it is desirable to bond the electronic component to a selected bond area of the copper structure produced on one or both sides of the substrate (as a joint of the joint) pad). The interconnect must be reliable in terms of bond strength, i.e., the thermal stress applied to the bond interconnect should never cause damage to the interconnect.

導線接合為積體電路封裝中晶片連接至積體電路基材之一種較佳方法且其在商業積體電路生產中佔70%以上。當前用於積體電路基材之主要打線接合方法為金打線接合,其中金打線接合於電解沈積之鎳及金層上。或者,金打線接合於鎳、鈀及金之表面上(ENEPIG)。在所有情況下,銅打線接合於最終金層上。最近,積體電路基材工業中已引入銅打線接合技術作為金打線接合之替代方法。當前銅打線接合標準為使用接合於層序列上之銅線接合物,該層序列係由沈積於基材之銅打線接合部分上之第一電解鎳層及第二金層組成。Wire bonding is a preferred method of connecting a wafer to an integrated circuit substrate in an integrated circuit package and it accounts for more than 70% of commercial integrated circuit production. The main wire bonding method currently used for integrated circuit substrates is gold wire bonding, in which gold wires are bonded to the electrolytically deposited nickel and gold layers. Alternatively, the gold wire is bonded to the surface of nickel, palladium and gold (ENEPIG). In all cases, the copper wire is bonded to the final gold layer. Recently, copper wire bonding technology has been introduced as an alternative to gold wire bonding in the integrated circuit substrate industry. The current copper bonding standard is to use a copper wire bond bonded to a layer sequence consisting of a first electrolytic nickel layer and a second gold layer deposited on the copper wire bonding portion of the substrate.

微電子封裝中打線接合之機械可靠性在很大程度上取決於基材(印刷電路板、PCB或積體電路基材)上之接合楔與接合墊之間界面處金屬間化合物之形成及發展,其為成功接合所必需。The mechanical reliability of wire bonding in microelectronic packages depends to a large extent on the formation and development of intermetallic compounds at the interface between the bonding wedge and the bonding pad on the substrate (printed circuit board, PCB or integrated circuit substrate). , which is necessary for successful bonding.

難以使金或銅打線接合於銅接合墊表面上的主要原因為銅金屬鍍層氧化之趨勢較高。The main reason why it is difficult to bond gold or copper wires to the surface of the copper bond pad is that the copper metal plating layer has a higher tendency to oxidize.

打線接合部分通常由銅製成。若其保持裸露或外部曝露於大氣及濕氣,則銅層之焊接及打線接合性質由於表面氧化或腐蝕而退化。因此,為保持焊接或打線接合性質,裸露或曝露之銅層通常經鎳電鍍或無電極電鍍。電鍍鎳層長期保護銅免受腐蝕性大氣損害。又,鎳層藉由充當擴散障壁層而保護銅以免在焊接組裝步驟期間被焊料溶解。此外,電鍍鎳層起界面膜作用,以防止隨後電鍍之銅層與金層彼此間擴散。隨後,以電解或無電極方式電鍍約0.5 μm厚度之打線接合金,以賦予有助於打線接合製程之性質。該等製程描述於例如US 5,235,139及US 6,733,823中。The wire bonding portion is usually made of copper. If it remains exposed or exposed to the atmosphere and moisture, the soldering and wire bonding properties of the copper layer degrade due to surface oxidation or corrosion. Thus, to maintain soldering or wire bonding properties, the exposed or exposed copper layer is typically nickel plated or electroless plated. The electroplated nickel layer protects copper from corrosive atmospheres for a long time. Also, the nickel layer protects the copper from being dissolved by the solder during the solder assembly step by acting as a diffusion barrier layer. In addition, the electroplated nickel layer functions as an interface film to prevent diffusion of the subsequently plated copper layer and the gold layer from each other. Subsequently, a wire bonding gold of a thickness of about 0.5 μm is electroplated electrolytically or electrodelessly to impart properties that contribute to the wire bonding process. Such processes are described, for example, in US 5,235,139 and US 6,733,823.

US 2007/0104929係關於電鍍印刷電路板之方法,其包含以下步驟:(a)提供具有預定電路圖案之印刷電路板,該印刷電路板具有用於在其上表面安裝半導體之打線接合部分及用於連接外部部件與印刷電路板之焊接部分;(b)在印刷電路板中除打線接合部分及焊接部分以外的其餘部分上形成光致阻焊層(photo solder resist layer);(c)在打線接合部分及焊接部分上形成鈀或鈀合金無電極電鍍層;及(d)將鈀或鈀合金電鍍層浸漬於含有水溶性金化合物之取代型浸漬式金電鍍溶液中,以在鈀或鈀合金電鍍層上形成金或金合金無電極電鍍層。US 2007/0104929 relates to a method of electroplating a printed circuit board comprising the steps of: (a) providing a printed circuit board having a predetermined circuit pattern, the printed circuit board having a wire bonding portion for mounting a semiconductor on an upper surface thereof, and a soldering portion for connecting the external component to the printed circuit board; (b) forming a photo solder resist layer on the printed circuit board except for the wire bonding portion and the soldering portion; (c) bonding the wire Forming a palladium or palladium alloy electroless plating layer on the joint portion and the welded portion; and (d) immersing the palladium or palladium alloy plating layer in a substituted impregnation gold plating solution containing a water-soluble gold compound to palladium or palladium alloy A gold or gold alloy electrodeless plating layer is formed on the plating layer.

US 2006/055023係關於包含疊層及防氧化層之晶片載體。防氧化層為位於接合指墊或其他接點之表面上,使用簡易快速塗膜技術形成之非電解金屬塗層或有機防氧化膜。US 2006/055023 relates to wafer carriers comprising a laminate and an oxidation barrier. The anti-oxidation layer is an electroless metal coating or an organic anti-oxidation film formed on the surface of the bonding finger pad or other contact using a simple rapid film coating technique.

US 5,175,609係關於用於抗腐蝕及抗應力互連多層冶金墊(其包含根據互連冶金學依序沈積之鉻層、鎳層及貴重或相對貴重金屬層)或多層冶金墊(其包含根據互連冶金學依序沈積之鉻層、可溶性貴重金屬層、鎳層及貴重或相對貴重金屬層)之新穎結構及方法。US 5,175,609 relates to a multi-layer metallurgical mat for corrosion and stress resistant interconnection (which comprises a chromium layer, a nickel layer and a precious or relatively precious metal layer deposited sequentially according to interconnect metallurgy) or a multilayer metallurgical mat (which includes A novel structure and method for a chromium layer, a soluble precious metal layer, a nickel layer, and a precious or relatively precious metal layer deposited sequentially by metallurgy.

EP 0 697 805 A1係關於藉由以下步驟製造印刷電路板之方法:提供具有銅電路圖案、孔洞及接合區之電路板;用阻焊遮罩覆蓋電路圖案;及使電路板與無電極電鍍鈀溶液接觸足以提供最終鈀處理層的時間,該最終鈀處理層厚度足以保護孔洞中及接合區上之銅沈積物免於形成氧化物且相對光滑及平坦以提供優良可焊性及優良打線接合能力。通常藉由在電路板上電鍍銅來設置銅電路圖案、孔洞及接合區。接著,鈀層可直接設置於銅上或設置於最初沈積於銅上之無電極電鍍鎳層上。EP 0 697 805 A1 relates to a method for manufacturing a printed circuit board by providing a circuit board having a copper circuit pattern, a hole and a land; covering the circuit pattern with a solder mask; and plating the circuit board with an electrodeless electrode The solution is contacted for a period of time sufficient to provide a final palladium treatment layer that is thick enough to protect the copper deposits in the voids and on the joint from oxide formation and relatively smooth and flat to provide excellent solderability and excellent wire bonding capability. . Copper circuit patterns, holes, and landings are typically provided by electroplating copper on a circuit board. Next, the palladium layer can be placed directly on the copper or on the electrodeless electroplated nickel layer initially deposited on the copper.

因此,本發明之一個目標為提供在具有由銅製成之打線接合部分之基材上沈積的層,該層確保非常可靠地形成打線接合且不含金層。如本文所用之金屬層意謂形成於打線接合部分上之至少一個由鈀或鈀合金製成之金屬層,其適用作銅打線接合表面。Accordingly, it is an object of the present invention to provide a layer deposited on a substrate having a wire bonding portion made of copper which ensures a very reliable formation of wire bonding and no gold layer. A metal layer as used herein means at least one metal layer formed of a palladium or palladium alloy formed on a wire bonding portion, which is suitable for use as a copper wire bonding surface.

本發明之另一目標為提供形成該層、同時在該金屬層上形成穩定打線接合,更特定言之銅打線接合之方法。Another object of the present invention is to provide a method of forming the layer while forming a stable wire bond on the metal layer, more specifically copper wire bonding.

本發明之另一目標為提供積體電路基材,該積體電路基材具有銅結構,其中該銅結構經塗覆金屬層。Another object of the present invention is to provide an integrated circuit substrate having a copper structure, wherein the copper structure is coated with a metal layer.

本發明之另一目標為提供印刷電路板,該印刷電路板具有銅結構,其中該銅結構經塗覆金屬層。Another object of the present invention is to provide a printed circuit board having a copper structure wherein the copper structure is coated with a metal layer.

為實現該等目標,本發明提供金屬層總成,其包含To achieve these objectives, the present invention provides a metal layer assembly comprising

(i)至少一個打線接合部分層,其由銅或銅合金製成;且沈積於其上(i) at least one wire bonding portion layer made of copper or a copper alloy; and deposited thereon

(ii)金屬層,其為鈀或鈀合金層;(ii) a metal layer which is a palladium or palladium alloy layer;

(iii)銅線,其打線接合於鈀或鈀合金層上。(iii) a copper wire bonded to a palladium or palladium alloy layer.

步驟(ii)中沈積之鈀或鈀合金層之厚度為0.01-5.0 μm,較佳為0.05-2.0 μm且更佳為0.1-0.5 μm。The palladium or palladium alloy layer deposited in the step (ii) has a thickness of from 0.01 to 5.0 μm, preferably from 0.05 to 2.0 μm and more preferably from 0.1 to 0.5 μm.

在該方法之較佳實施例中,鈀層由純鈀組成。在另一較佳實施例中,打線接合部分上之層總成不含鎳或鎳合金層,而僅含直接電鍍於打線接合部分上之鈀或鈀合金層。In a preferred embodiment of the method, the palladium layer consists of pure palladium. In another preferred embodiment, the layer assembly on the wire bonding portion does not contain a nickel or nickel alloy layer, but only a palladium or palladium alloy layer directly plated on the wire bonding portion.

鈀係自無電極(自催化)電鍍鈀浴中沈積,該鈀浴包含Palladium is deposited from an electrodeless (autocatalytic) electroplating palladium bath containing

▇鈀離子源;Palladium ion source;

▇錯合劑;▇ wrong mixture;

▇還原劑。▇Reducing agent.

迄今,通常在由銅或銅合金製成之打線接合部分層上電鍍鎳或鎳合金層。該鎳層之厚度通常為0.5-10.0 μm。Heretofore, a nickel or nickel alloy layer is usually electroplated on a wire bonding portion layer made of copper or a copper alloy. The thickness of the nickel layer is usually from 0.5 to 10.0 μm.

本發明之方法中不再需要電鍍鎳或鎳合金層。Electroplating of nickel or nickel alloy layers is no longer required in the process of the invention.

本發明者發現在打線接合部分之銅或銅合金上鍍純鈀層尤其有利。根據一個實施例(其中在電鍍鈀或鈀層之前,由銅或銅合金製成之打線接合部分上未沈積鎳或鎳合金層),純鈀甚至更佳。本發明之純鈀層為鈀含量超過99.0 wt.%,較佳超過99.5 wt.%鈀或更佳超過99.9 wt.%或超過99.99 wt.%鈀之層。The inventors have found that it is particularly advantageous to plate a pure palladium layer on the copper or copper alloy of the wire bonding portion. According to one embodiment (in which a nickel or nickel alloy layer is not deposited on the wire bonding portion made of copper or a copper alloy before plating the palladium or palladium layer), pure palladium is even more preferable. The pure palladium layer of the present invention is a layer having a palladium content of more than 99.0 wt.%, preferably more than 99.5 wt.% palladium or more preferably more than 99.9 wt.% or more than 99.99 wt.% palladium.

在該方法之另一實施例中,鈀電鍍層為合金層,其包含90至99.9 wt.%鈀及0.1至10.0 wt.%磷或硼。In another embodiment of the method, the palladium plating layer is an alloy layer comprising 90 to 99.9 wt.% palladium and 0.1 to 10.0 wt.% phosphorus or boron.

在本發明之較佳實施例中,金屬層僅包含一個鈀或鈀合金層,例如鈀-磷層,其直接形成於基材之銅或銅合金打線接合部分上。In a preferred embodiment of the invention, the metal layer comprises only one palladium or palladium alloy layer, such as a palladium-phosphorus layer, which is formed directly on the copper or copper alloy wire bond portion of the substrate.

通常,藉由預先用酸清潔劑處理且接著於微蝕刻浴中還原表面氧化銅來為接合部分之銅或銅合金表面電鍍作好準備。Typically, the copper or copper alloy surface of the joint portion is prepared by prior treatment with an acid cleaner followed by reduction of the surface copper oxide in a microetch bath.

為達成本發明之目的,可在沈積鈀或鈀合金層之前對銅或銅合金打線接合部分有利地施用另一活化步驟。該活化溶液可包含產生薄鈀層之鈀鹽。該層極薄且通常不覆蓋整個銅或銅合金打線接合部分。其不視為層總成中之不同層,而是視為活化作用,其形成除鈀/鈀合金層以外的金屬晶種層。該晶種層之厚度通常為幾埃(angstrom)。該晶種層藉由浸漬式交換法電鍍至銅或銅合金層。For the purposes of the present invention, another activation step can be advantageously applied to the copper or copper alloy wire bond portion prior to depositing the palladium or palladium alloy layer. The activation solution can comprise a palladium salt that produces a thin palladium layer. This layer is extremely thin and typically does not cover the entire copper or copper alloy wire bond portion. It is not considered to be a different layer in the layer assembly, but rather as an activation which forms a metal seed layer other than the palladium/palladium alloy layer. The thickness of the seed layer is typically a few angstroms. The seed layer is electroplated to a copper or copper alloy layer by an immersion exchange process.

若藉由無電極(自催化)電鍍方法沈積鈀層,則該活化溶液尤其較佳。The activation solution is particularly preferred if the palladium layer is deposited by an electrodeless (autocatalytic) plating method.

此鈀/鈀合金層較佳電鍍至設置於積體電路基材或印刷電路板上之銅或銅合金結構上。The palladium/palladium alloy layer is preferably plated onto a copper or copper alloy structure disposed on an integrated circuit substrate or a printed circuit board.

積體電路基材包含載體主體及設置於該載體主體一側或兩側上的銅結構。因此,在金屬結構上塗覆鈀或鈀合金層。隨後,銅打線接合於鈀或鈀合金層上。The integrated circuit substrate includes a carrier body and a copper structure disposed on one or both sides of the carrier body. Therefore, a palladium or palladium alloy layer is coated on the metal structure. Subsequently, the copper wire is bonded to the palladium or palladium alloy layer.

銅線較佳為純銅線。或者,其可為銅合金線。又,銅線或銅合金線可塗覆金或鈀,較佳為鈀。鈀塗層之厚度可例如介於5-50 nm之間,較佳為10-25 nm。金塗層可具有相同厚度範圍。The copper wire is preferably a pure copper wire. Alternatively, it may be a copper alloy wire. Further, the copper wire or copper alloy wire may be coated with gold or palladium, preferably palladium. The thickness of the palladium coating can be, for example, between 5 and 50 nm, preferably between 10 and 25 nm. The gold coating can have the same thickness range.

銅結構包含打線接合部分(亦稱為接合墊),其用於連接電子組件與基材;導線,其用於襯墊之間及金屬化孔洞與襯墊之間的電連接;及其他導體區域,例如接地區域、屏蔽區域及其類似區域。鈀或鈀合金層較佳僅塗覆於焊接及接合部分上,而不塗覆於導線及其他導體區域上。The copper structure includes a wire bond portion (also referred to as a bond pad) for connecting the electronic component to the substrate; a wire for electrical connection between the pads and between the metallized hole and the pad; and other conductor regions , for example, a grounded area, a shielded area, and the like. The palladium or palladium alloy layer is preferably applied only to the solder and joint portions and not to the wires and other conductor regions.

與先前技術相比,本發明之層總成提供電子組件與基材之間最可靠的接合連接。The layer assembly of the present invention provides the most reliable joint connection between the electronic component and the substrate as compared to the prior art.

本發明之層總成亦不含電鍍於鈀或鈀合金層上之金層。此不僅僅是顯著降低了總製程成本。本發明者亦發現,省去金層大大增強打線接合效能。The layer assembly of the present invention also does not contain a gold layer plated onto the palladium or palladium alloy layer. This not only significantly reduces the total process cost. The inventors have also discovered that the elimination of the gold layer greatly enhances the bonding efficiency.

本發明之方法較佳包含藉由無電極(自催化)電鍍沈積鈀或鈀合金層。The method of the present invention preferably comprises depositing a layer of palladium or palladium alloy by electroless (autocatalytic) electroplating.

無電極(自催化)電鍍涉及借助於無電極電鍍溶液中所含的還原劑還原金屬來沈積金屬,該還原劑因此氧化。基材金屬因此將氧化且從而溶解。在此情況下不使用電鍍溶液中所含的還原劑。Electrodeless (autocatalytic) electroplating involves depositing a metal by means of a reducing agent contained in an electroless plating solution to deposit a metal, which is thus oxidized. The substrate metal will therefore oxidize and thereby dissolve. In this case, the reducing agent contained in the plating solution is not used.

此外,較佳可藉由使基材之至少一個銅線部分與含有鈀離子源及還原劑之溶液(其不含磷且引起純鈀層沈積)接觸來沈積純鈀層。Further, it is preferred to deposit a pure palladium layer by contacting at least one copper wire portion of the substrate with a solution containing a source of palladium ions and a reducing agent which does not contain phosphorus and causes deposition of a pure palladium layer.

適用於沈積純鈀層之無電極(自催化)電鍍浴組合物描述於例如US 5,882,736中。該電鍍浴含有鈀鹽、一或多種氮化錯合劑及甲酸或甲酸衍生物,但不含次磷酸鹽及/或胺硼烷化合物。溶液之pH值高於4。較佳使用一級胺、二級胺或三級胺或多元胺作為氮化錯合劑。其為例如伸乙基-二胺;1,3-二胺基-丙烷、1,2-雙(3-胺基-丙基-胺基)-乙烷;2-二乙基-胺基-乙基-胺;及二伸乙基-三胺。此外,亦可使用二伸乙基-三胺-五乙酸;硝基-乙酸;N-(2-羥基-乙基)-伸乙基-二胺;伸乙基-二胺-N,N-二乙酸;2-(二甲基-胺基)-乙基-胺;1,2-二胺基-丙基-胺;1,3-二胺基-丙基-胺;3-(甲基-胺基)-丙基-胺;3-(二甲基-胺基)-丙基-胺;3-(二乙基-胺基)-丙基-胺;雙(3-胺基-丙基)-胺;1,2-雙(3-胺基-丙基)-烷基-胺;二伸乙基-三胺;三伸乙基-四胺;四伸乙基-五胺;五伸乙基-六胺;及該等氮化錯合劑之任何所要混合物。然而,含硫化合物不作為穩定劑與錯合劑一起使用。Electrodeless (autocatalytic) electroplating bath compositions suitable for depositing a pure palladium layer are described, for example, in US 5,882,736. The electroplating bath contains a palladium salt, one or more nitriding complexing agents, and a formic acid or formic acid derivative, but does not contain a hypophosphite and/or an amine borane compound. The pH of the solution is above 4. A primary amine, a secondary amine or a tertiary amine or a polyamine is preferably used as the nitriding wrong agent. It is, for example, an ethyl-diamine; 1,3-diamino-propane, 1,2-bis(3-amino-propyl-amino)-ethane; 2-diethyl-amino group- Ethyl-amine; and di-ethyl-triamine. In addition, di-ethyl-triamine-pentaacetic acid; nitro-acetic acid; N-(2-hydroxy-ethyl)-extended ethyl-diamine; ethyl-diamine-N,N- Diacetic acid; 2-(dimethyl-amino)-ethyl-amine; 1,2-diamino-propyl-amine; 1,3-diamino-propyl-amine; 3-(methyl -amino)-propyl-amine; 3-(dimethyl-amino)-propyl-amine; 3-(diethyl-amino)-propyl-amine; bis(3-amino-propyl , an amine; 1,2-bis(3-amino-propyl)-alkyl-amine; di-ethyl-triamine; tri-ethyl-tetraamine; tetraethyl-pentamine; Ethyl-hexamine; and any desired mixture of such nitriding complexing agents. However, sulfur-containing compounds are not used as stabilizers with the wronging agent.

更佳的是,用於以無電極方式沈積純鈀層之溶液為水溶液且含有鈀鹽(諸如氯化鈀或硫酸鈀)、作為還原劑之不含次磷酸鹽之化合物(例如甲酸、礦物酸(諸如硫酸及鹽酸)或礦物鹼(例如氫氧化鈉或氫氧化鉀))、錯合劑(例如胺化合物,諸如伸乙二胺)及(若需要)穩定化合物。或者,其他可使用之無電極電鍍鈀沈積溶液及方法在此項技術中熟知且描述於:美國專利第5,292,361號、第4,424,241號、第4,341,846號、第4,279,951號及第4,255,194號中。More preferably, the solution for depositing a pure palladium layer in an electrodeless manner is an aqueous solution and contains a palladium salt such as palladium chloride or palladium sulfate, and a hypophosphite-free compound (for example, formic acid, mineral acid) as a reducing agent. (such as sulfuric acid and hydrochloric acid) or a mineral base (such as sodium hydroxide or potassium hydroxide), a complexing agent (such as an amine compound such as ethylenediamine) and, if desired, a stabilizing compound. Alternatively, other electrodeless electroplating palladium deposition solutions and methods that can be used are well known in the art and are described in U.S. Patent Nos. 5,292,361, 4,424,241, 4,341,846, 4,279,951, and 4,255,194.

在本發明之另一較佳實施例中,基材之一側或兩側設置有保形遮罩,除該一側或兩側上之至少一個銅打線部分上塗有鈀或鈀合金層之區域外,該保形遮罩覆蓋該基材之該一側或兩側上之所有區域。保形遮罩較佳可為阻焊遮罩,例如可曝光及可顯影遮罩。該遮罩可以例如環氧樹脂為基礎且層壓、旋塗、滾塗或以類似方式施加於電路載體表面。隨後其曝露於光化性光且經顯影以暴露表面上將沈積層總成之區域。該等區域將設置打線接合部分。可形成保形遮罩使得基材表面上之暴露區域大於銅結構中形成之打線接合部分,藉此使基材之部分介電質表面區域曝光,或使得基材表面上之暴露區域小於銅結構中形成之打線接合部分,以便僅暴露銅結構中形成之打線接合部分。In another preferred embodiment of the present invention, a conformal mask is disposed on one or both sides of the substrate, except that at least one of the copper wire portions on the one or both sides is coated with a palladium or palladium alloy layer. In addition, the conformal mask covers all areas on one or both sides of the substrate. The conformal mask may preferably be a solder mask, such as an exposable and developable mask. The mask may be based on, for example, epoxy resin and laminated, spin coated, rolled or otherwise applied to the surface of the circuit carrier. It is then exposed to actinic light and developed to expose the area of the surface on which the deposited layer will be assembled. These areas will set the wire bonding portion. The conformal mask may be formed such that the exposed area on the surface of the substrate is larger than the wire bonding portion formed in the copper structure, thereby exposing a portion of the dielectric surface area of the substrate, or causing the exposed area on the surface of the substrate to be smaller than the copper structure The wire bonding portion is formed in the middle to expose only the wire bonding portion formed in the copper structure.

根據本發明之方法,所曝光之由銅或銅合金製成之打線接合部分鍍有純鈀或鈀合金層。According to the method of the present invention, the exposed wire bonding portion made of copper or a copper alloy is plated with a layer of pure palladium or palladium alloy.

鈀合金層較佳為具有0.1-10 wt.%,更佳0.5-7 wt.%磷含量之鈀-磷層。本發明之純鈀層為鈀含量超過99.0 wt.%,較佳超過99.5 wt.%鈀或更佳超過99.9 wt.%或超過99.99 wt.%鈀之層。較佳為純鈀層。The palladium alloy layer is preferably a palladium-phosphorus layer having a phosphorus content of 0.1 to 10 wt.%, more preferably 0.5 to 7 wt.%. The pure palladium layer of the present invention is a layer having a palladium content of more than 99.0 wt.%, preferably more than 99.5 wt.% palladium or more preferably more than 99.9 wt.% or more than 99.99 wt.% palladium. A pure palladium layer is preferred.

在所曝光之打線接合部分上電鍍鈀或鈀合金以形成鈀或鈀合金電鍍層。A palladium or palladium alloy is electroplated on the exposed wire bonding portion to form a palladium or palladium alloy plating layer.

以下更詳細描述在打線接合部分上形成無電極鈀或鈀合金電鍍層。An electrodeless palladium or palladium alloy plating layer is formed on the wire bonding portion in more detail below.

電鍍溶液中所用的還原劑決定是否電鍍純鈀或鈀合金(鈀-磷、鈀-硼)。舉例而言,適用於本發明之典型無電極電鍍鈀溶液包含(但不限於)作為鈀來源之硫酸鈀;作為還原劑之次磷酸鈉或二甲胺硼烷、甲醛或甲酸;作為錯合劑之乳酸及作為緩衝劑之丁二酸。為獲得鈀電鍍層之緻密結構,無電極電鍍鈀溶液之pH值較佳在4.5至5.5範圍內。The reducing agent used in the plating solution determines whether or not the pure palladium or palladium alloy (palladium-phosphorus, palladium-boron) is electroplated. For example, a typical electrodeless electroplating palladium solution suitable for use in the present invention includes, but is not limited to, palladium sulfate as a source of palladium; sodium hypophosphite or dimethylamine borane, formaldehyde or formic acid as a reducing agent; Lactic acid and succinic acid as a buffer. In order to obtain a dense structure of the palladium plating layer, the pH of the electrodeless electroplating palladium solution is preferably in the range of 4.5 to 5.5.

鈀或鈀合金電鍍製程係在約45℃至80℃下進行1分鐘至60分鐘而得到厚度在0.05至5.0 μm,更佳0.1至1.0 μm且更佳0.1至0.5 μm範圍內之鈀或鈀合金電鍍層。The palladium or palladium alloy electroplating process is carried out at about 45 ° C to 80 ° C for 1 minute to 60 minutes to obtain a palladium or palladium alloy having a thickness in the range of 0.05 to 5.0 μm, more preferably 0.1 to 1.0 μm and more preferably 0.1 to 0.5 μm. Plating.

電鍍浴中錯合劑之濃度係視鈀含量而定。通常,錯合劑與鈀之莫耳比為5:1至50:1,其中電鍍浴中錯合劑之濃度為每公升電鍍浴0.05公克至100公克。The concentration of the complexing agent in the plating bath depends on the palladium content. Typically, the molar ratio of the cross-linking agent to palladium is from 5:1 to 50:1, wherein the concentration of the cross-linking agent in the electroplating bath is from 0.05 grams to 100 grams per liter of plating bath.

塗覆溶液之pH值通常大於4。在pH值低於4之情況下,溶液變得不穩定且由於產生氫氣而傾向於自分解。在pH值稍低於4之情況下,金屬表面上主要沈積黏性不良的黑色鈀層,而在pH值低於約2之情況下,鈀自溶液中沈澱析出。在此情況下,基材上所得沈澱物呈黑色且黏性不足。The pH of the coating solution is usually greater than 4. In the case where the pH is lower than 4, the solution becomes unstable and tends to self-decompose due to the generation of hydrogen. At a pH slightly below 4, a poorly viscous black palladium layer is deposited on the metal surface, and at a pH below about 2, palladium precipitates out of solution. In this case, the resulting precipitate on the substrate was black and insufficiently sticky.

塗覆溶液之pH值較佳在5至6範圍內。在pH值大於7之情況下,鹼性浴使鈀以膠結方式(亦即無明亮光澤或黏著至基材)沈積於金屬表面上之傾向增強。此外,鹼塗覆溶液會侵蝕塗覆於電路板上之有機抗性膜,諸如阻焊遮罩。The pH of the coating solution is preferably in the range of 5 to 6. At pH values greater than 7, the alkaline bath enhances the tendency of palladium to deposit on the metal surface in a cemented manner (i.e., without bright gloss or adhesion to the substrate). In addition, the alkali coating solution can attack organically resistant films, such as solder masks, that are applied to the circuit board.

若在打線接合部分之銅或銅合金層上直接沈積純鈀層,則較佳對銅表面進行預處理。為達成此目的,通常於氧化性酸性溶液(例如硫酸與過氧化氫之溶液)中進行蝕刻清洗。較佳隨後再於酸性溶液(諸如硫酸溶液)中進行清洗。清洗後,較佳用含有鈀之溶液(諸如硫酸鈀溶液,其含有其他酸,例如硫酸、甲烷磺酸及磷酸)活化表面。通常,使基材在25℃至30℃下於活化浴中浸漬1至4分鐘。If a pure palladium layer is deposited directly on the copper or copper alloy layer of the wire bonding portion, the copper surface is preferably pretreated. To achieve this, etching cleaning is usually carried out in an oxidizing acidic solution such as a solution of sulfuric acid and hydrogen peroxide. Preferably, the cleaning is then carried out in an acidic solution such as a sulfuric acid solution. After washing, the surface is preferably activated with a solution containing palladium such as a palladium sulfate solution containing other acids such as sulfuric acid, methanesulfonic acid and phosphoric acid. Typically, the substrate is immersed in an activation bath at 25 ° C to 30 ° C for 1 to 4 minutes.

該活化步驟由於以下原因而為較佳:後續沈積步驟,例如於無電極(自催化)鈀浴中,該浴含有藉由鈀金屬之存在催化性活化之還原劑。因此,必須利用浸漬過程在銅表面上沈積至少一些鈀,其中更貴重的金屬鈀置換較不貴重的銅。若銅表面直接浸漬於自催化鈀浴中,則亦可發生此初始浸漬式鈀沈積,且一旦沈積極少量鈀,則該過程以自催化沈積方式進行。發現自催化鈀浴組合物可被過量銅離子去活化。若在自催化鈀浴中進行初始浸漬式鈀沈積,則不可避免地發生銅離子增濃。因此,在製備環境中,可較佳在自催化鈀浴前之額外步驟中應用浸漬式鈀浴(先前描述之活化溶液)以延長自催化鈀浴之使用壽命。This activation step is preferred for subsequent deposition steps, such as in an electrodeless (autocatalytic) palladium bath containing a reducing agent that is catalytically activated by the presence of palladium metal. Therefore, at least some palladium must be deposited on the copper surface by an impregnation process in which the more expensive metal palladium replaces the less expensive copper. This initial immersion palladium deposition can also occur if the copper surface is directly immersed in an autocatalytic palladium bath, and once a very small amount of palladium is deposited, the process proceeds in an autocatalytic deposition manner. The autocatalytic palladium bath composition was found to be deactivated by excess copper ions. If the initial immersion palladium deposition is carried out in an autocatalytic palladium bath, copper ion enrichment inevitably occurs. Thus, in a preparative environment, an impregnated palladium bath (the previously described activation solution) may be preferably employed in an additional step prior to the autocatalytic palladium bath to extend the useful life of the autocatalytic palladium bath.

接著,在較佳實施例中,可沖洗表面且接著在上述活化鈀浴中預處理後用無電極(自催化)鈀浴處理;在另一情況下,其可立即用無電極(自催化)鈀浴處理而不在活化鈀浴中進行預處理。Next, in a preferred embodiment, the surface can be rinsed and then pretreated in an activated palladium bath followed by an electrodeless (autocatalytic) palladium bath; in another case, it can be immediately electrodeless (autocatalytic) The palladium bath treatment was carried out without pretreatment in an activated palladium bath.

以下實例用於說明本發明之多種態樣。The following examples are provided to illustrate various aspects of the invention.

實例Instance

使用單面PCB(陣列大小61.8×113.8 mm)作為基材。陣列由兩張單卡(50×50 mm)組成。總銅厚度為30 μm(+/- 5 μm)。可在該基材之任何區域上進行打線接合。A single-sided PCB (array size 61.8 x 113.8 mm) was used as the substrate. The array consists of two single cards (50 x 50 mm). The total copper thickness is 30 μm (+/- 5 μm). Wire bonding can be performed on any area of the substrate.

基底材料為Hitachi MCL-E679FGB-(S),FR4 18/80,300 μm。The substrate material was Hitachi MCL-E679FGB-(S), FR4 18/80, 300 μm.

所用電鍍順序展示於下表中:The plating sequence used is shown in the table below:

表1A:在銅打線接合部分上電鍍純鈀(根據本發明)Table 1A: Electroplating of pure palladium on a copper wire bond portion (according to the invention)

表1B:使用浸漬式方法在銅墊上電鍍鈀(比較)Table 1B: Palladium plating on copper pads using an immersion method (comparative)

表2:在銅打線接合部分上電鍍鎳及純鈀Table 2: Electroplating of nickel and pure palladium on copper wire bonding

表3:在銅打線接合部分上電鍍鎳及鈀-磷合金Table 3: Electroplating of nickel and palladium-phosphorus alloys on copper wire joints

表4:在銅打線接合部分上電鍍鎳、純鈀及金(比較)Table 4: Electroplating of nickel, pure palladium and gold on copper wire joints (comparative)

根據表1 A/B-4使用之組分:Components used according to Table 1 A/B-4:

進行之測試:Test conducted: 拉拔測試Pull test

在如表1 A/B-4中所述沈積金屬層後,該等電鍍打線接合部分在165℃下接合於銅墊之具有Heraeus Maxsoft銅線(直徑0.8 μm)之部分上。使用微環境銅套組(Microenvironment Copper Kit)、使用Kulicke and Soffa Max Ultra打線接合器進行銅接合製程。形成氣體(5%/95% H2/N2)在形成期間保護無空氣焊球(free-air ball)。接合工具為Kulicke and Soffa CuPRAplus毛細管,其具有1.25密耳(mil)倒角直徑(CD)及60°內部倒角(ICA)。接合在超音波(US)處理存在下進行。After depositing the metal layers as described in Table 1 A/B-4, the electroplated wire bonding portions were bonded to a portion of the copper pad having a Heraeus Maxsoft copper wire (0.8 μm in diameter) at 165 °C. The copper bonding process was performed using a Microenvironment Copper Kit using a Kulicke and Soffa Max Ultra wire bonder. The forming gas (5%/95% H 2 /N 2 ) protects the free-air ball during formation. The bonding tool was a Kulicke and Soffa CuPRAplus capillary with a 1.25 mil chamfer diameter (CD) and a 60° internal chamfer (ICA). Bonding is performed in the presence of ultrasonic (US) processing.

在接合之前,用此項技術中已知的電漿蝕刻方法清洗鈀表面。Prior to bonding, the palladium surface is cleaned by plasma etching methods known in the art.

用Dage 4000 T p拉拔測試器進行拉拔測試。The pull test was performed with the Dage 4000 T p pull tester.

測試結果展示於表5中。測試10種接合樣品且表5中提供平均值。測試「表編號」指示如以上表1 A/B-4之電鍍順序。所得金屬層之厚度以μm表示。US處理時間在90秒與140秒之間變化。以公克拉力表示之相應拉拔強度值提供於表5中。The test results are shown in Table 5. Ten junction samples were tested and an average is provided in Table 5. The test "table number" indicates the plating sequence as shown in Table 1 A/B-4 above. The thickness of the resulting metal layer is expressed in μm. The US processing time varies between 90 seconds and 140 seconds. The corresponding pull strength values expressed in grams of carat force are provided in Table 5.

US(超音波)處理時間US (ultrasonic) processing time

表5:所得平均拉拔強度值之結果Table 5: Results of the average pull strength values obtained

如自表5之資料顯而易見,第1A號樣品之拉拔強度值在所有US處理時間中最高。拉拔強度值越高,則基材與銅線之間的接合越優良,此為所需的。接合強度值低於2.1視為不足以形成基材與銅線之間的可靠接合,介於2.2與3.9之間的值視為可接受。等於或高於4.0之值視為優良。當使用浸漬式鈀電鍍方法(第1B號樣品)電鍍鈀層時,與本發明之無電極(自催化)電鍍方法相比,接合效能顯著較弱。As evident from the information in Table 5, the pull strength value of sample No. 1A was highest in all US processing times. The higher the pull strength value, the better the bond between the substrate and the copper wire, which is desirable. A bond strength value below 2.1 is considered insufficient to form a reliable bond between the substrate and the copper wire, and a value between 2.2 and 3.9 is considered acceptable. A value equal to or higher than 4.0 is considered excellent. When the palladium layer was electroplated using the immersion palladium plating method (sample No. 1B), the bonding efficiency was remarkably weak as compared with the electrodeless (autocatalytic) plating method of the present invention.

第1號樣品之所有值均高於5,亦即第1號樣品極佳。此實例對應於本發明之尤其較佳實施例,其中鈀層為純鈀層且不經中間鎳或鎳合金層而直接沈積於銅打線接合部分上。All values of sample No. 1 were higher than 5, that is, sample No. 1 was excellent. This example corresponds to a particularly preferred embodiment of the invention wherein the palladium layer is a pure palladium layer and is deposited directly onto the copper wire bond portion without an intermediate nickel or nickel alloy layer.

第2號樣品及第3號樣品亦係藉由本發明之方法獲得且含有介於基材(更特定言之,打線接合部分)與鈀層之間的額外鎳層。所得平均拉拔強度值低於較佳實施例,但仍然可接受。Sample No. 2 and No. 3 were also obtained by the method of the present invention and contained an additional layer of nickel interposed between the substrate (more specifically, the wire bond portion) and the palladium layer. The resulting average draw strength value is lower than the preferred embodiment, but is still acceptable.

根據對應於比較實例之實驗添加金層(第4號樣品)作為總成之最終層意外引起所得平均拉拔強度值顯著降低。因此,接合效能較差。八個值中的三個值視為「不合格」,八個值中的五個值視為「可接受」且不存在極佳值。The addition of the gold layer (sample No. 4) as the final layer of the assembly according to the experiment corresponding to the comparative example unexpectedly caused the resulting average tensile strength value to be significantly lowered. Therefore, the bonding efficiency is poor. Three of the eight values are considered "failed" and five of the eight values are considered "acceptable" and there are no excellent values.

迄今,咸信金為最適用於打線接合之層。So far, Xianxinjin is the most suitable layer for wire bonding.

因此,藉由本發明之方法提供的層序列就所得平均拉拔強度值而言,產生極佳的銅打線接合結果,表明銅線與基材之處理表面之間的接合優良。Thus, the layer sequence provided by the method of the present invention produces excellent copper wire bonding results in terms of the resulting average draw strength value, indicating excellent bonding between the copper wire and the treated surface of the substrate.

對根據表1A(無電極(自催化)電鍍方法,本發明)及1B(浸漬式電鍍方法,比較)之電鍍方法所製備之樣品進行其他接合測試以確定本發明方法產生較佳接合效能。Other joint tests were conducted on samples prepared according to the plating methods of Table 1A (electrodeless (autocatalytic) plating method, the present invention) and 1B (immersion plating method, comparison) to determine that the method of the present invention produced better bonding efficiency.

測試如下所列四種樣品(具有兩種不同鈀層厚度)之Cu打線接合能力:Test the Cu wire bonding ability of the four samples listed below (with two different palladium layer thicknesses):

表1A:Table 1A:

無電極電鍍Pd(自催化)90 nm(Pd厚度90 nm)Electrodeless plating Pd (autocatalytic) 90 nm (Pd thickness 90 nm)

無電極電鍍Pd(自催化)150 nm(Pd厚度150 nm)Electrodeless plating Pd (autocatalytic) 150 nm (Pd thickness 150 nm)

表1B:Table 1B:

浸漬式Pd 100 nm,(Pd厚度100 nm)Impregnated Pd 100 nm, (Pd thickness 100 nm)

浸漬式Pd 150 nm,(Pd厚度150 nm)Impregnated Pd 150 nm, (Pd thickness 150 nm)

測試條件為「原樣」狀態(剛電鍍且未經熱處理)及在150℃熱處理4小時後。無電極(自催化)電鍍有鈀之所有樣品在兩種測試條件下均可與Cu接合。在浸漬式電鍍有Pd之樣品中,僅樣品「浸漬式Pd 150 nm」可在「原樣」條件下接合。樣品「浸漬式Pd 100 nm」在兩種測試條件下均不可接合,樣品「浸漬式Pd 150 nm」在熱處理「150℃,4小時」後不可接合。樣品在打線接合製程期間接合失敗。因此沒有銅線可固定於表面上且無法進行銅線拉拔測試。此外,浸漬式電鍍有Pd之兩種樣品在熱處理後顯示明顯變色。The test conditions were "as is" (just electroplated and not heat treated) and after heat treatment at 150 ° C for 4 hours. Electrodeless (autocatalytic) all samples plated with palladium were able to bond with Cu under both test conditions. In the sample impregnated with Pd, only the sample "impregnated Pd 150 nm" can be joined under "as is" conditions. The sample "impregnated Pd 100 nm" was not bondable under both test conditions, and the sample "impregnated Pd 150 nm" was not bondable after heat treatment "150 ° C for 4 hours". The sample failed to bond during the wire bonding process. Therefore, no copper wire can be fixed on the surface and the copper wire drawing test cannot be performed. In addition, the two samples impregnated with Pd showed significant discoloration after heat treatment.

除非另有說明,否則接合設備及參數如同上文所述,其中詳細參數設定如下。所用銅線:Hereaus Cu Maxsoft,Φ=20 μm,斷裂負載7.3 g,溫度:200℃。Unless otherwise stated, the joining equipment and parameters are as described above, with detailed parameters set as follows. Copper wire used: Hereaus Cu Maxsoft, Φ = 20 μm, breaking load 7.3 g, temperature: 200 °C.

表6:用於打線接合測試之參數設定Table 6: Parameter settings for wire bonding test

每個樣品進行30次拉拔。拉拔測試驗收準則係根據DVS 2811標準:最小斷裂力>50%線斷裂負載(>4.95 g);變異係數CV(標準差與平均值之比率)<0.15(<15%)。在接合前,所有樣品均用氬電漿預處理10分鐘。Each sample was subjected to 30 pulls. The pull test criteria are based on the DVS 2811 standard: minimum breaking force >50% line breaking load (>4.95 g); coefficient of variation CV (ratio of standard deviation to average) <0.15 (<15%). All samples were pretreated with argon plasma for 10 minutes prior to bonding.

表7:表面處理之拉拔強度(g);老化=按原樣Table 7: Drawing strength (g) of surface treatment; aging = as it is

表8:表面處理之拉拔強度(g);老化=4小時,150℃Table 8: Drawing strength (g) of surface treatment; aging = 4 hours, 150 ° C

如自表7及8顯而易見,由無電極(自催化)鈀沈積法獲得之鈀層之接合效能高於由浸漬式沈積獲得之鈀層之接合效能。在老化後及100 nm厚度下,浸漬式電鍍之鈀層完全不可接合且因此不適用於本發明之接合方法。As is apparent from Tables 7 and 8, the palladium layer obtained by the electrodeless (autocatalytic) palladium deposition method has a higher bonding efficiency than the palladium layer obtained by the impregnation deposition. After aging and at a thickness of 100 nm, the impregnated electroplated palladium layer is completely unbondable and therefore not suitable for use in the bonding method of the present invention.

Claims (7)

一種在基材上形成銅線之方法,該基材具有至少一個由銅或銅合金製成之打線接合部分,該方法包含以下步驟:(i)提供具有至少一個由銅或銅合金製成之打線接合部分的基材;(ii)在該至少一個打線接合部分上形成具有鈀含量超過99.9wt.%之鈀層,或包含90.0-99.9wt.%鈀及0.1-10.0wt.%磷之鈀合金層;及隨後(iii)將銅線接合於該鈀或鈀合金層上,及其中步驟(ii)之該鈀或鈀合金層係直接在該銅或銅合金接合部分上形成。 A method of forming a copper wire on a substrate having at least one wire bonding portion made of copper or a copper alloy, the method comprising the steps of: (i) providing at least one made of copper or a copper alloy a substrate for bonding the wire bonding portion; (ii) forming a palladium layer having a palladium content of more than 99.9 wt.% on the at least one wire bonding portion, or a palladium comprising 90.0-99.9 wt.% palladium and 0.1-10.0 wt.% phosphorus An alloy layer; and subsequently (iii) bonding a copper wire to the palladium or palladium alloy layer, and wherein the palladium or palladium alloy layer of step (ii) is formed directly on the copper or copper alloy joint portion. 如請求項1之方法,其中該鈀或鈀合金層之厚度為0.05-5.0μm。 The method of claim 1, wherein the palladium or palladium alloy layer has a thickness of from 0.05 to 5.0 μm. 如請求項1或2之方法,其中該鈀或鈀合金層之厚度為0.1-0.5μm。 The method of claim 1 or 2, wherein the palladium or palladium alloy layer has a thickness of from 0.1 to 0.5 μm. 如請求項1之方法,其中該鈀係自無電極(自催化)電鍍鈀浴中沈積,該無電極電鍍鈀浴包含:鈀離子源;錯合劑;還原劑。 The method of claim 1, wherein the palladium is deposited from an electrodeless (autocatalytic) electroplating palladium bath comprising: a source of palladium ions; a binder; a reducing agent. 一種層總成,其包含:(i)至少一個打線接合部分層,其由銅或銅合金製成;且於其上直接沈積: (ii)具有鈀含量超過99.9wt.%之鈀層,或包含90.0-99.9wt.%鈀及0.1-10.0wt.%磷之鈀合金層;及(iii)打線接合於該鈀或鈀合金層上之銅。 A layer assembly comprising: (i) at least one wire bonding portion layer made of copper or a copper alloy; and deposited directly thereon: (ii) a palladium layer having a palladium content of more than 99.9 wt.%, or a palladium alloy layer comprising 90.0-99.9 wt.% palladium and 0.1-10.0 wt.% phosphorus; and (iii) wire bonding to the palladium or palladium alloy layer Copper on the top. 一種印刷電路板,其具有如請求項5之層總成,及另外,用於連接外部部件與該印刷電路板之焊接部分。 A printed circuit board having a layer assembly as claimed in claim 5, and additionally, a solder portion for connecting an external component to the printed circuit board. 一種積體電路,其具有如請求項5之層總成。 An integrated circuit having a layer assembly as claimed in claim 5.
TW100148422A 2010-12-23 2011-12-23 Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and ic-substrates and the products prepared therefrom TWI551361B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175609A (en) * 1991-04-10 1992-12-29 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
EP0697805A1 (en) * 1994-08-05 1996-02-21 LeaRonal, Inc. Printed circuit board manufacture utilizing electroless palladium
US20060055023A1 (en) * 2004-09-10 2006-03-16 Kwun-Yao Ho Chip carrier and chip package structure thereof
TW201036131A (en) * 2009-03-23 2010-10-01 Tanaka Electronics Ind Coated copper wire for ball bonding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175609A (en) * 1991-04-10 1992-12-29 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
EP0697805A1 (en) * 1994-08-05 1996-02-21 LeaRonal, Inc. Printed circuit board manufacture utilizing electroless palladium
US20060055023A1 (en) * 2004-09-10 2006-03-16 Kwun-Yao Ho Chip carrier and chip package structure thereof
TW201036131A (en) * 2009-03-23 2010-10-01 Tanaka Electronics Ind Coated copper wire for ball bonding

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