TWI551050B - Signal modulation by pulse train segments for radiofrequency communications - Google Patents

Description

Signal Modulation of Pulse Sequence Fragments for Radio Frequency Communication

The invention relates to the technical field of signal modulation devices and methods for radio frequency communication, in particular for providing output signals to an RF front end, in particular a switching mode power amplifier.

Switching mode is an emerging technology for achieving high power efficiency in radio frequency (RF) power amplifiers. The switching mode means that the power transistor is in a fully conductive state or a fully closed state. Next, a filter at the output is typically required to remove unwanted harmonics of the switching frequency and quantize the noise.

The method of obtaining the bandpass RF signal is to use bandpass triangular wave modulation (BPSDM) operating at four times the RF carrier frequency. The development according to this method is disclosed in, for example, EP-A1-2330734 and EP-A1-2403136. However, including BPDSM, these techniques result in four pulses per carrier frequency and have an overall digital chain limitation that operates at very high frequencies above the desired RF carrier frequency, creating significant technical limitations.

Craven P. Posted by J.Audio Eng.Soc., Vol.41, No.5 (Towel the 24-bit DAC; novel noise-shaping topologies bringing correction for the nonlinearity in a PWM output stage) (XP000432100) reveals a nonlinear noise shaper that includes the essence of a combination via feedback or feedforward and feedback. Digital simulation and correction of PWM nonlinearity.

The method disclosed in WO-A1-2001/97384 measures the difference between a desired output signal and a real output signal based on a pulse-by-pulse pulse to reduce distortion and noise in a high power digital PWM amplifier.

WO-A 2-9215153 discloses a signal converter comprising a pulse modulator and a correction mechanism that corrects a signal input thereto based on an error in a previous value of its output to reduce an error effect in a desired signal band.

According to a first object, the present invention provides a method for generating a symbol mapping table in a memory to map a finite number of quantized complex output states of a modulation device operating at a first oversampling clock rate to quantized symbols, The method comprises: selecting a carrier frequency; selecting an initial group of pulse sequence segments having a time granularity corresponding to a second oversampling clock rate; determining a complex energy coefficient of the pulse sequence segment of the initial group at the carrier frequency; selecting a pulse sequence segment a subset, the complex energy coefficients of the subset of the pulse sequence segments at the carrier frequency closely approximating the quantized complex output state of the modulation device such that each quantized complex output state is uniquely mapped to the subset of pulse sequence segments; Quantizing each pulse sequence segment of the complex output state, and recording the quantized symbols of the pulse sequence segment is recorded and quantized The number of memory addresses associated with the number of output states.

According to an embodiment, such a method includes one or more of the following features.

In an embodiment, the method further generates a digital predistortion table in the memory, the method further comprising: effecting a complex energy coefficient of the pulse sequence segment of the carrier frequency on each pulse sequence segment mapped to the quantized complex output state, The complex predistortion symbols are determined, and the predistort symbols are recorded in a memory address associated with the quantized complex output state.

In an embodiment, the step of selecting a subset of the pulse sequence segments comprises: calculating a complex planar distance between the quantized complex output state of the modulation device and the complex energy coefficient of each pulse sequence segment, mapping the quantized complex output state to a minimum A sequence of pulse sequences of complex plane distances, as well as discarding segments of pulse sequences that are not mapped to any quantized complex output state.

In an embodiment, the method further comprises: determining a complex plexus center of the complex energy coefficient at the carrier frequency; shifting the complex plexus by a complex number such that the center of the complex plexus and the quantized complex output state of the modulating device form a second The center of the bundle is substantially matched.

In an embodiment, the method further comprises: determining a first circle geometrically embedded in a complex plex of the complex energy coefficients of the carrier frequency; and scaling the complex plexes to radius and modulate the embedded circle The peak energy of the quantized complex output state of the device is substantially equal.

In an embodiment, the step of selecting an initial set of pulse sequence segments comprises selecting a binary word length and constructing the length of the selected binary word The second carry word uniquely represents the width modulation and/or position modulation pulse sequence segment group.

In an embodiment, the step of selecting an initial set of pulse sequence segments includes selecting a limit, and constructing a set of width modulated and/or position modulated pulse sequence segments that satisfy the limit.

This initial limit is imposed to suit various purposes. In an embodiment, limiting the harmonics of the pulse sequence segments used to pre-plan the pulse sequence segments to emphasize the second Nyquist region at the carrier frequency such that at the first oversampling clock rate The upper carrier frequency can be combined with maximum power and minimum quantization noise.

In an embodiment, a fixed number of pulses defining each pulse sequence segment is limited, in particular one pulse per pulse sequence segment or two pulses per pulse sequence segment.

In an embodiment, limiting the logical relationship between the first half and the second half of the segment of the pulse sequence, in particular defining the equality, sign and sign between the first half and the second half of the pulse sequence segment Opposite, or complementary.

In an embodiment, the limit defines a fixed value for the second half of the pulse sequence segment.

In an embodiment, the pulses in the pulse sequence segment comprise a single level pulse.

In an embodiment, the pulses in the pulse sequence segment comprise a multi-level pulse, in particular a pulse having a two or three amplitude state other than zero.

In an embodiment, determining the complex number of the pulse sequence segments at the carrier frequency The step of energy coefficient includes calculating a discrete Fourier transform point of the pulse sequence segment at the desired carrier frequency.

In an embodiment, the step of determining the complex energy coefficient of the pulse sequence segment at the carrier frequency comprises feeding the pulse sequence segment to a radio frequency front end for transmitting the electromagnetic field and measuring the energy content of the electromagnetic field emitted at the carrier frequency.

In an embodiment, the present invention also provides a memory including at least one of a symbol map and a digital predistortion table generated by the above method.

In an embodiment, the method of using the memory includes: receiving an intermediate signal of a first oversampling clock rate; reading a quantized symbol in a symbol mapping table of a memory address associated with a current quantized complex state of the intermediate signal Reading a predistorted symbol in a digital predistortion table of a memory address associated with a current quantized complex state of the intermediate signal; generating a pulse sequence segment encoded by the quantized symbol; and providing a predistorted symbol as a feedback signal to Δ modulator.

According to an embodiment, the methods include one or more of the following features.

In one embodiment, the generated pulse sequence segment comprises a multi-level pulse, and the method further comprises a plurality of parallel single-level pulse sequence segments into which the multi-level pulse sequence segment is converted by the multi-branch power amplifier design and each A single bit quasi-pulse sequence segment is fed to the corresponding power amplifier feed branch.

In an embodiment, the multi-drop power amplifier design can be a two-way symmetric pulse feed, a two-way asymmetric 1:2 pulse feed Doherty or a three-way symmetric pulse feed Doer, and the like.

A first aspect of the present invention is based on the concept of being able to arbitrarily select pulses by using a pre-computed codebook to change the number of pulses per carrier cycle or to select an optimized set of pulses for a given carrier frequency. The first object of the present invention is based on the observation that careful selection of the pulse energy to be used has a positive influence on the characteristics of various systems and requirements, that is, clock rate requirements, coding efficiency, and frequency band signal noise. Ratio, capacitance loss in the driver and power amplifier, and so on.

According to a second object, the present invention provides a signal modulation device for providing an output signal to an RF front end, the device comprising: an input for receiving a plurality of input signals, the complex input signal comprising an in-phase component signal and a quadrature phase component signal; Σ Δ The modulator converts the complex input signal into an intermediate signal at an oversampling clock rate, wherein the intermediate signal obtains a first finite number of quantized complex states; and maps the quantized complex state of the intermediate signal to a predetermined quantized symbol a mapping table, each predetermined quantized symbol encoding a pulse sequence segment of the output signal; and a numerical oscillator for generating a phase signal oscillating at the selected carrier frequency, wherein the phase signal obtains a second finite number of quantization states, The symbol mapping table includes predetermined quantized symbols for each quantized complex state of the intermediate signal and each quantized state of the phase signal, and with the current quantized complex state of the intermediate signal and the current quantized state of the phase signal, The quantized symbols are selected by oversampling the clock cycle operation.

According to an embodiment, such a signal modulation device includes one or more of the following features.

In an embodiment, the apparatus further includes a quantized complex state of the intermediate signal A digital predistortion table mapped to a predetermined predistorted symbol, and a feedback loop for providing a predistorted symbol to the ΣΔ modulator.

In an embodiment, the digital predistortion table includes predetermined predistorted symbols for each quantized complex state of the intermediate signal and each quantized state of the phase signal, and the current quantized complex number of the intermediate signal during each oversampling clock cycle operation The current quantized state of the state and phase signals is used to select the predistorted symbols.

In an embodiment, the predistortion symbol associated with the quantized state of the intermediate signal and the quantized state of the phase signal is an energy coefficient of the pulse sequence segment encoded by the quantized symbol corresponding to the carrier frequency and a quantization corresponding to the complex phase signal A function of the complex phase coefficient of the state.

In an embodiment, the apparatus further includes a pulse generator configured to receive quantized symbols selected at each of the oversampled clock cycles, wherein the pulse generator generates a pulse sequence segment as a function of the received quantized symbols, wherein the pulse The generator operates at a second oversampling clock rate.

In an embodiment, the quantized symbols comprise a parallel binary order, and wherein the pulse generator comprises a sequencer that serializes the parallel binary order at a second oversampling clock rate.

In an embodiment, the phase signal is encoded with a predetermined number of bits, such as 4 bits.

In an embodiment, the numerical oscillator includes a phase accumulator that operates by defining a control signal of the selected carrier frequency of the predetermined number of bit codes and a clock signal of the first oversampling clock rate. The device also includes multi-level low-pass noise shaping Σ Δ filter, multi-level low-pass noise The shaping Δ Δ filter is configured to provide a control signal that is coded with a predetermined number of bits by filtering a refined control signal that is encoded with a higher number of bits.

In an embodiment, the device further includes a rate adjustable clock, the rate adjustable clock configured to provide a clock signal of the first oversampling clock rate, wherein the first oversampling clock rate is within a small adjustment range Adjusted.

In an embodiment, the symbol mapping table is obtained by performing the following steps: selecting an initial group of pulse sequence segments having a time granularity corresponding to a second oversampling clock rate; determining a pulse sequence segment of the initial set of carrier frequencies a complex energy coefficient; and, for each quantized state of the phase signal, calculating a complex phase coefficient corresponding to a quantized state of the complex phase signal; and selecting a subset of the pulse sequence segments, the subset of the pulse sequence segments being at a complex frequency of the carrier frequency The energy coefficient closely approximates the quantized complex state of the intermediate signal multiplied by the complex phase coefficients such that each quantized complex state of the intermediate signal is uniquely mapped to a pulse sequence segment such as a subset of the best adapted pulse sequence segments; Each of the pulse sequence segments of the complex output state is quantized, and the quantized symbols encoded by the pulse sequence segments are recorded in a memory address associated with the combination of the quantized complex state of the intermediate signal and the quantized state of the phase signal.

According to a second object, the present invention also provides a signal modulation method for providing an output signal to an RF front end, the method comprising: receiving an input of a plurality of input signals, wherein the plurality of input signals include an in-phase component signal and a quadrature phase component signal; The clock rate adjusts the complex input signal Σ Δ to an intermediate signal, wherein the intermediate signal obtains a first finite number of quantized complex states; generating a phase signal oscillating at the selected carrier frequency, wherein the phase The signal obtains a second limited number of quantization states; the symbol table is accessed in each oversampling clock cycle, and the pulse sequence segment of the output signal is selected according to the current quantized complex state of the intermediate signal and the current quantized state of the phase signal. The quantized symbol, wherein the symbol mapping table includes predetermined quantized symbols for each quantized complex state of the intermediate signal and each quantized state of the phase signal.

A second aspect of the present invention is based on the concept of being able to arbitrarily select a carrier oversampling ratio to limit the clock rate requirement. A second object of the present invention is derived from the observation that a higher carrier frequency can be produced at the same oversampling clock rate to help reduce the pulse density to relax the limitations of the power amplifier and driver chain and thereby reduce the gate. Power consumption of capacitor charging and discharging.

1‧‧‧Transformer

2‧‧‧Power Amplifier

3‧‧‧Bandpass output filter

4‧‧‧Antenna

5‧‧‧ Radio front end

6‧‧‧Multiple baseband signals

7‧‧‧ Frequency conversion time domain pulse signal

9‧‧‧Amplifier Bungee

10‧‧‧With pass Σ Δ modulator

11‧‧‧First quantizer

12‧‧‧Intermediate signal

13‧‧‧ Random access memory

14‧‧‧ symbol mapping table

15‧‧‧Digital predistortion symbol

16‧‧‧ pulse code

17‧‧‧Pulse generator

18‧‧‧Multiple power factor

35‧‧‧ Tap delay

50‧‧‧Numerical Controlled Oscillator

51‧‧‧ plural digits

52‧‧‧Upconversion intermediate signal

60‧‧‧Numerical Oscillator

61‧‧‧Quantified phase signal

63‧‧‧Control signal

70‧‧‧ Mixer

71‧‧‧Mixer

80‧‧‧ filter

81‧‧‧Enter

82‧‧‧ Input

106‧‧‧Multiple input signals

107‧‧‧Output signal

110‧‧‧Low-pass ΔΔ modulator

111‧‧‧First quantizer

112‧‧‧Multiple intermediate signals

113‧‧‧ memory

114‧‧‧ symbol mapping table

115‧‧‧Digital predistortion symbols

116‧‧‧Quantitative symbols

117‧‧‧ pulse generator

118‧‧‧Multiple power factor

These and other aspects of the invention may be apparent from and elucidated with reference to the illustrated embodiments illustrated herein.

1 is a functional representation of a radio frequency transmitter for digital communication.

2 is a functional representation of a signal modulation device for the transmitter of FIG. 1.

Figure 3 shows the complex bundle taken with the ΣΔ modulator of the modulation device of Figure 2.

4 is a schematic diagram of a pulse sequence segment encoded by a symbol map of the modulation device of FIG.

Figures 5 and 6 show the sequence of pulse sequences at two different carrier frequencies. Group of plural bundles.

Figure 7 is a representation of a pulse sequence segment that conforms to the twin pulse limit.

Figure 8 shows the complex energy bundle of a double pulse sequence segment set that conforms to the twin pulse limit at the carrier frequency.

Figure 9 is a schematic diagram of a pulse sequence segment that conforms to the P-0 limit.

Figure 10 is a schematic diagram of a pulse sequence segment that conforms to a symmetric limit.

Figure 11 is a schematic diagram of a pulse sequence segment that meets the opposite limitations.

Figure 12 is a schematic diagram of a pulse sequence segment that conforms to a complementary limit.

Figure 13 shows a spectrogram of the PPWM signal generated by the modulation device of Figure 2.

Figure 14 shows a time domain diagram of a three-bit quasi-pulse sequence generated by the modulation device of Figure 2 in an embodiment.

Figure 15 shows a time domain diagram of a four-bit quasi-pulse sequence generated by the modulation device of Figure 2 in an embodiment.

16 is a functional diagram of a signal modulation device for use in the transmitter of FIG. 1 in accordance with another embodiment.

17 is a conceptual diagram of a signal modulation device used in the transmitter of FIG. 1 in accordance with another embodiment.

Fig. 18 is a view showing the function of a signal modulation device for simulating the signal modulation device of Fig. 17.

Figure 19 is a functional representation of a modified embodiment of the signal modulation device of Figure 18.

Figure 20 shows the complex energy bundles taken by the ΣΔ modulator of the modulation device of Figures 17-19.

21 is a flow chart of a codebook selection method.

Illustrating an embodiment of a signal modulation device for use in a switched mode power amplifier of a wireless communication network such as 3G, 4G and higher. The RF carrier frequency used in these networks depends on the technology and regional spectrum management constraints and typically ranges between 700 MHz and 2.7 GHz.

Referring to Figure 1, a digital RF transmitter is illustrated. The digital RF transmitter includes a digital modulation device 1, a power amplifier 2, a band pass output filter 3, and an antenna 4. In contrast to the digital modulation device 1, the power amplifier 2, the band-pass output filter 3, and the antenna 4 are referred to as a radio front end 5.

The modulation device 1 includes two quantizer stages, the two quantizer stages operating at a first oversampling clock rate F1 and a second oversampling clock rate F2, respectively. The ratio between the oversampled clock rates F1 and F2 will be expressed as N = F2 / F1.

The modulation device 1 receives a complex baseband signal 6 at the input. The sampling rate of baseband signal 6 will be indicated as F0. The oversampling ratio between the sampling rate F0 and the first oversampling clock rate F1 will be expressed as M = F1/F0.

In implementation, the baseband signal 6 is received as a two parallel scalar component, i.e., an in-phase component labeled I and a quadrature phase component labeled Q. In the following, a signal processing method applied to the complex baseband signal 6, for example, ΣΔ modulation, will be explained. Because of the linearity, those skilled in the art will appreciate that the ΣΔ modulation of the complex signal can be implemented as two parallel ΣΔ modulation processes for forming the scalar components of the complex signal.

The modulation device 1 transmits the frequency conversion time domain pulse signal 7 to the radio The front end 5, the pulse signal 7 encodes the information content of the baseband signal 6 by the amplitude and position and/or width of the pulse.

Referring to Figure 2, an embodiment of a modulation device 1 employing BPSDM will now be described. As is known in the art, the bandpass ΔΔ modulator operates to frequency convert a useful information signal into a useful frequency band, also known as a clean bandwidth, and rejects quantization noise outside of the useful frequency band. The noise conversion function of this modulator has a typical V-shaped envelope as shown in the simulation results of FIG. The quantization noise rejected outside the clean bandwidth is filtered by the bandpass output filter 3.

For the sake of brevity, it is stated that the bandpass ΔΔ modulator 10 of Figure 2 is designed such that its clean bandwidth is centered around the selected carrier frequency of the RF transmitter. In the following, the carrier frequency will be indicated by FC. Since BPSDM is a well-known technique, for further information on the implementation of BSPDM, those skilled in the art can refer to the technical literature. In other portions of this specification, a specific embodiment of a simulated bandpass ΔΔ modulator will also be described.

Thus, the modulation device of Figure 2 includes a bandpass ΔΔ modulator 10 configured to receive and process a baseband signal 6. The band pass Δ modulator 10 includes a first quantizer 11 that operates at an oversampling clock rate F1 to deliver an intermediate signal 12 at the output. As shown, the oversampling ratio M can be between 10 and 30. At up to 5% of the SDM band, the bandpass ΔΔ modulator 10 typically includes an integration stage to the 3rd or 4th order to achieve a signal-to-noise of about 60 dB or higher over 5% of the SDM band. ratio.

Therefore, the intermediate signal 12 is a quantized complex signal, which is at each F1 clock. The cycle takes the quantized state within a given complex bundle 20. In an embodiment, the quantization state of the intermediate signal 12 is a 6-bit coded complex state, that is, 3 bits are used for the I component and 3 bits are used for the Q component. FIG. 3 will show a complex bundle 20 of quantized states of the intermediate signal 12 in this embodiment. Of course, the quantizer 11 can also produce a different number of states, i.e., result in a richer or poorer cluster.

Next, the random access memory 13 is provided to store the symbol map 14 and the digital predistortion table 15. At the memory address associated with the current state of the intermediate signal 12, the symbol map 14 is accessed at each F1 clock cycle to deliver the quantized symbols stored at the address, i.e., pulse code 16. The pulse code 16 encodes a predetermined pulse sequence segment, and when the pulse code 16 is received in each F1 clock cycle, the predetermined pulse sequence segment code is generated by the pulse generator 17 as the time domain pulse signal 7. The pulse generator 17 operates at a second oversampling frequency F2 such that the shortest pulse produced is equal to the F2 clock period.

In an embodiment, the pulse code 16 is a binary word having a word length equal to the oversampling ratio N, the pulse generator 17 is a sequencer, and the pulse generator 17 generates a unit quasi-pulse sequence fragment by serialization of the pulse code 16. 30, that is, the binary amplitude coded signal according to the second oversampling frequency F2. A description of the two pulse code 16 and the oversampled pulse sequence segment 30 is shown in FIG.

Similarly, in the memory address associated with the current state of the intermediate signal 12, the digital predistortion table 15 is accessed during each F1 clock cycle to deliver the complex predistortion symbols stored at the address, ie, the complex number Power factor 18. The complex power factor 18 is fed back to the bandpass ΔΔ modulator 10 via the feedback loop to provide pre-distortion as a direct form of the intermediate signal 12.

It will be appreciated that, depending on the above-described effects, a large variety of pulse sequences that are largely dependent on the manner in which the symbol map 14 is clustered can be generated. The symbol map 14 operates like a dictionary, i.e., a pulse codebook, which is a predefined set of pulse sequence segments that ultimately define the time domain pulse signal 7. Therefore, the above system is highly applicable. In particular, the selection of the pulse codebook can be optimized by the number limits and requirements of the application shape.

Referring to Fig. 21, a method for selecting a pulse codebook and thus filling the symbol mapping table 14 and the digital predistortion table 15 will be explained. The codebook is selected such that all quantized complex states of the intermediate signal 12 are properly represented. In the following, it is assumed that the intermediate signal 12 is limited by a fixed envelope signal. Therefore, the quantized state of the intermediate signal 12 is limited to at least a statistically significant manner within a single circle representing the nominal signal power. This single circle is indicated by the code 21 in FIG.

The pulse codebook selection is an offline process that begins with the selection of the initial set of candidate pulse sequence segments in step 40. This initial selection will more or less take into account the required limitations, that is, to obtain a larger or smaller initial set of candidate pulse sequence segments.

The limit to be considered is the binary word length of the pulse code. According to a single level pulse, the executable binary word length is at most equal to the oversampling ratio N. For the sake of explanation, in the following, it will be assumed that the binary word length is equal to the oversampling ratio N.

If the word length is the only imposed limit, then the initial set of 2 ^N (2 N-th power) pulse sequence segments is followed. Figure 4 shows two such pulse sequence segments 30 when N = 8. That is, the length of time of the pulse sequence segment 30 is the F1 clock period and the time granularity of the pulse is the F2 clock period. The information INO of the pulse sequence segment is encoded in the position and width of the pulse in a design called Pulse Position and Width Modulation (PPWM).

Once the initial set of candidate pulse sequence segments is identified, the method proceeds, and in step 41, the complex energy of each of the candidate pulse sequence segments at the RF carrier frequency of F0 is calculated. This calculation is performed via direct Fourier transform of the time domain pulse sequence segments. A complex bundle 25 of candidate pulse sequence segments is obtained. In the embodiment, this cluster is shown in Figures 5 and 6.

At step 42, the selected plurality of plexes 25 are offset and/or scaled to superimpose the dense portion of the complex plexus 25 to the statistically significant portion of the quantized complex state of the intermediate signal 12. The plex offset in the complex plane is equivalent to changing the continuous wave component of the pulse sequence segment that has no actual meaning for the transmitted RF signal. The proportionalization of the bundle is equivalent to changing the peak energy of the pulse.

In an embodiment, step 42 is performed as follows: The center 27 of the original complex bundle 25 is determined by geometric considerations as the center of mass of the useful portion of the plurality of bundles 25. The center 27 is then offset to match the center 22 of the plurality of bundles 20. Then, the largest circle 26 embedded in the plurality of bundles 25 is determined. The bundle 25 is then scaled to match the radius of the circle 26 to the radius of the circle 21. This is equivalent to adjusting the SDM loop and defining the peak energy of the input I-Q signal.

The method proceeds to step 43 where a distance optimization method is applied to each of the complex quantized states within the bundle 20 to find the closest mapper within the cluster 25. Number - as possible potential offset and/or proportionality in the situation. For example, the complex quantized state is selected within the plex 20, then the complex plane distance of the state to each point in the plex 25 is calculated, and the plex point of the plex 25 that minimizes the distance is selected as the mapping symbol. Although the mapping is interpreted in the frequency domain, that is, via the energy of the sampling at the carrier frequency FC, it should be noted that the subsequent selection of the time domain signal, that is, the selection of the subset of candidate pulse sequence segments is taken as Those pulse sequence segments that most closely match the complex energy of the carrier frequency FC with the quantized complex state of the intermediate signal 12. The uncompromised mismatch remaining between the best matching pulse sequence segment and the complex state of the intermediate signal 12 will result in a final quantization noise as a symmetric error of the method. However, the level of this symmetry error is controlled. Of course, since the accessible codebook becomes richer with the growing parameter N, the higher the oversampling ratio N, the lower the symmetric quantization noise will be.

At step 44, for each selected pulse sequence segment, at the address associated with the corresponding quantized complex state of the intermediate signal 12, the complex energy of the carrier frequency FC is stored in the predistortion table 15, and, in the intermediate signal At the address corresponding to the quantized complex state of 12, the pulse code encoded by the pulse sequence segment is stored in the mapping table 14.

Now, the different rules for initial group selection in step 40 will be explained.

The first level rule is to limit the number of signal transitions in the F1 clock cycle to reduce the power consumption in the radio front end 5 and the required amplifier bandwidth. In particular, by limiting the number of 0-1 transitions and the number of 1-0 transitions to each pulse sequence segment, ie a single pulse limit, in this way The number of pulses that are segmented for each pulse sequence is limited to one. As shown, the 37-pulse sequence segment meets a single pulse limit within an unrestricted group of 256 of the 8-bit pulse code. Figure 4 shows the pulse code 00111100 that meets the single pulse limit and the pulse code 00010100 that does not match. Similarly, the 137 pulse sequence segment conforms to a single pulse limit of a 16-bit pulse code.

Figures 5 and 6 further show a single pulse limit, and Figures 5 and 6 show the complex bundle 25 obtained by applying this limit. In these examples, the carrier frequency FC is defined via the frequency ratio FC/F1. The circularity of the plexus 25 is observed and thus the number of pulse sequence segments that can be used within the circle 26 is a function of the ratio R. That is, when R becomes closer to 1/2, the roundness is improved.

Figure 7 shows different selection limits, i.e., defining two pulses per pulse train segment with each pulse having a length less than N/2, i.e., a twin pulse limit. As a result, more information is encoded at the expense of more pulses per carrier cycle. For N = 16, an initial set of 37 ² = 1369 pulse sequence segments is taken. Figure 8 shows the corresponding complex bundle 25.

The selection limit can also be enhanced to emphasize the resulting signal in a particular portion of the spectrum. In the illustrated embodiment of these limitations, the pulse sequence segment 30 is divided into two half segments 31 and 32, and specific rules are applied to define the second half 32.

Figure 9 shows the case where the second half 32 is a uniform zero, i.e., no pulses are allowed in the second half 32. This rule is also used to reduce low power pulse density, such as 6dB back shift.

FIG. 10 shows the case where the second half segment 32 is a copy of the first half segment 31. This rule can be used to reduce spectral noise and images above 0.5F1.

In an embodiment, the effect of video power, the same transmitting device that enhances the increased codebook selection step, employs a codebook resulting from the rules shown in Figures 9 and 10. That is, the codebook of Fig. 9 is used at a lower power, and the codebook of Fig. 10 is used at a higher power. This will reduce the number of pulses per carrier cycle at 2 at lower power and maintain good encoder efficiency, similar to the Doer effect.

In the modified embodiment, the bundles resulting from Figures 9 and 10 are joined in a series in step 40. Therefore, the SDM feedback loop ultimately operates to view the average and peak energy of the input signal 6 to switch from a codebook (Fig. 9) to another codebook (Fig. 10).

Figure 11 shows the opposite of the second half segment 32 being the first half segment 31. This rule is used to reduce the image and spectral noise around the 0 and 2 ^* F1 frequencies, that is, 0 modulo 2 ^* F1. This is a suitable choice for the carrier frequency FC close to F1 and the high pass driver chain in the radio front end 5. In fact, no noise energy exists close to DC, so that it does not pose a risk of envelope reconstruction in the AC-coupled driver chain, helping to keep the chain-keeping binary pulses clean.

Figure 12 shows the second half segment 32 being the complement of the first half segment 31. This rule is used in a similar manner to the condition of Figure 11, and this rule in turn provides appropriate PWM carrier rejection at frequency F1 to improve encoder efficiency. Those filtering effects occur at the expense of doubling the second oversampling clock rate F2 and thus doubling the number of pulses per carrier period and the ratio N (i.e., factor K).

Quantization example

Computer simulation of 4WCDMA radio transmission.

In the first simulation result, the parameters and results are: FC=1.875 GHz; M=2; F1=2 GHz; N=16; F2=32 GHz; K=3.04; ACLR=73.3 dB; unfiltered 60 dB ACLR bandwidth = 88MHz; maximum IBW = 60MHz; code efficiency DC to 2 ^* F1 of unfiltered = 85.1%; DC efficiency to 2 ^* number of filtered F1 = 96.1%; filtered bandwidth = 140MHz 60dB ACLR . The codebook is limited by a single pulse rule in the first half of the segment along with the complementary rule (Fig. 12).

In the second simulation result, the modified parameters are only: FC = 2.125 GHz; M = 0.9412. The results were only modified to: K = 2.73; ACLR = 74 dB; filtered coded efficiency of DC to 2 ^* F1 = 96.9%.

It has been observed that the PPWM bundle can have strong efficiency and shift the ACLR towards the input. Efficiency and ACLR slowly degrade as the first 10 dB shifts back.

Figure 13 shows the spectrum of the pulsed time domain signal 7 taken in a similar simulation scenario, where: FC = 2.125 GHz; F1 = 2 GHz; N = 32; F2 = 64 GHz. The codebook is limited by a single pulse rule in the first half of the segment along with the complementary rule (Fig. 12).

In the above, reference is made to a single level pulse sequence. However, similar mapping and coding methods can be applied to a richer cluster that increases the quantization pulse level dimension (i.e., the pulse slice segment containing the multi-level pulse). It will be appreciated that doubling the number of amplitude states of the pulses will result in a secondary expansion of the plexus. These multi-level pulse sequences are particularly suitable for driving multi-drop power amplifiers, where The multi-level quasi-pulse sequence is ultimately converted into a plurality of parallel single-level pulse sequences such that each parallelized single-level pulse sequence drives the respective amplifier branches such that only a portion of the total power is switched.

An embodiment of the multi-level principle described above will be explained with reference to Figs.

In Fig. 14, the simulation results show a 3-bit quasi-pulse sequence suitable for driving a 2-way symmetric pulse feed type amplifier. The simulation parameters are: N=8; FC=2.125 MHz; F1=2 GHz; F2=16 GHz. A codebook that is constrained by a single pulse rule in the first half of the segment along with the complementary rule (Fig. 12) produces two independent parallel single level pulse sequences. These parameters mean a codebook that produces 11 pulse sequences with 2 pulses per column. The summation result is a pulse sequence of 3 relative values -1; 0; +1, that is, a total of 51 multi-level pulse sequences in the resulting codebook. Designed in a three-state class S to implement a 2-way symmetrical pulse feed amplifier.

Some of the characteristics of the old multi-branch Doe's amplifier can be recovered by using the two branches on the amplitude. The following example mimics a 2-way asymmetric 1:2 pulse feed Doer and a 3-way symmetric pulse feed Doer.

In the 2-way asymmetric 1:2 pulse feed doer case, a two independent parallel single level pulse sequence is generated by a single pulse rule in the first half segment that is constrained by the complementary rule (Fig. 12). These parameters mean a codebook that produces 11 pulse sequences with 2 pulses per column. The second sequence has double the amplitude compared to the first sequence. Therefore, two identical but uncorrelated pulse sequence fragment codebooks are generated, which are both binary levels, 0-1 and 0-2, respectively. The result of the summation is a pulse sequence of 4 relative values of -1.5; -0.5; +0.5; +1.5, that is, a total of 121 multi-levels in the resulting codebook. Pulse sequence. The best average K = 1.45 pulses per carrier cycle was observed. Asymmetric Doer is simulated by feeding each column to the power amplifier branch.

Figure 15 shows the case of a 3-way symmetric pulse feed Doer-Il amplifier. Using the same codebook and plexes as the previous 2-way asymmetry, the only difference is the power amplifier feed. That is, the design uses a three-phase branch in the Doge circuit. At the same clock speed F2 = 16 GHz, the initial 3-bit quasi-pulse sequence is converted into a 3-binary pulse sequence. This results in a main pulse signal and two equal sharps that act on the upper and lower envelope peaks, respectively. The other parameters of the simulation are N=8; FC=2.125MHz and F1=2GHz.

Figure 16 shows another embodiment of a modulation device 1 comprising an increased FIR filter for digital filtering. Elements that are the same as or similar to Figures 1 and 2 are denoted by the same reference numerals.

The power amplifier 2 is made up of 6 small drivers and power transistors having 6 identical finger sets. Spatial FIR filtering is added in the modulation device 1 with low quantization and a limited number of taps to map to the 6-distribution driver 19 of the last-level transistor finger. The summing point of the finger, that is, the amplifier drain 9 is the filter output.

The figure shows an example with 4 taps and 6 identical fingers; 4 taps (1/2 1 1 1/2) are equally spaced to produce a periodic frequency response: one harmonic falls to FC, with some close to the PPWM carrier Band and SDM image modulus F1.

The tap delay 35 can be programmed by a digital delay tree and each tap-sequencer. The configuration provides programmability to accommodate FC and IBW targets as well as compensating for amplifier geometry delay and phase imbalance between fingers, especially for larger crystals Grain and power.

The FIR performance is very robust to tap a finger gain mismatch that is slightly larger than the finger mismatch on the same power transistor die, for example up to 20%. Filter tap 35 removes SDM PPWM noise in, for example, the RX band or the adjacent TX band. However, since the cancelled TX noise simply disappears in the final stage grain of the PA, it does not increase the encoder efficiency.

In the foregoing, a method for calculating complex energy for storage in the predistortion table 15 is explained. In an embodiment, the predistortion table 15 is populated via experimental measurements of the complex energy of the selected pulse sequence segments at the carrier frequency FC. These measurements result in consideration of the advantages of the analog characteristics of the radio front end 5, such as limited transition slope, memory utility of the drive, and the like.

In fact, the analog nature of the radio front end 5 is such that the spectrum of the emitted electromagnetic field is slightly different from the spectrum of the output signal 7 of the pulse generator 17. However, considering the pulse signal actually transmitted by the antenna 4 instead of its ideal digital representation, a better efficiency of the predistortion feedback loop can be achieved. For this purpose, the complex energy coefficient 18 is determined or refined via experimental measurements performed as follows: Σ Δ modulator 10 is controlled to repeat a given pulse sequence segment during an appropriate measurement period, during an appropriate measurement period, A detector is employed to measure the amplitude and phase of the transmit field at approximately the carrier frequency FC. The measured phase is the relative phase with respect to a given reference, which may be, for example, any pulse sequence of a codebook having a non-zero energy and a measurable phase at carrier frequency FC. For error minimization, the reference pulse should be a pulse that preferably has a high energy at the carrier frequency FC, i.e., preferably around the bundle. Repeat processing of all pulse sequence segments of the codebook and thus Fill the predistortion table 15.

While the above description is directed to methods for selecting a particular codebook optimized for a particular application, it should be understood that Tables 14 and 15 are also populated to produce well-known coded designs, such as conventional PWM coded designs. Since PWM generation is well known in the art, this alternative is not required to be further detailed.

Turning now to Figures 17 and 18, an embodiment of a simulated band pass Δ Δ modulator will be described. Elements having functions similar to those previously described in Figures 2 and 3 are indicated by the same code number plus 100.

The basic concepts in Figures 17 and 18 are to simulate bandpass by using a low pass ΔΔ modulator 110 and a numerically controlled oscillator (NCO) 50 for performing two-bit frequency transposition at the carrier frequency of a useful FC. The delta modulator, the binary digit transposition is the first digit transposition performed by the first mixer 70 between the first quantizer 111 and the mapping table 114, and by the ΣΔ modulator 110. The second mixer 71 in the feedback loop performs a second digit transposition.

The low pass Δ modulator 110 has a clean bandwidth centered at DC (0 Hz) and having a width of approximately 5% of the oversampling frequency F1, and operates to reject quantization noise outside of the low frequency band.

The numerically controlled oscillator 50 is a digital generator that produces a discrete value representation of the sinusoidal waveform oscillating at a controlled frequency, clock discrete time. In Fig. 17, the NCO 50 receives the clock signal at the oversampling frequency F1 and the control signal set to apply the carrier frequency of the useful FC. That is, the NCO 50 delivers a complex number of digits 51 at each F1 clock cycle, the complex number of digits 51 approximating the instantaneous value of the complex sinusoidal carrier oscillating at the carrier frequency FC.

The mixer 70 is a complex multiplier that multiplies the quantized complex intermediate signal 112 delivered by the quantizer 111 by a complex number of bits 51 to produce an up-converting intermediate signal 52. Since the output signal 51 is coded with a finite number of bits, the up-converting intermediate signal 52 is also coded with a finite number of bits and is used to access the symbol map 114 and the digital pre-distortion table 115 as described above. However, the difference from the above implementation is that the number of complex quantized states of the up-conversion intermediate signal 52 will generally be much higher than the number of states of the intermediate signal 112. This point will be explained with reference to FIG.

In FIG. 20, the complex bundle of intermediate signals 112 is assumed to be identical to the complex bundle of intermediate signals 12. Figure 20 is a true representation of the instantaneous phase angle by rotating the complex bundle 20 of Figure 3. And the cluster 120 is obtained to represent the intermediate signal 112 and the plural in the mixer 70. Multiply. It should be noted that for each phase of the NCO output signal 51, a respective rotated cluster 120 is obtained.

Therefore, in order to develop the symbol mapping table 114 and the digital predistortion table 115 in the same manner as described above, for each quantization state of the quantizer 111 in each and every possible rotated cluster 120, the table must be filled so that the table The size is equal to the phase angle The factor expansion of the number of discrete values. This observation means that the instantaneous phase is coded with a finite number of bits such as 4 bits or 16 discrete values, otherwise the memory access time becomes too long and interferes with SDM stability.

Since the digital predistortion table 115 is filled with complex energy coefficients derived from the rotated bundle 120, the mixer 71 must operate to multiply the retrieved coefficients before feeding the retrieved coefficients back to the SDM modulator 110. The conjugate value of the output signal 51 is output.

Since the complex mixers 70 and 71 are complex digital multipliers, they cannot be implemented at a useful carrier frequency such as several GHz without a large delay that jeopardizes the bandwidth of the SDM modulator 110 and the stability of the feedback loop. The action is a conceptual view. Referring to Figure 18, a preferred embodiment in accordance with the same concept will now be described in which the operations of multipliers 70 and 71 are replaced by pre-computations engulfed in symbol mapping table 114 and digital predistortion table 115.

In FIG. 18, the NCO 60 delivers a time domain quantization signal 61, and the time domain quantization signal 61 represents the instantaneous phase of the carrier oscillating at the selected carrier frequency FC. . In an embodiment, the quantized phase signal 61 is coded in 4 bits. Now, the address field for the pulse code selection is increased by, for example, a 4-bit NCO bit representing the quantized instantaneous phase of the digital local oscillator, such that the post quantizer mixer 70 is implicit. This will be better understood by comparing Figures 3 and 20 again.

In FIG. 3, the quantization state of the plex 20 is uniquely represented by a 6-bit address such as the address 101101 for the circular state 65. In contrast, in Figure 20, it should be noted that for the phase angle Each discrete value has a rotated cluster 120, and the quantization state of the cluster 120 is uniquely represented by a 10-bit address such as address 101101/0001 for the circular state 165. This is because the amplitudes of the components I and Q and the instantaneous phase angle must all be combined to define individual states.

In view of the above, the table 114 is filled with each and every rotation bundle 120 using the codebook selection method described with reference to FIG. As a result, the size of the codebook will be expanded by a factor of 16 for the 4-bit coded phase signal 61.

Regarding the resulting complex energy coefficient 118, it must be multiplied by the conjugate factor before being stored in the digital predistortion table 115. Instead of using the mixer 71.

For the other portions, the operation of the memory 113 and the pulse generator 117 is similar to the operation of the memory 13 and the pulse generator 17 and requires no further explanation.

The above method for simulating a local oscillator can shift the clean bandwidth of the low pass SDM modulator 110 to the desired RF carrier frequency band limited only by the oversampled clock rate F1. The NCO 50 or 60 controls the spectral transition such that the carrier frequency is selected by the NCO 50 or 60 anywhere between 0 and F1. Depending on the particular bandpass pulse sequence (see Figure 12), even the second Nyquist zone can be selected.

As a result, the sub-GHz cellular frequency band is synthesized with the same instantaneous clean bandwidth as the upper frequency band of 2 GHz and the same SDM clock rate F1. In an embodiment, a digital radio transmitter is obtained that is suitable for use in fixed clocks covering 700 to 2200 MHz and using rates F1 and F2.

For better frequency resolution, the number of bits of the NCO output signal 61 must be large. For example, a 10 MHz step for a F1 = 2 GHz clock means that the phase is coded in 8 bits. The expansion factor of 256 is such that the mapping table is followed by an issue of access time at this high speed. Therefore, the instant phase signal is preferably limited to 3 or 4 bits.

Referring to Figure 19, another embodiment in accordance with the same principles employs a whisker (MASH) noise shaping filter 80 to generate an NCO phase signal 61. That is, the control signal 63 of the NCO 60 is delivered via a smoothing engine made of a Mash ΣΔ filter 80, which is easily transported at a high speed pipeline. There is no stability issue. The whisker filter 80 receives, for example, a 7-bit coded refined carrier frequency value FC, and receives the most efficient bit at the first input 81 and the least significant bit at the second input 82. Although the fourth-order filter is shown, the second or third order is sufficient for good phase and frequency spur stabilization.

An advantage of the analog bandpass ΔΔ modulator of Figures 17 through 19 is that the complete SDM structure includes the function of transposing the baseband input signal 6 or 106 at the useful RF carrier frequency. It should be noted that the band pass ΔΔ modulator 10 of Fig. 2 can be made differently. However, some bandpass Δ-Δ modulation designs require frequency transposition before entering the SDM modulator. In other words, some of the original bandpass SDM architectures require an input signal 6 that is not a baseband signal 6 but a version that has been transposed at the carrier frequency FC, thus requiring a higher oversampling rate F1.

The modulation device may be a hardware mechanism such as an ASIC, or a combination of a hard body and a soft body such as an ASIC and an FPGA, or at least one microprocessor having a software module disposed therein, and at least one memory.

The invention is not limited to the embodiment. The scope of the appended claims is to be construed as being limited by the details

The use of verbs such as "to include" and "to include" and the singular words does not exclude elements or steps other than the elements or steps recited in the claims. In addition, the use of the articles "a" or "an" or "an"

In the scope of the patent application, the code placed in the bracket should not be construed as limiting the scope of the claim for the scope of the patent application.

6‧‧‧Multiple baseband signals

7‧‧‧ Frequency conversion time domain pulse signal

10‧‧‧With pass Σ Δ modulator

11‧‧‧First quantizer

12‧‧‧Intermediate signal

13‧‧‧ Random access memory

14‧‧‧ symbol mapping table

15‧‧‧Digital predistortion symbol

16‧‧‧ pulse code

17‧‧‧Pulse generator

18‧‧‧Multiple power factor

F1‧‧‧First oversampling clock rate

F2‧‧‧Second oversampling clock rate

Claims (18)

A method of generating a symbol mapping table (14) in a memory (13) for outputting a finite number of quantized complex output states of a △ Δ modulation device (10) operating at a first oversampling clock rate (F1) Mapping to quantized symbols, the method comprising: selecting a carrier frequency (FC); selecting (40) an initial set of pulse sequence segments (30) having a time granularity corresponding to a second oversampled clock rate (F2); determining the carrier a frequency domain complex energy coefficient of a pulse sequence segment of an initial group of frequencies (FC); selecting (43) a subset of pulse sequence segments, the subset of the pulse sequence segments having a complex frequency energy coefficient (25) in the frequency domain of the carrier frequency Approximating the quantized complex output state (20) of the △ Δ modulation device such that each quantized complex output state is uniquely mapped to the pulse sequence segment of the subset; for each pulse sequence segment of the quantized complex output state map (30) The quantized symbol (16) encoding the burst sequence segment is recorded (44) at a memory address associated with the quantized complex output state. For example, in the method of claim 1, and in order to generate a digital predistortion table (15) in the memory, the method further comprises: for each pulse sequence segment (30) mapped to the quantized complex output state, a function of the frequency domain complex energy coefficient (25) of the pulse sequence segment of the carrier frequency to determine a complex predistortion symbol; and recording (44) the predistorted symbol in the quantized complex output state The associated memory address. The method of claim 1, wherein the selecting a subset of the pulse sequence segments comprises: calculating a quantized complex output state (20) of the Σ Δ modulation device and the frequency domain complex energy coefficient of each pulse sequence segment (25) a complex plane distance between; mapping the quantized complex output state to a sequence of pulse sequences that result in a minimum complex plane distance; and discarding a sequence of pulse sequences that are not mapped to any quantized complex output state. The method of claim 3, further comprising: determining a center of a complex bundle of frequency domain complex energy coefficients at the carrier frequency; shifting the complex bundle by a complex number such that a center of the complex bundle and the Σ Δ The center of the second bundle formed by the quantized complex output states of the modulation device substantially matches. The method of claim 3, wherein the method further comprises: determining a first circle geometrically embedded in the complex cluster of frequency domain complex energy coefficients of the carrier frequency; and scaling the complex cluster to The radius of the inscribed circle is substantially equal to the peak energy of the quantized complex output state of the △Δ modulator. The method of claim 1, wherein the initial group of the selected pulse sequence segments comprises: selecting a binary word length; A set of width modulation and/or position modulation pulse sequence segments uniquely represented by a binary word having the selected binary word length is constructed. The method of claim 1, wherein the step of selecting the initial set of pulse sequence segments comprises: selecting a limit; and constructing a pulse sequence segment set that satisfies the width modulation and/or position modulation of the limit. The method of claim 7, wherein the limit defines a fixed number of pulses per segment of the pulse sequence, in particular one pulse per pulse sequence segment or two pulses per pulse sequence segment. The method of claim 7 or 8, wherein the limitation defines a logical relationship between the first half and the second half of the pulse sequence segment, in particular defining the first half of the pulse sequence segment and Equality, sign opposite, or complementarity between the second half. The method of claim 7 or 8, wherein the limit defines a fixed value for the second half of the pulse sequence segment. The method of claim 1, wherein the pulse in the pulse sequence segment comprises a single level pulse. The method of claim 1, wherein the pulse in the pulse sequence segment comprises a multi-level pulse, in particular a pulse having a two or three amplitude state other than zero. The method of claim 1, wherein determining the frequency domain complex energy coefficient of the pulse sequence segment at the carrier frequency comprises calculating a Fourier transform of the pulse sequence segment at the carrier frequency. The method of claim 1, wherein determining the frequency domain complex energy coefficient of the pulse sequence segment at the carrier frequency comprises feeding the pulse sequence segment to a radio frequency front end for transmitting the electromagnetic field and by measuring the emission around the carrier frequency The amplitude and phase of the electromagnetic field measure the energy content of the electromagnetic field emitted at the carrier frequency. A signal modulation device for providing an output signal to a radio frequency front end, the device comprising: a memory comprising a symbol mapping table generated by the method according to any one of claims 1 to 14; and a pulse generator ( 17,117), configured to receive a quantized symbol (16) selected in the symbol map of a memory address associated with a quantized complex output state of the △ delta modulation device (10), wherein the pulse generator is configured to The quantized complex output state map and the sequence of pulse sequences encoded by the received quantized symbol (16) are generated. A method of using a signal modulation device according to claim 15 wherein the memory further comprises a digital predistortion table produced by the method according to claim 2, the method comprising: using the first oversampling The clock rate (F1) receives the intermediate signal; reads the quantized symbol in the symbol map of the memory address associated with the current quantized complex state of the intermediate signal; reads the current quantized complex state with the intermediate signal a predistorted symbol in the digital predistortion table of the associated memory address; encoded by the pulse generator (17, 117) to be encoded by the quantized symbol a pulse sequence segment; and, providing a predistortion symbol as a feedback signal to the △Δ modulator. The method of claim 16, wherein the generated pulse sequence segment comprises a multi-level pulse, the method further comprising converting the multi-level pulse sequence segment into a plurality of parallel unit standards according to a multi-branch power amplifier design The pulse sequence segments and the respective unit quasi-pulse sequence segments are fed to corresponding feed branches of the power amplifier. The method of claim 17, wherein the multi-branch power amplifier design is selected from the group consisting of a two-way symmetric pulse feed, a two-way asymmetric 1:2 pulse feed Doer, and a three-way symmetric pulse feed Doer. In the group.