TWI550793B - Chip fabrication process and structure thereof - Google Patents

Description

Wafer process and its structure

SUMMARY OF THE INVENTION The present invention relates to a wafer process and a structure thereof, and more particularly to a process for forming a bonding bump electrically connected to a redistribution line on one side of a wafer by a section of a redistribution line.

In order to increase the computing speed, function or increase the data storage space of electronic products, two or more wafers are usually stacked vertically to form a wafer stack structure, but since the stacked chips will cause an increase in the overall package thickness, it is not advantageous. In order to thinen the market thickness of electronic products, if the adjacent wires are electrically connected by solder wires, the height of the bonding wires will also increase the overall package thickness, which is not conducive to the market demand for thinning the thickness of electronic products.

The main object of the present invention is to provide a wafer process including a "provide a wafer" step, the wafer having a plurality of wafers and a plurality of dicing streets, each of the wafers having a first upper surface and a first lower surface and a plurality of guiding pads exposed on the first upper surface, the cutting props having a second upper surface and a second lower surface, each of the second upper surfaces being located between the adjacent first upper surfaces, and then performing Forming a metal layer on the first upper surface, the second upper surface, and the conductive pad, the metal layer is electrically connected to the conductive pad, and then "patterning the metal layer" Step, the metal layer is patterned to form a plurality of redistribution lines, each of the redistribution lines having a first line segment and a second line segment connected to the first line segment, the first line segment being a first line segment One end portion is electrically connected to the guiding pad, the second line segment is retained on the second upper surface of the cutting channel, and then, a step of "removing the second line segment" is performed, and the second line is removed At the same time, a groove is formed at the same time. Cutting the second upper surface, and after removing the second line segment, forming the first line segment with a second end portion, the second end portion having a cross section facing the other first line a section of the section substantially flush with an inner surface of the recess, and thereafter performing a step of "forming an engaging projection" formed on the section perpendicular to the cross-sectional direction, The bonding protrusion protrudes from the inner surface of the groove and is suspended above the groove, and then, a step of “forming a cover layer” is performed, the cover layer covers the joint protrusion, and finally “removing the cutting path” In the step of singulating the wafers into individual wafers, each of the wafers has a side connecting the first upper surface and the first lower surface, and the bonding protrusion protrudes from the side surface.

Another object of the present invention is to provide a wafer process including a "provide a wafer" step, the wafer having a plurality of wafers and a plurality of dicing streets, each of the wafers having a first upper surface and a first lower surface And a plurality of guiding pads exposed on the first upper surface, the cutting props having a second upper surface and a second lower surface, each of the second upper surfaces being located between the adjacent first upper surfaces, and then forming a plurality of redistribution lines, each of the redistribution lines having a first line segment and a second line segment connected to the first line segment, the first line segment being electrically connected to the lead by a first end portion a pad, the second line segment is retained on the second upper surface of the scribe line, and then performing a "remove second line segment" step, and when the second line segment is removed, a groove is simultaneously formed Cutting the second upper surface, and after removing the second line segment, forming the first line segment with a second end portion, the second end portion having a cross section, the cross section facing the other first a line segment that is substantially flat with an inner surface of the groove After that, a step of "forming an engaging convex portion" is formed on the cross section perpendicular to the cross-sectional direction, the engaging convex portion protrudes from the inner surface of the recess and is suspended Above the groove, a step of "forming a cover layer" is performed, the cover layer covers the joint protrusion, and finally a "removing the cut track" step is performed to singulate the wafers into individual wafers, each The wafer has a side connecting the first upper surface and the first lower surface, and the engaging protrusion protrudes from the side.

The present invention forms the bonding protrusion electrically connected to the redistribution line on the side of the wafer by the cross section of the redistribution line, and covers the bonding protrusion with the cover layer, and the wafer can cover the same The layer is electrically connected laterally to another wafer or electronic component to avoid increasing the overall package thickness, and the cover layer can increase the holding force of the bonding protrusion to prevent the bonding protrusion from coming off the section of the redistribution line.

Please refer to FIGS. 1 to 6 , which are a preferred embodiment of the present invention. A wafer process includes the step of “providing a wafer” in FIG. 1 and the step of “forming a metal layer” in FIG. The step of "patterning the metal layer" in the figure, the step of "removing the second line segment" in FIG. 4, the step of "forming a bonding protrusion" in FIG. 5, the step of "forming a covering layer" in FIG. 6, and Step 7 of "Remove the cutting lane".

First, referring to FIG. 1 , in the step of “providing a wafer 100 ”, the wafer 100 has a plurality of wafers 110 and a plurality of dicing streets 120 , each of the wafers 110 having a first upper surface 111 , a first a lower surface 112 and a plurality of guiding pads 113 exposed on the first upper surface 111, the cutting channel 120 has a second upper surface 121 and a second lower surface 122, each of the second upper surfaces 121 being adjacent to each other Between the first upper surfaces 111 of the wafer 110.

Next, referring to FIG. 2, in the step of "forming a metal layer 130", the metal layer 130 is formed on the first upper surface 111 of each of the wafers 110 and the second upper surface 121 of each of the dicing streets 120. The metal layer 130 is electrically connected to the conductive pad 113. In this embodiment, the material of the metal layer 130 may be selected from copper, aluminum, or the like.

Next, referring to FIGS. 2 and 3, in the step of "patterning the metal layer 130", the metal layer 130 is patterned to form a plurality of redistribution lines 131, each of which has a first line. The first line segment 131a is electrically connected to the guiding pad 113 by a first end portion 131c, and the second line segment 131b is retained in the second line segment 131b. The second upper surface 121 of the scribe line 120.

Alternatively, in different embodiments, the steps of "forming a metal layer 130" and "patterning the metal layer 130" may be omitted, and may be directly applied to the first upper surface of each of the wafers 110 by plating, sputtering, or the like. 111. The second upper surface 121 of each of the dicing streets 120 and the conductive pad 113 form the redistribution lines 131, and each of the redistribution lines 131 has a first line segment 131a and a connection thereto. a second line segment 131b of the first line segment 131a. The first line segment 131a is electrically connected to the guiding pad 113 by a first end portion 131c. The second line segment 131b is retained in the cutting path 120. Two upper surfaces 121.

Next, referring to FIG. 4, in the step of "removing the second line segment 131b", the embodiment removes the second line segment 131b by a cutting tool 200, and the cutting tool 200 is simultaneously at the cutting path 120. The second upper surface is formed with a recess 123, and after the second line segment 131b is removed, the first line segment 113a is formed with a second end portion 131d having a cross section 131e. The section 131e faces the other first line segment 113a. In the present embodiment, the section 131e is substantially flush with an inner surface 123a of the recess 123.

Next, referring to FIG. 5, in the step of "forming a joint convex portion 140", the joint convex portion 140 is formed on the cross section 131e in a direction perpendicular to the cross section 131e, and the joint convex portion 140 is convex. The inner surface 123a of the recess 123 is suspended above the recess 123. In this embodiment, the joint protrusion 140 can be formed on the cross section 131e by electroplating or the like. The material of the joint protrusion 140 can be It is made of copper, aluminum or other conductive materials.

Next, referring to FIG. 6 , in the step of “forming a cap layer 150 ”, the cap layer 150 may be formed by a plating process, and the material of the cap layer 150 may be selected from nickel (Ni), silver (Ag). a conductive metal such as gold (Au), palladium (Pd), platinum (Pt), tin (Sn), or zinc (Zn) or a combination of the foregoing conductive metals. In the present embodiment, the cover layer 150 covers at least the layer The bonding protrusion 140 is preferably covered by the first layer 131a at the same time to prevent the bonding protrusion 140 from coming off the section 131e of the redistribution line 131.

Next, referring to FIG. 7, in the step of "removing the dicing street 120", the first lower surface 112 of the wafer 110 and the second lower surface of the dicing street 120 are in a polishing process. Surface 122 is ground to remove the dicing street 120, or in various embodiments, the dicing street 120 can be removed by another cutting tool to singulate the wafers 110 into individual wafers. Each of the wafers 110 has a side surface 114 connecting the first upper surface 111 and the first lower surface 113, and the bonding protrusion 140 protrudes from the side surface 114. The wafer 110 can be electrically connected laterally to the covering layer 150. A wafer or electronic component to avoid increasing the overall package thickness.

Referring to FIG. 7, a wafer structure obtained by the wafer process of the present invention comprises a wafer 110, a plurality of redistribution lines 131, a bonding protrusion 140 and a cover layer 150. The wafer 110 has a first The upper surface 111, a first lower surface 112, a side surface 114 connecting the first upper surface 111 and the first lower surface 112, and a plurality of guiding pads 113 exposed on the first upper surface 111, the plurality of The redistribution line 131 is formed on the first upper surface 111 of the wafer 110. Each of the redistribution lines 131 has a first line segment 131a. The first line segment 131a has a first end portion 131c and a second end portion. The first line segment 131a is electrically connected to the guiding pad 113 by the first end portion 131c. The second end portion 131d has a section 131e on the side surface 114 of the wafer 110. The bonding protrusion 140 is formed. Formed on the section 131e along a direction perpendicular to the section 131e, and the bonding protrusion 140 is suspended above the side surface 114 of the wafer 110. The cover layer 150 covers the bonding protrusion 140 and is suspended on the side surface. Above the 114, the wafer 110 can be electrically connected to the other layer by the cover layer 150. Or an electronic component to avoid increasing the overall package thickness. Preferably, the cover layer 150 is stretched to the first line 131a, and the cover layer 150 can increase the holding force of the joint protrusion 140 to avoid the joint protrusion. The portion 140 is separated from the section of the redistribution line.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧ wafer
110‧‧‧ wafer
111‧‧‧First upper surface
112‧‧‧First lower surface
113‧‧‧ Guide pads
120‧‧‧ cutting road
121‧‧‧Second upper surface
122‧‧‧Second lower surface
123‧‧‧ Groove
123a‧‧‧ inner surface
130‧‧‧metal layer
131‧‧‧Redistributed lines
131a‧‧‧First line segment
131b‧‧‧second line segment
131c‧‧‧ first end
131d‧‧‧second end
Section 131e‧‧‧
140‧‧‧Joint projection
150‧‧‧ Coverage
200‧‧‧ cutting tools

1 to 7 are schematic cross-sectional views showing a wafer process of the present invention.

110‧‧‧ wafer

111‧‧‧First upper surface

112‧‧‧First lower surface

113‧‧‧ Guide pads

114‧‧‧ side

131‧‧‧Redistributed lines

131a‧‧‧First line segment

131c‧‧‧ first end

131d‧‧‧second end

Section 131e‧‧‧

140‧‧‧Joint projection

150‧‧‧ Coverage

Claims (9)

A wafer process includes: providing a wafer having a plurality of wafers and a plurality of dicing streets, each of the wafers having a first upper surface, a first lower surface, and a plurality of exposed on the first upper surface a guiding pad, each of the cutting props has a second upper surface and a second lower surface, each of the second upper surfaces being located between the adjacent first upper surfaces; forming a metal layer, the metal layer being shaped The first upper surface of the wafer, the second upper surface of each of the dicing streets, and the conductive pad, the metal layer is electrically connected to the conductive pad; the metal layer is patterned, and the metal layer is patterned to form a plurality Each of the redistribution lines has a first line segment and a second line segment connected to the first line segment, the first line segment being electrically connected to the guiding pad by a first end portion, The second line segment is retained on the second upper surface of the cutting lane; the second line segment is removed, and when the second line segment is removed, a recess is simultaneously formed on the second upper surface of the cutting lane And removing the second line segment, forming the first line segment a second end portion having a cross section facing the other first line segment, the cross section being substantially flush with an inner surface of the recess; forming an engaging convex portion, An engaging convex portion is formed on the cross section perpendicular to the cross-sectional direction, the engaging convex portion protrudes from the inner surface of the groove and is suspended above the groove; forming a covering layer, the covering layer is covered The bonding protrusions; and removing the dicing lines to singulate the wafers into individual wafers, each of the wafers having a side connecting the first upper surface and the first lower surface, and the bonding convex portion is convex Out of this side. The wafer process of claim 1, wherein the cover layer simultaneously covers the wafer The first line segment. The wafer process of claim 1, wherein the cover layer is selected from the group consisting of nickel (Ni), silver (Ag), gold (Au), palladium (Pd), platinum (Pt), and tin (Sn). , zinc (Zn) conductive metal. A wafer structure comprising: a wafer having a first upper surface, a first lower surface, a side connecting the first upper surface and the first lower surface, and a plurality of surfaces exposed on the first upper surface a first plurality of redistribution lines formed on the first upper surface of the crystal, each of the redistribution lines having a first line segment having a first end and a second end The first line segment is electrically connected to the guiding pad by the first end portion, the second end portion has a cross section on the side surface, and an engaging convex portion is formed along the direction perpendicular to the cross section. And overhanging the side of the wafer; and a cover layer covering the joint protrusion. The wafer structure of claim 4, wherein the cover layer extends over the first line segment. The wafer structure of claim 4, wherein the cover layer is selected from the group consisting of nickel (Ni), silver (Ag), gold (Au), palladium (Pd), platinum (Pt), and tin (Sn). , zinc (Zn) conductive metal. A wafer process includes: providing a wafer having a plurality of wafers and a plurality of dicing streets, each of the wafers having a first upper surface, a first lower surface, and a plurality of exposed on the first upper surface a guiding pad, each of the cutting props has a second upper surface and a second lower surface, each of the second upper surfaces being located between the adjacent first upper surfaces; forming a plurality of redistribution lines, each of the redistribution lines Having a first line segment and a connection to the a second line segment of the first line segment, the first line segment is electrically connected to the guiding pad by a first end portion, and the second line segment is retained on the second upper surface of the cutting channel; a second line segment, when removing the second line segment, simultaneously forming a groove on the second upper surface of the cutting path, and forming the first line segment with a second end portion, the second end portion having a section facing the other first line segment, the section being substantially flush with an inner surface of the groove; forming an engagement protrusion forming the joint protrusion perpendicular to the section direction The bonding protrusion is connected to the cross section and suspended above the groove; forming a cover layer to cover the bonding protrusion; and removing the cutting path to singulate the wafers into individual wafers, each The wafer has a side connecting the first upper surface and the first lower surface, and the engaging protrusion protrudes from the side. The wafer process of claim 7, wherein the cover layer covers the first line segment. The wafer process of claim 7, wherein the cover layer is selected from the group consisting of nickel (Ni), silver (Ag), gold (Au), palladium (Pd), platinum (Pt), and tin (Sn). , zinc (Zn) conductive metal.