TWI547103B - Low density parity-check code decoder and decoding method thereof - Google Patents

Description

Decoder of low density parity check code and decoding method thereof

The present invention is a decoder, and more particularly to a decoder for a low density parity check code and a decoding method thereof.

The data may be destroyed during the transmission process due to the poor reliability of the transmission medium or the interference of external factors, and the effect of the error control coding is to restore the damaged data. Commonly used error correction codes include Hamming Code, Reed Solomon Code, BCH Code (Bose Chaudhuri Hocquengham Code), and Low Density Parity-Check Code. Errors with low-density parity check codes have better error detection and correction capabilities, and can also be decoded at very high rates. In the design of a part of the parallel architecture of the decoder of the conventional low-density parity check code, in order to improve the parallelism of the operation, and in order to avoid the memory access problem of the column block and the column block, the memory is usually The body is divided into memory blocks in units of Cyclic Matrix for operation, and these memory blocks are read or written. However, in this way, during the operation, the storage space of the storage space due to writing or reading will still be encountered.

Therefore, in the case where the low-density parity check code has various advantages, there are still many problems, such as the above-mentioned data collision, circuit area, and computational complexity. In the design of the decoder of low-density parity check code, how to effectively improve is still the goal of future efforts.

The embodiment of the invention provides a decoder for low-density parity check code for decoding encoded data having a bit node and a check node. The decoder includes a computing module and a memory. The computing module includes k arithmetic units and n displacement units, and the memory includes n memory units. The memory is coupled to the computing module. Each of the displacement units is coupled to each of the operation units one-to-many. The memory unit is coupled to the displacement unit. The computing module divides the encoded data into n first bit strings. The i-th computing unit calculates the i-th bit in the first bit string and generates a second bit string, where i=1~k is an integer. The jth displacement unit generates a third bit string from the jth bit of the received second bit string, and shifts the third bit string, wherein j=1~n is an integer. The memory unit is configured to store the shifted third bit string separately. Where k, n≧1, and is an integer.

The embodiment of the invention provides a decoding method for a low-density parity check code, which is used for decoding encoded data having a bit node and a check node. The decoding method includes the steps of: dividing the coded data into n first bit strings; calculating the i-th bit in the first bit string by the i-th operation unit of the k operation units and generating the second bit a string, wherein an integer of i=1~k; the jth bit of the received second bit string generates a third bit string by the jth shift unit of the n shift units, and the third bit The metastring displacement, where j=1~n is an integer; the n third bit strings after the displacement are respectively stored in n memory cells; wherein k, n≧1, and are integers.

In summary, the decoder for low-density parity check code proposed by the embodiment of the present invention and the decoding method thereof can avoid the conventional decoder using low-density parity check code in the process of writing and reading. The resulting data collided. On the other hand, in the decoder architecture proposed by the present invention, the parallelism of the operation of the low density parity check code decoder is improved by dividing the memory into a parallel architecture of a memory block in units of a cyclic matrix. It is also possible to replace the traditional decoder with a switching network. When performing calculations, both writing and reading must use a switching network, and simplify the bit node unit that is conventionally used. And can achieve the effect of avoiding data collision and further shorten the calculation time. Overall, this hair Although the effective improvement of the low-density parity check code has the problem of high decoding capability but high cost, the cost of the overall decoder is effectively reduced.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

1‧‧‧Decoder

10‧‧‧ Receiving unit

11‧‧‧Computation Module

12‧‧‧ memory

13‧‧‧Switch unit

111-1, 111-2, ..., 111-k‧‧‧ arithmetic unit

112-1, 112-2, ..., 112-n‧‧‧ displacement unit

121-1, 121-2, ..., 121-n‧‧‧ memory unit

Ec‧‧‧ encoded data

Ed‧‧‧Decoding data

H‧‧‧cyclic check matrix

S101~S113‧‧‧ is the method step flow

1 is a block diagram of a decoder of a low-density parity check code according to an embodiment of the present invention; FIG. 2 is a schematic diagram of partitioning of a loop check matrix block according to an embodiment of the present invention; and FIG. 3 is a low-density parity check according to an embodiment of the present invention; Schematic diagram of the decoder operation process of the code verification; FIG. 4 is a flow chart of the decoding method of the low density parity check code according to the embodiment of the present invention.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "or" may include all combinations of any one or more of the associated listed items.

Please refer to FIG. 1. FIG. 1 is a decoding of a low density parity check code according to an embodiment of the present invention. Block diagram of the device. As shown in FIG. 1, the present invention is a decoder 1 having a low density parity check code for decoding encoded data Ec having a bit node and a check node to generate decoded data. Ed also ensures the correctness of the decoded data Ec. The encoded data Ec is formed by encoding the original data (not shown) through an encoder. However, there are techniques commonly used in error correction codes for bit nodes and check nodes, which are generally known to those skilled in the art, and therefore will not be described herein. It is to be noted that, in the embodiment of the present invention, the decoder 1 adopts a Quasi Cyclic-Low Density Parity-Check (QC-LDPC) as an implementation manner.

The decoder 1 includes a receiving unit 10, a computing module 11, a memory 12, and a switching unit 13. The computing module includes arithmetic units 111-1, 111-2, ..., 111-k and displacement units 112-1, 111-2, ..., 111-k, and the memory includes memory units 121-1, 121 -2,...,121-n. The computing module 11 is coupled to the receiving unit 10 , and the memory 12 is coupled to the computing module 11 . The memory 12 and the switching unit 13 are coupled to the computing module 11 .

The receiving unit 10 is configured to receive and temporarily store the encoded data Ec, and initialize the bit node of the encoded data Ec to provide the decoder 1 for decoding. In this embodiment, the receiving unit 10 initializes the bit node in the encoded data Ec by a log likelihood ratio (LLR), so that the encoded data Ec conforms to the low density parity check code calculation module 11 The algorithm model is modeled and the calculations are performed in the calculation module 11. The receiving unit 10 can also initialize the bit nodes in the encoded data Ec in other manners, such as normalization, which is not limited by the present invention. In addition, in the embodiment of the present invention, the receiving unit 10 may be a register, and has a high-speed storage component with a limited storage capacity for temporarily storing instructions, data, and addresses. In decoder 1, the scratchpad is the topmost level in the memory hierarchy and is the fastest way to manipulate data in the system. Scratches are usually estimated by the number of bits they can hold, such as an 8-bit scratchpad or a 32-bit scratchpad. In the embodiment of the present invention, the temporary register is usually implemented in the form of a register array, but it can also The invention is practiced using a separate flip-flop, high speed core memory, thin film memory, and other means on several machines, and the invention is not limited thereto.

The calculation module 11 is configured to calculate the encoded data Ec received by the receiving unit 10. More specifically, the computing module 11 decodes the encoded data of the low density parity check code having the bit node and the check node. When the computing module 11 receives the encoded data Ec, the encoded data Ec is divided into n first bit strings, wherein each first bit string is a length of k bits.

The operation unit 111-i is respectively configured to calculate the i-th bit in the n first bit strings cut by the calculation module 11 and generate a second bit string, where k, n≧1, and are integers , where i=1~k is an integer. All of the arithmetic units 111-1, 111-2, ..., 111-k simultaneously calculate n bits received from the n first bit strings and generate a second bit string. That is, each of the arithmetic units 111-1, 111-2, ..., 111-k collects the first to kth bits from each of the first bit strings, and thus the string of the second bit string The length is n. For example, the computing module 11 cuts the encoded material Ec into 15 first bit strings, and each first bit string is 16 bits. The arithmetic unit 111-1 receives the first bit in each of the first bit strings for operation, that is, the arithmetic unit 111-1 receives and operates a string of a length of 15 bits. Similarly, the operation unit 111-2 receives the second bit in each of the first bit strings to perform an operation, that is, the operation unit 111-2 receives and calculates another string of the length of 15 bits, This type of push. In the embodiment of the present invention, the operation units 111-1, 111-2, ..., 111-k may be a Central Process Unit (CPU), a Micro Control Unit (MCU) or the like. The components having the computing function are not limited by the invention.

The displacement units 112-1, 112-2, ..., 112-n are used to shift the bit string. Each of the displacement units is coupled to each of the operation units 111-1, 111-2, . . . , 111-k. Each of the shifting units 112-1, 112-2, ..., 112-n collects the first to nth bits of all the received second bit strings to generate a third bit string, and the third bit The metastring is displaced. Wherein the length of the string of the third bit string is longer than the string of the first bit string The degree is the same as k. In the embodiment of the present invention, the number of bits of the displacement units 112-1, 112-2, ..., 112-n is not limited by the user according to the practical setting of the user.

The memory 12 is used to store information that the computing module 11 needs to store during the calculation process. More specifically, when the decoder calculates the low density parity check code, the calculation is repeated in an iterative manner, so that the result of each calculation is stored through the memory 12. In the embodiment of the present invention, the memory 12 may be implemented by using a volatile or non-volatile memory chip such as a flash memory chip, a read-only memory chip or a random access memory chip, but the embodiment does not This is limited. Further, the decoder 1 is divided into memory blocks in units of a cyclic matrix, that is, the memory 12 includes a plurality of memory units 121-1, 121-2, ..., 121-n. Each memory unit is coupled to the displacement unit for respectively storing the third bit string after the displacement of each displacement unit. The bit storage space of the memory unit 121-1, 121-2, ..., 121-n is greater than or equal to the string length of the encoded data Ec, and the bit storage space has a plurality of string storage columns, wherein each word The number of bits that can be stored in the string storage column is greater than or equal to the number of k arithmetic units. It is worth mentioning that the decoder can achieve the best cost-effectiveness when the number of bits that can be stored in each string storage column is equal to the number of k arithmetic units. On the other hand, the memory 12 can also include unused memory cells (not shown). More specifically, the memory 12 actually includes m memory cells (m≧n≧1), and is only provided by the memory cells 121-1, 121-2, ..., 121-n in the embodiment of the present invention. Stored while computing, while other mn are not used. Alternatively, in other embodiments, n memory cells may be selectively used from m memory cells for use, and m-n are not used in the current operation, and the present invention is not limited thereto.

The switching unit 13 is configured to switch the message passing to the computing mode or the receiving mode. When the computing module 11 receives the encoded data Ec from the receiving unit 10, the switching unit 13 switches to the computing mode, and the computing module 11 begins to perform the iterative calculation of the cyclic low-density parity check code, and is set according to the user. Preset calculations or Syndrome Text to determine whether to end or stop counting Count. When the calculation is stopped, the switching unit 13 switches to the receiving mode, so that the receiving unit 10 provides the next encoded data Ec to the computing module 11 to continue the calculation.

Next, please refer to FIG. 2. FIG. 2 is a schematic diagram of partitioning of a loop check matrix block according to an embodiment of the present invention. The decoder proposed by the embodiment of the present invention adopts a structure of a cyclic check matrix H, wherein the Np*Mp check matrix is in units of blocks p*p, and each block has a unit matrix cyclic shift (Cyclic Shifts). Characteristics, the cyclic displacement of each block is different. The blocks of each column store their calculation results in different memory units 121-1, 121-2, ..., 121-n, respectively. For example, the user can use a 1024*512 loop check matrix H, where each block size is 32*32. Therefore, 1024/32 requires 32 memory cells (ie, the aforementioned memory blocks). However, the more detailed loop check matrix characteristics are those commonly used in the art, and are commonly used in error correction codes, and therefore will not be described herein.

Please refer to FIG. 1 and FIG. 3 simultaneously. FIG. 3 is a schematic diagram of the operation process of the decoder of the low density parity check code according to the embodiment of the present invention. In the decoding process of the low density parity check code decoder 1 of the embodiment of the present invention, the calculation of the iteration is performed in the calculation module 11. The calculation result of the memory block of each loop check matrix is stored in the memory units 121-1, 121-2, ..., 121-n, and the calculation is repeated.

More specifically, in the process of repeating the calculation, the calculation module 11 reads the third bit stored last time from the respective memory units 121-1, 121-2, ..., 121-n in the memory 12. Yuan string. Next, the arithmetic units 111-1, 111-2, ..., 111-k are respectively used to calculate the 1st to kth bits in the read n third bit strings, and generate a new second A bit string in which the length of the new second bit string is n. Then, each of the shifting units 112-1, 112-2, ..., 112-n collects the first to nth bits of all the received second bit strings to generate a new third bit string, and The new third bit string is shifted. Finally, the new third bit string is again stored in the original memory unit 121-1, 121-2, ..., 121-n to provide the next iterative calculation until the computing module 11 reaches the pre-up The design count or the symptom test is stopped at zero, and the decoded data Ed is output.

Please refer to FIG. 4. FIG. 4 is a decoding of a low density parity check code according to an embodiment of the present invention. Method flow chart. The decoding method of the embodiment of the present invention includes the following steps: Step S101, receiving encoded data, and performing initialization; Step S103, dividing the encoded data into a plurality of first bit strings according to the number of memory cells; and step S105, each first The i-th bit of the bit string is calculated in the operation unit 111-i and generates a second bit string; in step S107, after the operation units 111-1, 111-2, ..., 111-k are operated, Each of the j-th bit in each second bit string is transmitted to the displacement unit 111-j to generate a third bit string, and the third bit string is shifted; in step S109, it is checked whether the number of calculations reaches the pre-predetermined The design calculation number or the symptom test is zero; in step S111, the n third bit strings are respectively stored in the correspondingly coupled memory units 121-1, 121-2, ..., 121-n; in step S113, the switch In the receive mode, the next encoded data is received.

Please also refer to Figure 1, Figure 3 and Figure 4. In step S101, the receiving unit 10 receives and temporarily stores the encoded material Ec, and further initializes the bit node of the encoded data Ec to provide the decoder 1 for decoding. In step S103, when the calculation module 11 receives the encoded data Ec, the encoded data Ec is divided into n first bit strings, wherein each first bit string is k bits.

In step S105, the computing units 111-1, 111-2, ..., 111-k are respectively used to calculate the first to kth bits in each of the first bit strings cut by the computing module 11 And produces a second bit string, where k, n ≧ 1, and is an integer. It is worth mentioning that all of the arithmetic units 111-1, 111-2, ..., 111-k simultaneously calculate all n bits from the n first bit strings and generate a second bit string. For example, the computing module 11 cuts the encoded material Ec into 15 first bit strings, and each first bit string is 16 bits. The arithmetic unit 111-1 receives the first bit in each of the first bit strings for operation, that is, the arithmetic unit 111-1 receives and operates a set of 15 bit length second bit strings. Similarly, the operation unit 111-2 receives the second bit in each of the first bit strings for operation, that is, the operation unit 111-2 receives and calculates another set of 15 second bit strings of length analogy. The arithmetic operations of all the above arithmetic units are simultaneously processed.

In step S107, after the arithmetic units 111-1, 111-2, ..., 111-k are operated, Each of the j-th bit in each second bit string is transmitted to the displacement unit 111-j to generate a third bit string, and the third bit string is shifted. It is worth mentioning that the displacement of each displacement unit can be set according to the actual usage of the user.

In step S109, the calculation module 11 checks whether the number of calculations of the iterations reaches the number of calculations preset by the user or the symptom test is zero. If the calculation module 11 determines YES, the decoded data Ed is output and the process proceeds to step S113. If the calculation module 11 determines NO, the process proceeds to step S111.

In step S111, the shifted jth third bit string is separately stored in the corresponding coupled memory unit 121-j to provide the next iterative calculation. It is worth mentioning that the bit storage space of the memory units 121-1, 121-2, ..., 121-n is greater than or equal to the string length of the encoded data Ec, and the bit storage space has multiple sets of string storage. A column in which the number of bits that can be stored in each string storage column is greater than or equal to the number of k arithmetic units.

In step S113, when the calculation module 11 determines that the condition for stopping the calculation is reached and outputs the decoded data Ed, the switching unit 13 switches to the receiving mode, so that the receiving unit 10 provides the next encoded data Ec to the computing module 11 to continue the new one. Decoding calculation.

[The possible effects of the invention]

In summary, the decoder for low-density parity check code proposed by the embodiment of the present invention and the decoding method thereof can avoid the conventional decoder using low-density parity check code in the process of writing and reading. The resulting data collided. On the other hand, in the decoder architecture proposed by the present invention, the parallelism of the operation of the low density parity check code decoder is improved by dividing the memory into a parallel architecture of a memory block in units of a cyclic matrix. It is also possible to replace the traditional decoder with a switching network. When performing calculations, both writing and reading must use a switching network, and simplify the bit node unit that is conventionally used. And can achieve the effect of avoiding data collision and further shorten the calculation time. In general, the present invention effectively improves the low-density parity check code, although it has the capability of high decoding but is costly, and effectively reduces the cost of the overall decoder.

The above description is only the preferred embodiment of the present invention, but the features of the present invention are not limited thereto, and any one skilled in the art can easily change or modify it in the field of the present invention. Covered in the following patent scope of this case.

111-1, 111-2, ..., 111-k‧‧‧ arithmetic unit

112-1, 112-2, ..., 112-n‧‧‧ displacement unit

121-1, 121-2, ..., 121-n‧‧‧ memory unit

Claims (11)

A Low Density Parity Check Code (LPDC) decoder for decoding an encoded data having a plurality of bit nodes and a plurality of check nodes, the decoder comprising: a computing module Dividing the coded data into n first bit strings, the calculation module includes: k operation units, the i-th operation unit calculates the i-th bit in the first bit strings and generates one a second bit string, wherein i = 1 to an integer of k; and n displacement units, one to more coupled to the k operation units, the jth displacement unit to receive the second bit strings The third bit string generates a third bit string, and the third bit string is shifted, wherein j=1 to n an integer; and a memory coupled to the computing module, including: n The memory unit is coupled to the n displacement units for respectively storing the shifted third bit strings; wherein k, n≧1, and is an integer. The decoder of the low density parity check code according to claim 1, further comprising: a receiving unit, receiving the encoded data, and initializing the bit nodes of the encoded data. The decoder of the low density parity check code of claim 2, wherein the computing module determines whether to stop the calculation according to a preset number of calculations or a symptom test. The decoder of the low-density parity check code of claim 1, further comprising: a switching unit coupled to the computing module to switch the message passing into a computing mode or a receiving mode. The decoder of the low density parity check code of claim 1, wherein the low density parity check code is a Quasi Cyclic-Low Density Parity Check (QC-LDPC). The decoder of the low density parity check code of claim 1, wherein one of the memory cells has a bit storage space greater than or equal to a string length of the encoded data, and The bit storage space has a plurality of sets of string storage columns. The decoder of low density parity check code as claimed in claim 6, wherein the number of bits that can be stored in each of the string storage columns is greater than or equal to the number of the k operation units. A decoder for low density parity check code as claimed in claim 1, wherein the arithmetic units simultaneously calculate the first bit strings and generate the second bit string. A decoder for low density parity check code as claimed in claim 1, wherein the first bit string and the third bit string have a string length of k. A decoder for low density parity check code as claimed in claim 1, wherein the second bit string has a string length of n. A decoding method for a low-density parity check code, configured to decode an encoded data having a plurality of bit nodes and a plurality of check nodes, the decoding method comprising: dividing the encoded data into n first bit strings Calculating the first to kth bits of the n first bit strings by k arithmetic units and generating k second bit strings; the k received by the n displacement units respectively The first to nth bits of the second bit string generate n third bit strings, and the third bit strings are shifted; and the shifted third bit strings are respectively stored in n memories Unit; where k, n≧1, and is an integer.