TWI547085B - Power converter - Google Patents

Description

Power converter

The present invention relates to a converter, and more particularly to a power converter capable of achieving high voltage conversion gain.

The output voltage generated by conventional solar power generation systems and fuel cell power generation systems is a low voltage to solve the safety and reliability of residential applications, but with the rise of grid-connected power generation systems, to reach its 200/380V The high DC voltage must first boost the low output voltage generated by the solar power system and the fuel cell power generation system. Therefore, the boost type power converter plays an important role in the power electronics field.

In order to reduce input current ripple and high power applications, conventional boost converters have chosen an interleaved boost converter as shown in Figure 1. The interleaved boost converter is electrically coupled to an external power supply 60 that generates an input voltage Vin1 and includes a first converter 6, and a second converter 7. The first converter 6 is electrically connected to the external power source 60 to receive the input voltage Vin1 and generate a sixth voltage V6 and a seventh voltage V7. The second converter 7 is electrically connected to the first converter 6 to receive the sixth and seventh voltages V6, V7, and generates a DC output voltage Vo1 according to the sixth and seventh voltages V6, V7.

When the interleaved boost converter operates in continuous conduction mode (When the continuous conduction mode is a condition in which the magnitude of the current flowing through the two inductors L1 and L2 is always greater than zero), the voltage conversion gain M is as shown in the following formula (1). The parameter d is the individual duty cycle of the two switches S1 and S2 of the first converter 6, the parameter Vo1 is the DC output voltage, and the parameter Vin1 is the input voltage.

According to formula (1), when the interleaved boost converter is to obtain a high voltage conversion gain, the switches S1 and S2 need to operate at a very large conduction ratio d, resulting in the interleaved boost converter. It is easy to generate a problem of large current ripple. And if the switches S1 and S2 are operated at a very large conduction ratio d in order to obtain a high voltage conversion gain, the output diodes are passed before the two output diodes D1 and D2 are turned off. The magnitudes of the currents of the bodies D1 and D2 are quite different from the magnitudes of the currents flowing through the output diodes D1 and D2 when the output diodes D1 and D2 are turned off, and the reverse recovery loss is equivalent. Big. Even more, in some applications, such as a typical Pulse Width Modulation (PWM) control integrated circuit (IC), it is more difficult to achieve a conduction ratio d greater than 0.9. Therefore, it is quite difficult to obtain a high voltage conversion gain in this case. In addition, the voltage stress of the switches S1 and S2 of the conventional interleaved boost converter is mostly a high voltage output voltage, so the switches S1 and S2 have a high on-resistance value, resulting in the switches S1. S2 has a large conduction loss when turned on.

Accordingly, it is an object of the present invention to provide a power converter that can increase the voltage conversion gain while reducing the turn-on ratio and input current ripple.

Therefore, the power converter of the present invention comprises a reduced current chopper module, a boosting module, and a gain boosting module.

The reduced current chopper module is adapted to be electrically connected to a DC voltage source that supplies a DC input voltage to receive the DC input voltage from the DC voltage source, and accordingly generate a first voltage and a second voltage.

The boosting module includes a first boosting circuit and a second boosting circuit.

The first boosting circuit has a first end and a second end, respectively, electrically connected to the reduced current chopper module to respectively receive the first and second voltages from the reduced current chopper module The third boosting circuit and the fourth boosting circuit respectively output a third voltage and a fourth voltage at the third and fourth ends according to the first and second voltages.

The second boosting circuit is electrically connected to the third and fourth ends of the first boosting circuit to respectively receive the third and fourth voltages, and generate a boosted voltage according to the third and fourth voltages And the second boosting circuit includes a first diode and a first capacitor.

The first diode has an anode electrically connected to the fourth end of the first boosting circuit, and a cathode.

The first capacitor has a first end electrically connected to the cathode of the first diode, and a second end electrically connected to the third end of the first booster circuit, and the first end of the first capacitor The boost voltage is outputted at one end.

The gain boosting module is electrically connected to the second boosting circuit of the boosting module to receive the boosting voltage from the second boosting circuit, and generates a DC output voltage according to the boosting voltage, and the gain is boosted The module includes a first output diode, a second output diode, a third output diode, a first output capacitor, a first secondary inductor, a second secondary inductor, and a second output inductor. a second output capacitor, a third output capacitor, and an output resistor.

The first output diode has an anode electrically connected to the cathode of the first diode of the second boosting circuit and receiving the boosting voltage, and a cathode.

The second output diode has an anode electrically connected to the cathode of the first output diode, and a cathode.

The third output diode has an anode electrically connected to the cathode of the second output diode, and a cathode.

The first output capacitor has a first end electrically connected to the cathode of the third output diode, and a second end.

The first secondary side inductor is connected in series to the second secondary side inductor, and the first secondary side inductor is electrically connected to the second end of the first output capacitor, and the second secondary side inductor is electrically connected to the first The cathode of the two output diodes.

The second output capacitor is electrically connected between the second end of the first output capacitor and the cathode of the first output diode.

The third output capacitor is electrically connected between the cathode of the first output diode and the ground.

The output resistor is electrically connected between the cathode and the ground of the third output diode, and the voltage across the output resistor is used as the DC output voltage.

Preferably, the current-carrying chopper module includes a first primary side inductance, a first excitation inductance, a first leakage inductance, a first switch, a second primary side inductance, and a second electromagnetic inductance. a second leakage inductance and a second switch.

The first primary side inductor has a first end electrically connected to the DC voltage source to receive the DC input voltage, and a second end.

The first magnetizing inductance is connected in parallel to the first primary side inductance.

The first leakage inductance has a first end electrically connected to the second end of the first primary side inductance, and a second end outputting the first voltage.

The first switch is electrically connected between the second end of the first leakage inductance and the ground, and has a control end for receiving a first control signal, so that the first switch is turned on according to the first control signal. Or not.

The second primary side inductor has a first end electrically connected to the DC voltage source to receive the DC input voltage, and a second end.

The second magnetizing inductance is connected in parallel to the second primary side inductance.

The second leakage inductance has a first end electrically connected to the second end of the second primary side inductance, and a second end outputting the second voltage.

The second switch is electrically connected between the second end of the second leakage inductance and the ground, and has a control end for receiving a second control signal, so that the second switch is turned on according to the second control signal. Or not.

The effect of the present invention is that the first boosting circuit of the first boosting module and the second boosting circuit cooperate to make the output resistor The DC output voltage is increased, thereby increasing the voltage conversion gain of the power converter of the present invention, and the first and second switches have the advantage of having low voltage stress without operating at a large turn-on ratio.

1‧‧‧Reducing current chopper module

10‧‧‧DC voltage source

11‧‧‧First primary side inductance

12‧‧‧First switch

13‧‧‧Second primary side inductance

14‧‧‧Second switch

2‧‧‧Boost Module

21‧‧‧First booster circuit

211‧‧‧First boost unit

212‧‧‧Second boost unit

213‧‧‧second boost unit

214‧‧‧ third boost unit

22‧‧‧second booster circuit

221‧‧‧ first diode

222‧‧‧first capacitor

3‧‧‧ Gain boost module

31‧‧‧First output diode

32‧‧‧Second output diode

33‧‧‧ Third output diode

34‧‧‧First output capacitor

35‧‧‧First secondary inductance

36‧‧‧Second secondary inductance

37‧‧‧Second output capacitor

38‧‧‧ third output capacitor

39‧‧‧Output resistance

41‧‧‧second capacitor

42‧‧‧second diode

43‧‧‧ third capacitor

44‧‧‧ Third Dipole

45‧‧‧fourth capacitor

46‧‧‧Fourth dipole

51‧‧‧ Third Dipole

52‧‧‧ third capacitor

53‧‧‧fourth capacitor

54‧‧‧Fourth dipole

55‧‧‧ fifth capacitor

56‧‧‧ fifth diode

60‧‧‧External power supply

6‧‧‧ first converter

7‧‧‧Second converter

D1‧‧‧ output diode

D2‧‧‧ output diode

I1‧‧‧ first circuit

I2‧‧‧second loop

I3‧‧‧ third circuit

Iin‧‧‧ input current

L1‧‧‧Inductance

L2‧‧‧Inductance

Lm1‧‧‧first magnetizing inductance

Lm2‧‧‧second magnetizing inductance

Lk1‧‧‧First Leakage Inductance

Lk2‧‧‧Second leakage inductance

S1‧‧ switch

S2‧‧‧ switch

Vo‧‧‧DC output voltage

Vo1‧‧‧DC output voltage

Vin‧‧‧DC input voltage

Vin1‧‧‧ input voltage

V1‧‧‧ first voltage

V2‧‧‧second voltage

V3‧‧‧ third voltage

V4‧‧‧fourth voltage

V5‧‧‧ boost voltage

V6‧‧‧ sixth voltage

V7‧‧‧ seventh voltage

Vgs1‧‧‧ first control signal

Vgs2‧‧‧ second control signal

Other features and effects of the present invention will be apparent from the following description of the drawings. FIG. 1 is a circuit diagram illustrating a conventional interleaved boost converter; FIG. 2 is a circuit diagram illustrating the present invention. A first embodiment of the inventive power converter; FIG. 3 is a timing diagram illustrating the first embodiment; FIG. 4 is a circuit diagram illustrating the first embodiment operating in mode one; FIG. 5 is a circuit diagram illustrating The first embodiment operates in mode two; FIG. 6 is a circuit diagram illustrating the first embodiment operating in mode three; FIG. 7 is a circuit diagram illustrating the first embodiment operating in mode four; FIG. 8 is a circuit diagram illustrating The first embodiment operates in mode five; FIG. 9 is a circuit diagram illustrating the first embodiment operating in mode six; FIG. 10 is a schematic diagram illustrating a voltage conversion gain versus a turn-on ratio of the first embodiment FIG. 11 is a waveform diagram illustrating the first and second control signals, the DC input voltage, and the DC output voltage of the first embodiment; FIG. 12 is a waveform diagram illustrating the flow through the first embodiment. One and second And receiving the output current of the first to third capacitors; FIG. 13 is a waveform diagram illustrating the voltage across the individual such first and second control signals and first and second switches of the first embodiment; Figure 14 is a circuit diagram showing a first booster circuit of a second embodiment of the power converter of the present invention; Figure 15 is a circuit diagram showing the first and the third embodiment of the power converter of the present invention The second boosting circuit; and FIG. 16 is a circuit diagram illustrating the first and second boosting circuits of a fourth embodiment of the power converter of the present invention.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

<First Embodiment>

Referring to FIG. 2, a first embodiment of the power converter of the present invention includes a reduced current chopper module 1, a boost module 2, and a gain boosting module 3.

The current reducing chopper module 1 is adapted to be electrically connected to a DC voltage source 10 for supplying a DC input voltage Vin to receive the DC input voltage Vin from the DC voltage source 10, and accordingly generate a first voltage V1 and A second voltage V2.

The current reducing chopper module 1 includes a first primary side inductor 11, a first magnetizing inductance Lm1, a first leakage inductance Lk1, a first switch 12, a second primary side inductance 13, and a second The magnetizing inductance Lm2, a second leakage inductance Lk2, and a second switch 14.

The first primary side inductor 11 has a first end electrically connected to the DC voltage source 10 to receive the DC input voltage Vin, and a second end. The first magnetizing inductance Lm1 is connected in parallel to the first primary side inductor 11. The first A leakage inductance Lk1 has a first end electrically connected to the second end of the first primary side inductor 11, and a second end outputting the first voltage V1. The first switch 12 is electrically connected between the second end of the first leakage inductance Lk1 and the ground, and has a control end for receiving a first control signal Vgs1, so that the first switch 12 is according to the first The control signal Vgs1 is turned on or off. The second primary side inductor 13 has a first end electrically connected to the DC voltage source 10 to receive the DC input voltage Vin, and a second end. The second magnetizing inductance Lm2 is connected in parallel to the second primary side inductor 13. The second leakage inductance Lk2 has a first end electrically connected to the second end of the second primary side inductor 13 and a second end outputting the second voltage V2. The second switch 14 is electrically connected between the second end of the second leakage inductance Lk2 and the ground, and has a control end for receiving a second control signal Vgs2, so that the second switch 14 is according to the second The control signal Vgs2 is turned on or off. In the first embodiment, each of the first and second switches 12, 14 is an N-type metal oxide half field effect transistor, but is not limited thereto.

The boosting module 2 includes a first boosting circuit 21 and a second boosting circuit 22. The first boosting circuit 21 has a first end and a first electrically connected to the reduced current chopper module 1 to respectively receive the first and second voltages V1, V2 from the reduced current chopper module 1 a second end, a third end, and a fourth end. The first boosting circuit 21 outputs a third voltage V3 and a fourth voltage V4 at the third and fourth ends respectively according to the first and second voltages V1 and V2. The first boosting circuit 21 includes a first boosting unit 211. The first boosting unit 211 includes a second capacitor 41 and a second diode 42. The second capacitor 41 has an electrical connection to the first boosting power a first end of the first end of the path 21 and a second end electrically connected to the fourth end of the first boosting circuit 21. The second diode 42 has an anode electrically connected to the second and third ends of the first boosting circuit 21, and a cathode electrically connected to the fourth end of the first boosting circuit 21.

The second boosting circuit 22 is electrically connected to the third and fourth ends of the first boosting circuit 21 to respectively receive the third and fourth voltages V3, V4, and according to the third and fourth voltages V3 and V4 generate a boosting voltage V5, and the second boosting circuit 22 includes a first diode 221 and a first capacitor 222. The first diode 221 has an anode electrically connected to the fourth end of the first boosting circuit, and a cathode. The first capacitor 222 has a first end electrically connected to the cathode of the first diode 221, and a second end electrically connected to the third end of the first booster circuit 21, and the first capacitor The first end of 222 outputs the boost voltage V5.

The boosting module 3 is electrically connected to the second boosting circuit 22 of the boosting module 2 to receive the boosted voltage V5 from the second boosting circuit 22, and generates a DC output according to the boosting voltage V5. Voltage Vo. The gain boosting module 3 includes a first output diode 31, a second output diode 32, a third output diode 33, a first output capacitor 34, and a first secondary inductor 35. a second secondary side inductor 36, a second output capacitor 37, a third output capacitor 38, and an output resistor 39.

The first output diode 31 has an anode electrically connected to the cathode of the first diode 221 of the second boosting circuit 22 and receiving the boosting voltage V5, and a cathode. The second output diode 32 has an anode electrically connected to the cathode of the first output diode 31, and a cathode. The first The three-output diode 33 has an anode electrically connected to the cathode of the second output diode 32, and a cathode. The first output capacitor 34 has a first end electrically connected to the cathode of the third output diode 33, and a second end. The first secondary side inductor 35 and the second secondary side inductor 36 are connected in series, and the first secondary side inductor 35 is electrically connected to the second end of the first output capacitor 34. The second secondary side inductor 36 is electrically connected to the cathode of the second output diode 32. The second output capacitor 37 is electrically connected between the second end of the first output capacitor 34 and the cathode of the first output diode 31. The third output capacitor 38 is electrically connected between the cathode of the first output diode 31 and the ground. The output resistor 39 is electrically connected between the cathode of the third output diode 33 and the ground, and the voltage across the output resistor 39 is used as the DC output voltage Vo.

In the first embodiment, the first primary side inductor 11 and the first secondary side inductor 35 are combined into a first coupled inductor, and the first coupled inductor, the first magnetizing inductor Lm1, and the first leakage current The sense Lk1 is combined into a first transformer, and the first primary side inductance 11 and the first secondary side inductance 35 have a turns ratio of one. The second primary side inductor 13 and the second secondary side inductor 36 are combined into a second coupled inductor, and the second coupled inductor, the second magnetizing inductor Lm2 and the second leakage inductor Lk2 are combined into a second transformer. The ratio of the turns ratio of the second primary side inductor 13 and the second secondary side inductor 36 is one.

Referring to FIG. 3, the parameter Iin represents an input current of the DC voltage source 10, and the parameters iLk1 and iLk2 represent currents flowing through the first leakage inductance Lk1 and the second leakage inductance Lk2, respectively, parameters i31, i221, i42, i32. And i33 respectively indicate a current flowing through the first output diode 31, a current flowing through the first diode 221, a current flowing through the second diode 42, and flowing through the second output diode. The current of 32, the current flowing through the third output diode 33.

In order to clearly explain the operation of the first embodiment of the power converter of the present invention, the following six modes will be described in detail, and for convenience of explanation, in FIGS. 4 to 9, the conductive elements are drawn in solid lines, The turned-on components are drawn in dashed lines.

Mode one (t0~t1): Referring to FIG. 3 and FIG. 4, the DC input voltage Vin provides energy such that the input current Iin rises linearly, and the first and second switches 12, 14 are respectively subjected to the first And the second control signals Vgs1, Vgs2 are controlled to be turned on, so that the first and second diodes 221, 42 and the first to third output diodes 31-33 are reverse biased and not turned on. Therefore, in this mode, the currents iLk1, iLk2 flowing through the first and second leakage inductances Lk1, Lk2 respectively charge the first and second leakage inductances Lk1, Lk2, and when the second When the switch 14 is controlled by the second control signal Vgs2 and is not turned on, it enters mode 2.

Mode 2 (t1~t2): Referring to FIG. 3 and FIG. 5, the second switch 14 has been switched to be non-conducting, and the first switch 12 is continuously turned on. At this time, the second diode 42 and the first and third output diodes 31 and 33 are turned into a forward bias by the reverse bias, and the current iLk2 flows through the second leakage inductance Lk2. After being divided into a first current i1 and a second current i2, the first current i1 is The second diode 42, the second capacitor 41 and the first switch 12 flow to the ground, and charge the second capacitor 41. The second current i2 flows to the ground via the first capacitor 222, the first output diode 31 and the third output capacitor 38. The second current i2 discharges the first capacitor 222 and charges the third output capacitor 38, so the current iLk2 flowing through the second leakage inductance Lk2 decreases linearly.

At the same time, the energy of the second magnetizing inductance Lm2 is also transmitted to the second secondary side inductor 36 by coupling, so that a third current i3 flows from the second secondary side inductor 36 through the third output two. The pole body 33 and the first output capacitor 34 charge the first output capacitor 34. When the energy stored in the second leakage inductance Lk2 is completely released, the mode 3 is entered.

Mode 3 (t2~t3): Referring to FIG. 3 and FIG. 6, the second switch 14 continues to be non-conducting, and the first switch 12 is continuously turned on. The energy of the second leakage inductance Lk2 is completely released, so that the first output diode 31 and the second diode 42 are converted into a reverse bias by the forward bias and are not turned on. At this time, the energy of the second magnetizing inductance Lm2 is continuously coupled to the second secondary side inductor 36, and the third current i3 continues to charge the first output capacitor 34. When the second switch 14 is turned on by the second control signal Vgs2, it enters mode four.

Mode 4 (t3~t4): Referring to FIG. 3 and FIG. 7, the second switch 14 is switched to be turned on, and the first switch 12 is continuously turned on. At this time, the operation mode is the same as the mode, so No longer. When the first switch 12 is controlled by the first control signal Vgs1 and is not turned on, the mode 5 is entered.

Mode 5 (t4~t5): Referring to FIG. 3 and FIG. 8, the first switch 12 has been switched to be non-conducting, and the second switch 14 is continuously turned on. At this time, the first diode 221 and the second output diode 32 are turned into a forward bias by the reverse bias, and the current iLk1 flowing through the first leakage inductance Lk1 passes through the second. The capacitor 41, the first diode 221, the first capacitor 222 and the second switch 14 flow to the ground, and charge the first capacitor 222, and the second capacitor 41 passes through the first diode 221 Energy is released to the first capacitor 222.

In addition, the energy stored in the first magnetizing inductance Lm1 is transmitted to the first secondary side inductor 35 by coupling, and the second output capacitor 37 is charged. When the energy of the first leakage inductance Lk1 is completely released, and the first diode 221 is converted from the forward bias to the reverse bias and is not turned on, the mode 6 is entered.

Mode 6 (t5~t6): Referring to FIG. 3 and FIG. 9, the first switch 12 continues to be non-conducting, and the second switch 14 is continuously turned on. The first diode 221 is not turned on, and the energy of the first magnetizing inductor Lm1 is continuously coupled to the first secondary inductor 35, and the second output capacitor 37 is performed via the second output diode 32. Charging. When the first switch 12 is turned on by the first control signal Vgs1, it returns to the mode one to restart a new cycle.

It is worth noting that this input is used in high power applications. The current Iin tends to have a large amplitude, so if the first primary side inductance 11 and the second primary side inductance 13 respectively receive half of the average current Iavg of the input current Iin (ie, Iavg/2), And the first and second switches 12, 14 perform an interleaving operation (ie, in the second and third modes, the first switch 12 is turned on, and the second switch 14 is not turned on, in the mode five or six, the mode The first switch 12 is not turned on, and the second switch 14 is turned on, which can offset the current ripple generated by the input current Iin between the first primary side inductor 11 and the second primary side inductor 13 And further reducing the magnitude of the current ripple generated by the input current Iin.

In the following, when the first embodiment of the power converter of the present invention is operated in the above mode, the DC output voltage Vo is analyzed and derived, and in order to simplify the analysis, the first and second switches 12, 14 are ignored. The first and second diodes 221, 42 and the first to third output diodes 31-33 have a turn-on voltage drop and a very short transient characteristic, and also ignore the first and the first The two leakage inductances Lk1, Lk2, and the capacitance values of the first to third output capacitors 34, 37, 38 are defined to be large enough to make the voltage across the first to third output capacitors 34, 37, 38 A constant. Therefore, the following formulas (2), (3), (4), and (5) can be derived:

The parameters V ₄₁ , V ₂₂₂ , and V ₃₈ are the cross voltages of the second capacitor 41 , the first capacitor 222 and the third output capacitor 38 , respectively, and the parameters V ₃₄ and V ₃₇ are the first and second respectively. The voltage across the output capacitors 34, 37, the parameter Vin is the DC input voltage, the parameter D is a duty ratio of the first and second switches 12, 14, and the value of the conduction ratio D is greater than 0.5. The parameter n is the turns ratio of the first and second coupled inductors, and the first and second coupled inductors have the same turns ratio, and the parameter X1 is a total capacitance, and the total capacitance X1 is equal to the same The sum of the first and second capacitors 222, 41, and the third output capacitor 38. In the first embodiment, the total capacitance number X1 is as shown in the following formula (4.1): X1 = n ₄₁ + n ₂₂₂ + n ₃₈ formula (4.1)

The parameters n ₄₁ , n ₂₂₂ , and n ₃₈ are the number of the second capacitor 41 , the first capacitor 222 , and the third output capacitor 38 , respectively. In the first embodiment, the number of the second capacitor 41, the first capacitor 222, and the third output capacitor 38 are each 1, so X1 is equal to three (ie, X1=1+1+1=3) .

In the first embodiment, the DC output voltage Vo of the power converter of the present invention is the third output capacitor 38 and the voltages V ₃₈ , V _{34 of the} first and second output capacitors ₃₄ , ₃₇ , V _{37 is} added and can be obtained by the following formula (6):

The voltage conversion gain (CG) of the power converter of the present invention can be obtained by the following formula (7):

According to the above formula (7), the magnitude of the voltage conversion gain CG is a turns ratio n related to the first and second coupled inductors, and the conduction ratio D of the first and second switches 12, 14 . Therefore, the voltage conversion gain CG of the power converter of the present invention can be improved by increasing the turns ratio n or the turn-on ratio D, so that the power converter of the present invention does not need to be a conventional power converter only by formulating The conduction ratio d in (1) is adjusted to the maximum value to increase its voltage conversion gain M. Furthermore, increasing the voltage conversion gain CG of the power converter of the present invention by adjusting the turns ratio n or the value of the turn-on ratio D makes the power converter of the present invention more design freedom.

For example, referring to FIG. 10, it is a schematic diagram of the variation of the voltage conversion gain CG of the power converter of the present invention on the conduction ratio D. According to the formula (7), when the value of the conduction ratio D is 0.6 and the value of the turns ratio n is 1, the value of the voltage conversion gain CG is 12.5. When the value of the conduction ratio D is 0.6 and the value of the turns ratio n is 3, the value of the voltage conversion gain CG is 22.5. When the value of the conduction ratio D is 0.6 and the value of the turns ratio n is 5, the value of the voltage conversion gain CG is 32.5.

The above theoretical analysis was verified by the simulation experiment of the first embodiment of Figs. 11 to 13 below. Wherein, the DC input voltage Vin has a size of 36 volts, the DC output voltage Vo has a magnitude of 400 volts, and the maximum output power is 400 watts, and the first and second coupled inductors have a turns ratio n of 1 .

According to the above parameter values and formula (7), it can be inferred that the conduction ratio D is 0.55, and the first and second control of the first and second switches 12, 14 can be seen by corresponding to the simulation experiment diagram of FIG. The conduction ratio D of the control signals Vgs1 and Vgs2 is also approximately 0.55. Therefore, it can be confirmed that the conduction ratio D calculated by the equation (7) derived from the above theoretical analysis is surely matched with the simulation experiment diagram.

By the formula (2) to Equation (5) can calculate the voltage V across the second capacitor 41 is the size of ₄₁ 80 volts, the voltage across the first capacitor 222 size is 160 V ₂₂₂ V, the third output voltage V 38 across the capacitor ₃₈ is the size of 240 volts, while the size of such cross voltage V _{34 is} such V and the first and second output capacitor 34, 37 is ₃₇ 80 volts, and the plurality of first and The conduction voltage drops of the second switches 12, 14, the first and second diodes 221, 42 and the first to third output diodes 31-33 are taken into consideration and compared with FIG. The magnitudes of the first capacitors 222 and the first to third output capacitors ₃₄ , ₃₇ , ₃₈ of the simulated experimental diagrams of FIG. 12 are indeed the same as the magnitudes of the voltages V ₂₂₂ , V ₃₄ , V ₃₇ , V ₃₈ . The magnitudes of the cross-over voltages V ₂₂₂ , V ₃₄ , V ₃₇ , and V ₃₈ calculated by the formulas (2) to (5) are the same.

Referring to FIG. 13, waveform diagrams of the first and second control signals Vgs1, Vgs2 of the first embodiment and the voltages Vds1, Vds2 of the first and second switches 12, 14 are shown. It can be observed that when the first and second switches 12, 14 are non-conducting, the magnitudes of the voltages Vds1, Vds2 of the first and second switches 12, 14 are about 80 volts, only the DC output. The voltage Vo (Vo is equal to 400 volts) is one-fifth times, thus confirming that the first and second switches 12, 14 of the power converter of the present invention have a low voltage The advantage of force.

<Second embodiment>

Referring to FIG. 14, a difference between the second embodiment of the power converter of the present invention and the first embodiment is that the first booster circuit 21 further includes N second boosting units 212, and the second boosting units Each of 212 has a first end, a second end, a third end, and a fourth end, N ≧ 1, N being a positive integer.

In the second embodiment, the first and second ends of the first second boosting unit 212 are electrically connected to the cathode and the anode of the second diode 42 of the first boosting unit 211, respectively. . The first and second ends of the i-th second boosting unit 212 are electrically connected to the fourth and third ends of the i-1th second boosting unit 212, respectively, 2≦i≦N-1, i is a positive integer. The first and second ends of the Nth second boosting unit 212 are electrically connected to the fourth and third ends of the N-1th second boosting unit 212, respectively, and the Nth second rising The third and fourth ends of the voltage unit 212 are electrically connected to the third and fourth ends of the first booster circuit 21, respectively.

Each of the second boosting units 212 includes a third capacitor 43 , a third diode 44 , a fourth capacitor 45 , and a fourth diode 46 .

In the jth second boosting unit 212, 1≦j≦N,j is a positive integer, and the third capacitor 43 is electrically connected to the second end and the third end of the jth second boosting unit 212. Between the ends. The third diode 44 has an anode electrically connected to the first end of the jth second boosting unit 212, and a cathode electrically connected to the third end of the jth second boosting unit 212. The fourth capacitor 45 is electrically connected to the anode of the third diode 44 and the jth second liter Between the fourth ends of the pressing unit 212. The fourth diode 46 has an anode electrically connected to the third end of the jth second boosting unit 212, and a cathode electrically connected to the fourth end of the jth second boosting unit 212.

The operation procedure and the operation principle of the second embodiment are respectively similar to the first embodiment, and details are not described herein again. Therefore, it can be seen from the above formula (4) that the voltage across the third output capacitor 38 V _{38 is} as shown in the following formula (8):

X2=n ₄₁ +N(n ₄₃ +n ₄₅ )+n ₂₂₂ +n ₃₈ Formula (8.1)

Wherein, the parameter X2 is a total number of capacitors, and the formula (8.1) indicates that in the second embodiment, the total capacitance number X2 is equal to the first and second capacitors 222, 41, and the N second boosting units. The sum of the number of the third and fourth capacitors 43, 45, and the third output capacitor 38 (see FIG. 2) in 212. The parameters n ₄₁ , n ₂₂₂ , and n ₃₈ are the number of the second capacitor 41 , the first capacitor 222 (see FIG. 2 ) and the third output capacitor 38 respectively, and the parameters n ₄₃ and n ₄₅ are respectively the N numbers. The number of the third and fourth capacitors 43, 45 in the second boosting unit 212. For example, when N=2, X2=1+2(1+1)+1+1=7.

Therefore, according to the formulas (6), (8), (8.1), and when N = 2, it can be inferred that the DC output voltage Vo of the second embodiment is as shown in the following formula (9).

<Third embodiment>

Referring to FIG. 15, a difference between the third embodiment of the power converter of the present invention and the first embodiment is that the first booster circuit 21 further includes a second boosting unit 213, and the second boosting unit 213 includes A third diode 51 and a third capacitor 52.

The third diode 51 has an anode electrically connected to the first end of the first booster circuit 21 (see FIG. 2) and the first end of the second capacitor 41, and an electrical connection to the second The cathode of the anode of the pole body 42. The third capacitor 52 has a first end electrically connected to the second end of the first boosting circuit 21 and a second end electrically connected to the anode of the second diode 42.

The operational procedures and operational principles of the third embodiment are similar to the first embodiment, respectively, and therefore will not be repeated. Therefore, from the above equation (4) can be seen as the following equation ₃₈ (10) of the third output voltage V across capacitor 38 is:

X3=n ₅₂ +n ₄₁ +n ₂₂₂ +n ₃₈ formula (10.1)

Wherein, the parameter X3 is a total capacitance quantity, and the formula (10.1) indicates that in the third embodiment, the total capacitance quantity X3 is equal to the third capacitance 52, the first and second capacitances 222, 41, and the The sum of the number of third output capacitors 38 (see Figure 2). The parameters n ₅₂ , n ₄₁ , n ₂₂₂ , and n ₃₈ are the number of the third capacitor 52 , the second capacitor 41 , the first capacitor 222 , and the third output capacitor 38 (see FIG. 2 ), respectively. Since the number of the third capacitor 52, the second capacitor 41, the first capacitor 222, and the third output capacitor 38 of the third embodiment are each 1, X3 is equal to four (ie, X3=1+1) +1+1=4).

Therefore, according to formulas (6), (10), (10.1), the first The DC output voltage Vo of the third embodiment is as shown in the following formula (11).

<Fourth embodiment>

Referring to FIG. 16, a difference between the fourth embodiment of the power converter of the present invention and the third embodiment is that the first boosting circuit 21 further includes N third boosting units 214, and the third boosting units Each of the 214 has a first end, a second end, a third end, and a fourth end, N ≧ 1, N being a positive integer.

In the fourth embodiment, the first and second ends of the first third boosting unit 214 are electrically connected to the first and second ends of the first boosting circuit 21 (see FIG. 2), respectively. . The first and second ends of the i-th third boosting unit 214 are electrically connected to the fourth and third ends of the i-1th third boosting unit 214, respectively, 2≦i≦N-1, i is a positive integer. The first and second ends of the Nth third boosting unit 214 are electrically connected to the fourth and third ends of the N-1th third boosting unit 214, respectively, and the Nth third rising The third and fourth ends of the pressing unit 214 are electrically connected to the first end of the third capacitor 52 and the anode of the third diode 51, respectively.

Each of the third boosting units 214 includes a fourth capacitor 53 , a fourth diode 54 , a fifth capacitor 55 , and a fifth diode 56 . In the jth third boosting unit 214, 1≦j≦N,j is a positive integer, and the fourth capacitor 53 is electrically connected to the second end and the third end of the jth third boosting unit 214. Between the ends. The fourth diode 54 has an electrical connection to the jth An anode of the first end of the third boosting unit 214 and a cathode electrically connected to the third end of the jth third boosting unit 214. The fifth capacitor 55 is electrically connected between the anode of the fourth diode 54 and the fourth end of the j th third boost unit 214. The fifth diode 56 has an anode electrically connected to the third end of the jth third boosting unit 214, and a cathode electrically connected to the fourth end of the jth third boosting unit 214.

The operational procedures and operational principles of the fourth embodiment are similar to the first embodiment, respectively, and therefore will not be repeated. Therefore, it can be seen from the above formula (4) that the voltage across the third output capacitor 38 V _{38 is} as shown in the following formula (12):

X4=N(n ₅₃ +n ₅₅ )+n ₅₂ +n ₄₁ +n ₂₂₂ +n ₃₈ Formula (12.1)

Wherein, the parameter X4 is a total number of capacitors, and the formula (12.1) indicates that in the fourth embodiment, the total capacitance number X4 is equal to the fourth capacitors 53 in the N third boosting units 214 and the like The sum of the fifth capacitor 55, the third capacitor 52, the first and second capacitors 222, 41, and the third output capacitor 38 (see FIG. 2). The parameters n ₅₃ and n ₅₅ are the number of the fourth capacitors 53 and the fifth capacitors 55 in the N third boosting units 214, respectively, and the parameters n ₅₂ , n ₄₁ , n ₂₂₂ , and n ₃₈ are respectively The number of the third capacitor 52, the second capacitor 41 (see FIG. 2), the first capacitor 222, and the third output capacitor 38 (see FIG. 2). For example, when N=2, X4=2(1+1)+1+1+1+1=8

Therefore, according to the formulas (6), (12), (12.1), and when N = 2, it can be inferred that the DC output voltage Vo of the fourth embodiment is as shown in the following formula (13).

In summary, the above embodiment has the following advantages:

1. Reducing the current chopping of the input current Iin: the first primary side inductance 11 and the second primary side inductance 13 respectively receive half of the average current Iavg of the input current Iin (ie, Iavg/2) And the first and second switches 12, 14 are interleaved, so that the current generated by the input current Iin at the first primary side inductance 11 and the second primary side inductance 13 can be mutually Offset, thereby reducing the magnitude of the current ripple generated by the input current Iin.

2. High voltage conversion gain: The present invention utilizes the cooperation of the first boosting circuit 21 and the second boosting circuit 22, and is between the first boosting unit 211 and the second boosting circuit 22 Connecting the N second boosting units 212 (FIG. 14) in series, or connecting the N third boosting units 214 to the second boosting unit 213 and the reduced current by connecting in series as shown in FIG. Between the wave module 1 so that the DC output voltage Vo can be changed as in the formulas (11), (13), thereby achieving a high voltage conversion gain, and there is no need to borrow a boost type power converter as is conventional. A high voltage conversion gain can be achieved by operating at a very large conduction ratio d.

3. High efficiency: as shown in FIG. 13, the voltage stress of the first and second switches 12, 14 of the present invention is much smaller than the DC output voltage Vo, so the first and second switches 12, 14 respectively Have a lower on-resistance value such that the first and second switches 12, 14 have a lower conduction when conducting loss. It can be seen from FIG. 3 that the currents i31, i32, i33, i221, i42 flowing through the first to third output diodes 31-33 and the first and second diodes 221, 42 are The first to third output diodes 31 to 33 and the first and second diodes 221 and 42 are reversely biased and are not significantly turned on before being turned on, thereby improving the conventional voltage converter. The diode reverse recovery loss and the power converter of the present invention have the advantage of high efficiency, so that the object of the present invention can be achieved.

However, the above is only the embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and the patent specification of the present invention are still It is within the scope of the patent of the present invention.

1‧‧‧Reducing current chopper module

10‧‧‧DC voltage source

11‧‧‧First primary side inductance

12‧‧‧First switch

13‧‧‧Second primary side inductance

14‧‧‧Second switch

2‧‧‧Boost Module

21‧‧‧First booster circuit

211‧‧‧First boost unit

22‧‧‧second booster circuit

221‧‧‧ first diode

222‧‧‧first capacitor

3‧‧‧ Gain boost module

31‧‧‧First output diode

32‧‧‧Second output diode

33‧‧‧ Third output diode

34‧‧‧First output capacitor

35‧‧‧First secondary inductance

36‧‧‧Second secondary inductance

37‧‧‧Second output capacitor

38‧‧‧ third output capacitor

39‧‧‧Output resistance

41‧‧‧second capacitor

42‧‧‧second diode

Lm1‧‧‧first magnetizing inductance

Lm2‧‧‧second magnetizing inductance

Lk1‧‧‧First Leakage Inductance

Lk2‧‧‧Second leakage inductance

Vo‧‧‧DC output voltage

Vin‧‧‧DC input voltage

Iin‧‧‧ input current

V1‧‧‧ first voltage

V2‧‧‧second voltage

V3‧‧‧ third voltage

V4‧‧‧fourth voltage

V5‧‧‧ boost voltage

Vgs1‧‧‧ first control signal

Vgs2‧‧‧ second control signal

Claims (9)

A power converter includes: a reduced current chopper module adapted to electrically connect a DC voltage source that supplies a DC input voltage to receive the DC input voltage from the DC voltage source, and thereby generate a first a voltage and a second voltage; a boosting module comprising a first boosting circuit having electrically connected to the reduced current chopper module to respectively receive the first and the first from the reduced current chopper module a first end of the two voltages, a second end, a third end, and a fourth end, wherein the first boosting circuit is respectively configured at the third and fourth ends according to the first and second voltages Outputting a third voltage and a fourth voltage, wherein the first boosting circuit includes a first boosting unit, and the first boosting unit includes a second capacitor having an electrical connection to the first boosting circuit a first end of the first end, a second end electrically connected to the fourth end of the first boosting circuit, and a second diode having an electrical connection to the first boosting circuit An anode of the second and third ends, and an electrical connection to the first boosting circuit a four-terminal cathode, and a second boosting circuit electrically connected to the third and fourth ends of the first boosting circuit to respectively receive the third and fourth voltages, and according to the third and fourth The voltage generates a boosted voltage, and the second boosting circuit includes a first diode having an electrical connection An anode of the fourth end of the circuit, a cathode, and a first capacitor having a first end electrically connected to the cathode of the first diode, and an electrical connection to the first booster circuit a second end of the third end, and the first end of the first capacitor outputs the boosting voltage; and a gain boosting module electrically connected to the second boosting circuit of the boosting module to receive the second rising Pressing the boosting voltage of the circuit, and generating a DC output voltage according to the boosting voltage, and the gain boosting module includes a first output diode having a first two electrically connected to the second boosting circuit a cathode of the pole body and receiving the boosting voltage, and a cathode, a second output diode having an anode electrically connected to the cathode of the first output diode, and a cathode, a third An output diode having an anode electrically connected to the cathode of the second output diode, and a cathode, a first output capacitor having a first end electrically connected to the cathode of the third output diode And a second end, a first secondary side inductance connected in series with a first a second side inductor electrically connected to the second end of the first output capacitor, the second secondary side inductor electrically connecting the cathode of the second output diode, and a second output capacitor Electrically connected between the second end of the first output capacitor and the cathode of the first output diode a third output capacitor electrically connected between the cathode and the ground of the first output diode, and an output resistor electrically connected between the cathode and the ground of the third output diode, the output resistor The cross voltage acts as the DC output voltage. The power converter of claim 1, wherein the reduced current chopping module comprises: a first primary side inductor having a first end electrically connected to the DC voltage source to receive the DC input voltage, and a second end; a first magnetizing inductance connected in parallel to the first primary side inductance; a first leakage inductance having a first end electrically connected to the second end of the first primary side inductance, and an output a second end of the first voltage; a first switch electrically connected between the second end of the first leakage inductance and the ground, and having a control end for receiving a first control signal, such that the first a switch is turned on or off according to the first control signal; a second primary side inductor having a first end electrically connected to the DC voltage source to receive the DC input voltage, and a second end; a second a magnetizing inductor connected in parallel to the second primary side inductor; a second leakage inductor having a first end electrically connected to the second end of the second primary side inductor, and a second end outputting the second voltage And a second switch electrically connected to the second leakage inductance The second end is connected to the ground and has a control end for receiving a second control signal, so that the second switch is turned on or off according to the second control signal. The power converter of claim 1, wherein the first booster circuit The method further includes N second boosting units, and each of the second boosting units has a first end, a second end, a third end, and a fourth end, where N≧1, N are a positive integer; wherein the first and second ends of the first second boosting unit are electrically connected to the cathode of the second diode of the first boosting unit and the anode; wherein, the ith The first and second ends of the second boosting unit are electrically connected to the fourth and third ends of the i-1th second boosting unit, respectively, and 2≦i≦N-1,i is a positive integer; And the first and second ends of the Nth second boosting unit are electrically connected to the fourth and third ends of the N-1th second boosting unit, respectively, and the Nth and second ends The third and fourth ends of the boosting unit are electrically connected to the third and fourth ends of the first boosting circuit, respectively. The power converter of claim 3, wherein the jth second boosting unit, 1≦j≦N,j is a positive integer, and each jth second boosting unit comprises: a third capacitor, Electrically connected between the second end of the jth second boosting unit and the third end; a third diode having an electrical connection to the first end of the jth second boosting unit An anode, and a cathode electrically connected to the third end of the jth second boosting unit; a fourth capacitor electrically connected to the anode of the third diode and the jth second boosting unit Between the fourth ends; and a fourth diode having an electrical connection to the jth second boosting list An anode of the third end of the element, and a cathode electrically connected to the fourth end of the jth second boosting unit. The power converter of claim 1, wherein the first boosting circuit further comprises a second boosting unit, and the second boosting unit comprises: a third diode having an electrical connection The first end of a booster circuit and the anode of the first end of the second capacitor, and a cathode electrically connected to the anode of the second diode; and a third capacitor having an electrical connection a first end of the second end of the boosting circuit and a second end electrically connected to the anode of the second diode. The power converter of claim 5, wherein the first boosting circuit further comprises N third boosting units, and each of the third boosting units has a first end, a first The second end, the third end, and the fourth end, N≧1, N are positive integers; wherein the first and second ends of the first third boosting unit are electrically connected to the first boosting circuit The first and second ends; wherein the first and second ends of the i th third boosting unit are electrically connected to the fourth and third of the i-1th third boosting unit, respectively a terminal, 2≦i≦N-1, i is a positive integer; and wherein the first and second ends of the Nth third boosting unit are electrically connected to the N-1th third boosting unit respectively Waiting for the fourth and third ends, and the third and fourth ends of the Nth third boosting unit are electrically connected to the first end of the third capacitor and the anode of the third diode, respectively. The power converter of claim 6, wherein the jth third boost a unit, 1≦j≦N, j is a positive integer, each jth third boosting unit includes: a fourth capacitor electrically connected to the second end of the jth third boosting unit and the first Between the three ends; a fourth diode having an anode electrically connected to the first end of the jth third boosting unit, and a third electrically connected to the jth third boosting unit a cathode of the terminal; a fifth capacitor electrically connected between the anode of the fourth diode and the fourth end of the jth third boosting unit; and a fifth diode having an electrical connection An anode of the third end of the jth third boosting unit, and a cathode electrically connected to the fourth end of the jth third boosting unit. The power converter of claim 2, wherein the first primary side inductance and the first secondary side inductance are combined into a first coupled inductor, the second primary side inductor and the second secondary side inductor A second coupled inductor is synthesized. The power converter of claim 2, wherein each of the first switch and the second switch is an N-type MOS field effect transistor.