TWI545738B - Unit pixel, photo-detection device and method of measuring a distance using the same - Google Patents

Description

Unit pixel, light detecting device, and method for measuring distance using the same [related application]

The present application claims priority to U.S. Provisional Application No. 61/372,709, filed on Aug. The manner is fully incorporated herein.

An exemplary embodiment relates to a light detecting device. More specifically, the exemplary embodiment relates to a unit pixel having a ring structure, a photodetecting device including a unit pixel having a ring structure, and a method of measuring a distance using a unit pixel having a ring structure.

An image sensor is a light detecting device that converts an optical signal containing information about an image and/or distance (ie, depth) of an object into an electrical signal. Various types of image sensors (such as charge-coupled device (CCD) image sensors, CMOS image sensors (CIS), etc.) have been developed to provide high quality objects. Image information. Recently, three-dimensional (3D) image sensors providing depth information and two-dimensional image information are being researched and developed.

The three-dimensional image sensor can use infrared light or near-infrared light as a light source to obtain depth information. The 3D image sensor may have a lower signal-to-noise ratio (SNR) and sensitivity than conventional 2D image sensors, which results in incorrect depth information.

One or more embodiments provide unit pixels of a light detecting device having high sensitivity and improved signal to noise ratio.

One or more embodiments provide a light detecting device including the unit pixel.

One or more embodiments provide a method of measuring the distance from an object using the light detecting device.

One or more embodiments may provide a unit pixel having a ring-shaped single-joint structure that efficiently collects and discharges photocharges to accurately measure the distance from the object.

One or more embodiments may provide a pixel array including a unit pixel and a photodetecting device that integrally form a drain region corresponding to an outermost portion of a unit pixel without an antihalation structure. This improves the overall design tolerance.

One or more embodiments may provide a light detecting device and a method of measuring a distance, which can obtain depth information using a variable binary signal by a distance of a line-of-sight object and have a high signal-to-noise ratio.

One or more embodiments may provide a unit pixel included in a photodetecting device, the unit pixel comprising a floating diffusion region in a semiconductor substrate, an annular collecting gate over the semiconductor substrate, An annular discharge gate over the semiconductor substrate, and a drain region in the semiconductor substrate, wherein the collector gate and the drain gate are respectively disposed in the floating diffusion region and the drain region between.

The collection gate can surround the floating diffusion region, the discharge gate can surround the collection gate, and the drain region can surround the discharge gate.

The floating diffusion region can be centered and the drain region is located at the outermost side relative to the floating diffusion region as compared to the collector gate and the drain gate.

The collection gate and the discharge gate may have a circular or polygonal annular shape.

The collecting gate signal and the discharging gate signal may be respectively applied to the collecting gate and the discharging gate, wherein when the collecting gate signal is started, the photocharge generated in the semiconductor substrate is collected in the floating diffusion region, and wherein the discharging is started At the gate signal, the photocharge generated in the semiconductor substrate is discharged into the drain region.

The annular photocharge storage region is in the semiconductor substrate and between the floating diffusion region and the drain region, the photocharge storage region being doped with an impurity of a conductivity type opposite to that of the semiconductor substrate.

The collection gate and the inner portion of the photocharge storage region may at least partially overlap, and wherein the discharge gate and the outer portion of the photocharge storage region may at least partially overlap.

The collection gate is located between the photocharge storage region and the floating diffusion region, and wherein the discharge gate is located between the photo charge storage region and the drain region.

The unit pixel may comprise an annular pinned layer in the semiconductor substrate for covering the photocharge storage region, the pinned layer being doped with an impurity of a conductivity type opposite to that of the photocharge storage region.

The unit pixel may include an annular light gate between the semiconductor substrate and between the collection gate and the discharge gate, and to cover the photocharge storage region.

The semiconductor substrate may include a plurality of photocharge generating regions doped with impurities of the same conductivity type and different concentrations.

One or more embodiments may provide a light detecting device comprising: a sensing unit configured to convert received light into an electrical signal, the sensing unit comprising at least one unit pixel; A control unit configured to control the sensing unit.

The sensing unit may include a pixel array in which a plurality of unit pixels are arranged in a rectangular or triangular grid.

The plurality of unit pixel drain regions may be integrally formed and spatially coupled to each other in the semiconductor substrate.

The floating diffusion regions of at least two of the plurality of unit pixels may be electrically coupled to each other and to a pixel group.

The unit pixel may be regularly omitted at at least one grid point of the grid, and the sensing unit may include a readout circuit at the grid point where the unit pixel is omitted to provide the plurality of unit pixels The output.

The plurality of unit pixels may include a color pixel and a depth pixel, and the light detecting device may be a three-dimensional image sensor.

One or more embodiments may provide a method of measuring a distance, the method comprising: emitting light to an object; using a plurality of binary signals that are increased according to a phase difference with respect to the emitted light, corresponding to the emitted The received light of the light is converted into an electrical signal; and a distance from the object is calculated based on the electrical signal, wherein the received pixel is converted into an electrical signal using a unit pixel, the unit pixel being included in a floating diffusion region in the semiconductor substrate, an annular collection gate over the semiconductor substrate, an annular discharge gate over the semiconductor substrate, and a drain region in the semiconductor substrate, wherein the collection gate and the discharge gate are respectively disposed Between the floating diffusion zone and the bungee zone.

The duty ratio of the plurality of binary signals may be increased according to a phase difference with respect to the emitted light.

Converting the received light into an electrical signal can include: collecting photocharges generated by the received light in a floating diffusion region when the plurality of binary signals are activated; and deactivateing the plurality of The binary carry signal discharges the photocharge generated by the received light into the drain region.

The method can include: adjusting a phase of the plurality of binary signals and a duty ratio to focus on a phase corresponding to the calculated distance; and using a plurality of binary bits having an adjusted phase and a duty ratio Signal to correct the distance from the object.

One or more embodiments may provide a method of measuring a distance, the method comprising: emitting light to an object; using a plurality of binary signals that are increased according to a phase difference with respect to the emitted light, corresponding to the emitted Converting the received light of the light into an electrical signal; and calculating a distance from the object based on the electrical signal, wherein a single connector pixel having a ring structure is used to convert the received light into an electrical signal, wherein The floating diffusion region of the pixel is located at the center of the annular structure, and the drain region of the pixel is disposed at an outer portion of the annular structure.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the features may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. In the figures, the size and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to as "on", "connected to" or "coupled to" another element or layer, Directly coupled or directly coupled to another element or layer, or an intervening element or layer may be present. In contrast, when an element is referred to as “directly on,” “directly connected,” or “directly connected” or “directly connected” to another element or layer, there are no intervening elements or layers. Like numbers refer to like elements throughout the description. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, but such elements, components, regions, layers and/or sections It should not be limited by these terms. The terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed hereinafter may be referred to as a second element, component, region, layer or section, without departing from the teachings of the invention.

For ease of description, spatially related terms such as "lower", "lower", "lower", "above", "upper", and the like may be used herein to describe one element or feature described in the figures. The relationship of another component or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. For example, elements that are "under" or "beneath" or "an" or "an" Thus, the exemplary term "lower" can encompass the orientation above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially related descriptors used herein interpreted accordingly. In addition, elements "between" or "circum" other elements may be "between" or "an" or "an" More specifically, for example, the elements may extend along a different plane than one or more of the other elements extending along the other element, but the elements may be between the other elements and / or surround the other components.

The terminology used herein is for the purpose of the description of the particular exemplary embodiments As used herein, the singular forms "" It is further understood that the terms "comprises" or "an" The presence or addition of components and/or their groups.

Exemplary embodiments are described herein with reference to the cross-sectional illustrations of the illustrative exemplary embodiments (and intermediate structures). Thus, variations from the shapes of the figures may be expected due to, for example, manufacturing techniques and/or tolerances. Therefore, the exemplary embodiments should not be construed as limited to the specific shapes of the regions described herein, but should include the shape variations resulting from, for example, manufacturing. For example, an implanted region illustrated as a rectangle will typically have a rounded or curved feature and/or a gradient of implant concentration at its edges rather than a binary change from the implanted region to the non-implanted region. . Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface from which the implantation takes place. The area illustrated in the figures is therefore illustrative in nature and is not intended to limit the scope of the invention.

All terms (including technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It is to be further understood that a term (such as a term defined in a commonly used dictionary) should be interpreted as having a meaning consistent with its meaning in the context of the related art and will not be idealized or over-formed unless explicitly defined herein. The meaning of the meaning is interpreted.

1 illustrates a layout of an exemplary embodiment of a unit pixel of a light detecting device.

Referring to FIG. 1, a unit pixel may include a first area REG1, a second area REG2, and a third area REG3. The first zone REG1 can be located at the center of the unit pixel. The second zone REG2 may surround the first zone REG1. The third zone REG3 can surround the second zone REG2. The unit pixel can have a ring structure. The first region REG1, the second region REG2, and/or the third region REG3 may each have a ring structure, for example, a circular, polygonal ring structure. More specifically, although an example of a circular unit pixel is illustrated in FIG. 1, an embodiment of the ring structure of the unit pixel is not limited to a circle, but may be, for example, a polygon or a regular polygon.

As will be described in detail below with reference to FIGS. 2 through 12, the first region REG1 may correspond to a floating diffusion region for collecting photocharges. The third region REG3 may correspond to a drain region for discharging photocharges. The second region REG2 between the first region REG1 and the third region REG3 may correspond to a gate region forming at least one gate.

In some embodiments, the unit pixel can be formed by a CMOS process using a semiconductor substrate. Similar to the conventional CMOS process, the floating diffusion region as the first region REG1 and the drain region as the third region REG3 can be formed in the semiconductor substrate using an ion implantation process or the like. The gate region as the second region REG2 may be formed on the semiconductor substrate using a deposition process, an etching process, or the like.

2 illustrates a plan view of an exemplary embodiment of a unit pixel 100 of a light detecting device.

Referring to FIG. 2, the unit pixel 100 can include a floating diffusion region 110, a collection gate 120, a drain gate 130, and a drain region 140. The collection gate 120 may be formed over the semiconductor substrate. The collection gate 120 may have an annular shape surrounding the floating diffusion region 110 formed in the semiconductor substrate when viewed from the top of the unit pixel 100. The drain gate 130 may be formed over the semiconductor substrate. The discharge gate 130 may have an annular shape surrounding the collection gate 120 when viewed from the top. The drain region 140 may be formed in a semiconductor substrate. The drain region 140 may surround the drain gate 130 when viewed from the top. The drain region 140 may have a ring shape.

As will be described in detail below with reference to FIGS. 3 and 4, the unit pixel 100 can be formed on a semiconductor substrate by a CMOS process. The floating diffusion region 110 and the drain region 140 may be formed in a semiconductor substrate. The collection gate 120 and the discharge gate 130 may be formed over the semiconductor substrate.

Although the annular collecting gate 120 and the annular discharge gate 130 are illustrated as having a circular shape in FIG. 2, the embodiment is not limited thereto. For example, the annular collection gate 120 and the annular discharge gate 130 can have a regular polygonal shape, as generally depicted, for example, in FIGS. 15 and 16.

More specifically, for example, in one or more embodiments, the inner edge 140i of the drain region 140 can have the same shape as the collection gate 120 and the drain gate 130. The outer edge 140o of the drain region 140 may have the same or a different shape than the collection gate 120 and/or the discharge gate 130. For example, in the case where a plurality of unit pixels are arranged in an array, the drain regions of the adjacent unit pixels may be spatially coupled to each other and may be integrally formed in the semiconductor substrate. In such embodiments, since the drain region is integrally formed, the outer edge of the drain region may not be defined for a particular unit pixel.

3 and 4 illustrate cross-sectional views of an exemplary embodiment of a unit pixel 100 taken along line I1-I2 of FIG. Since the unit pixel 100 of FIG. 2 has a ring structure that is substantially circularly symmetric about the center, the line I1-I2 can be any line that passes through the center of the unit pixel 100.

Referring to FIG. 3, the unit pixel 100a may include a floating diffusion region 110 formed in the semiconductor substrate 10, a collection gate 120 formed over the semiconductor substrate 10, a discharge gate 130 formed over the semiconductor substrate 10, and formed The drain region 140 in the semiconductor substrate 10. As described above, the floating diffusion region 110, the collection gate 120, the discharge gate 130, and the drain region 140 may each have an annular structure that is substantially circularly symmetric about the vertical central axis VC.

The floating diffusion region 110 and the drain region 140 may extend from the upper surface of the semiconductor substrate 10 into the semiconductor substrate 10. The floating diffusion region 110 and the drain region 140 can be formed using, for example, an ion implantation process or the like. The collection gate 120 and the discharge gate 130 may be formed on the semiconductor substrate 10 using a deposition process, an etching process, or the like. The collection gate 120 and the discharge gate 130 may be spaced apart from the upper surface of the semiconductor substrate 10. Although not illustrated, an insulating layer such as an oxide layer may be formed between the upper surface of the semiconductor substrate 10 and the collection gate 120 and the discharge gate 130.

The collection gate 120 and the discharge gate 130 may comprise, for example, polysilicon, transparent conducting oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), titanium dioxide. (TiO ₂ ) and the like.

More specifically, for example, in one or more embodiments in which light incident on the unit pixel 100a passes through the upper surface of the semiconductor substrate 10, the collection gate 120 and the discharge gate 130 may include, for example, transparent conduction. Oxide. In one or more embodiments in which light incident on the unit pixel 100a passes through the lower surface of the semiconductor substrate 10, the collection gate 120 and the discharge gate 130 may comprise, for example, a non-transparent conductive oxide.

Referring to Figures 3 and 4, the unit pixel 100a can include a photocharge storage region 150. Photocharge storage region 150 may be formed in semiconductor substrate 10 and between floating diffusion region 110 and drain region 140. The photo charge storage region 150 may have a ring shape. The photocharge storage region 150 may be doped with an impurity of a conductivity type opposite to that of the semiconductor substrate 10. Photocharge storage region 150 can be spaced apart from floating diffusion region 110 and drain region 140. The photo-charge storage region 150 can at least partially overlap the collection gate 120 and the discharge gate 130. In some embodiments, the semiconductor substrate 10 can be a P-type semiconductor substrate, and the photo-charge storage region 150 can be doped with N-type impurities. In other embodiments, the semiconductor substrate 10 can be an N-type semiconductor substrate or can include an N-type well, and the photo-charge storage region 150 can be doped with a P-type impurity.

More specifically, as illustrated in FIG. 3, in one or more embodiments, the collection gate 120 can be formed in a ring shape and can cover an inner portion of the photocharge storage region 150. The drain gate 130 may be formed in a ring shape to cover an outer portion of the photo charge storage region 150. The collection gate 120 can be spaced apart from the discharge gate 130. In such embodiments, the photocharge storage region 150 may first be formed into a ring shape, and the gates 120, 130 may then be formed into their respective annular shapes in accordance with the shape of the photocharge storage region 150 to cover the photocharge storage region 150. The individual parts.

The collection gate signal CG and the discharge gate signal DRG may be applied to the collection gate 120 and the discharge gate 130, respectively. In some embodiments, the collection gate signal CG and the drain gate signal DRG can be complementarily activated (see, for example, Figures 5 and 6). If the collection gate signal CG is activated, a channel is formed in a region of the semiconductor substrate 10 below the collection gate 120 or in a region between the photocharge storage region 150 and the floating diffusion region 110. If the discharge gate signal DRG is activated, a channel is formed in a region of the semiconductor substrate 10 below the discharge gate 130 or in a region between the photo charge storage region 150 and the drain region 140.

Therefore, photo charges generated in the semiconductor substrate 10 can be collected into the floating diffusion region 110 at the time of starting the collection of the gate signal CG. When the discharge gate signal DRG is activated, the photocharge generated in the semiconductor substrate 10 can be discharged into the drain region 140. The drain voltage DR applied to the drain region 140 may have an appropriate voltage level according to the conductivity type of the semiconductor substrate 10 and the voltage level of the drain gate signal DRG.

A time-of-flight (TOF) light detecting device measures the light reflected by the object to determine the distance from the object. In general, lock type detection methods using two binary or four binary are widely used to determine the distance.

In a typical lock type detection method, these binary bits are phase shifted from each other by 180 degrees (in the case of two binary bits) or 90 degrees (in the case of four binary bits), and the sinusoidal modulated wave Or a 50% duty cycle pulse signal is used for the binary. For the lock type detection method, a unit pixel having a multi-tie structure in which a photocharge storage region and/or a photocharge generation region are shared by a plurality of floating diffusion regions is generally used.

Referring to Figures 1 through 3, in one or more embodiments, a single floating diffusion region (e.g., 110) can be associated with a photocharge storage region (e.g., 150) such that only one floating diffusion region is required per unit of pixel. (for example, 110) to provide an output. More specifically, as described above, the unit pixel 100 may have a ring structure surrounding the central floating diffusion region 110. In one or more embodiments, the outermost drain region 140 can be included to expel, for example, undesired photocharges generated during undesired periods.

The photocharge collected in the floating diffusion region 110 can be output as a floating diffusion voltage FD via a readout circuit described below, and can be converted into an electrical signal corresponding to the amount of collected photocharge. Thus, in one or more embodiments, unit pixel 100 can be used as a single-link detector that provides output using one floating diffusion region 110.

Referring to FIG. 4, a unit pixel 100b similar to the unit pixel 100a of FIG. 3 may include a floating diffusion region 110 formed in the semiconductor substrate 10', a collection gate 120 formed over the semiconductor substrate 10', and formed in the semiconductor. A discharge gate 130 over the substrate 10', and a drain region 140 formed in the semiconductor substrate 10'. The unit pixel 100b may also include the photocharge storage region 150 described above. Repetitive descriptions of similar components of the exemplary embodiments of FIGS. 3 and 4 will be omitted. That is, in general, only the difference between the unit pixel 100a of FIG. 3 and the unit pixel 100b of FIG. 4 will be described below.

Referring to FIG. 4, the semiconductor substrate 10' of the unit pixel 100b of FIG. 4 may include a plurality of regions 11, 13, and 15 doped with impurities of the same conductivity type and different concentrations. For example, in the case where the semiconductor substrate 10' has P-type conductivity, the semiconductor substrate 10' may sequentially include the P region 11, the P-region 13, and the P+ region 15 from the upper surface of the semiconductor substrate 10'. The P-region 13 is lighter than the P region 11 and the P+ region 15 is heavier than the P region 11.

In the case of using near-infrared (NIR) light having a wavelength ranging from about 700 nm to about 850 nm as a light source in the TOF photodetecting device, a P-type semiconductor substrate can be used as the semiconductor substrate 10'. In one or more embodiments, the thickness of the P-region 13 can range from about 2 μm to about 20 μm. More specifically, for example, in some embodiments, the thickness of the P-region 13 can range from about 3 μm to about 5 μm.

Photons incident on the unit pixel 100b can enter the P-region 13, and an electron-hole pair can be generated in the P-region 13. That is, the P-region 13 may correspond to a main photocharge generating region, and photocharges may be mainly generated in the main photocharge generating region. The photoelectrons generated as minority carriers can be moved into the depletion region of the N-P junction at the boundary between the photocharge storage region 150 and the P-region 13, and can then be diffused and collected in the photocharge storage region 150. The photo-charge storage region 150 can be substantially completely depleted and can be similar to the buried channel of the charge coupled device CCD. Furthermore, since the heavily doped P+ region 15 is located below the P-region 13, photoelectrons generated near the boundary between the P-region 13 and the P+ region 15 may tend to move into the N-P junction portion.

As described above, the semiconductor substrate 10 may include a plurality of photocharge generating regions 11, 13, and 15 doped with impurities of different concentrations, and the sensitivity of the unit pixel 100b may be improved.

5 and 6 illustrate cross-sectional views for describing an example of horizontal movement of photocharges in the unit pixels of Figs. 3 and 4. More specifically, FIG. 5 illustrates the unit pixel 100b of FIG. 4 operating in a collection mode, and FIG. 6 illustrates the unit pixel 100b of FIG. 4 operating in a rejection mode.

Referring to FIG. 5, in the collection mode, the collection gate signal CG applied to the collection gate 120 is activated and the discharge gate signal DRG applied to the discharge gate 130 is deactivated. For example, the collector gate signal CG can be activated to a relatively high voltage of approximately 3.3 V, and the drain gate signal DRG can be deactivated to a relatively low voltage of approximately 0.0 V.

As illustrated in FIG. 5, a potential wall may be formed between the drain region 140 and the photocharge storage region 150 and may block the movement of photoelectrons. The photoelectrons diffused into the photocharge storage region 150 may be collected in the floating diffusion region 110 via a channel formed between the photocharge storage region 150 and the floating diffusion region 110 near the upper surface of the semiconductor substrate 10'. Since the unit pixel has a ring structure, the photoelectrons can move horizontally toward the center (that is, in the centripetal direction), and thus can be collected in the floating diffusion region 110.

Referring to FIG. 6, in the reject mode, the collection gate signal CG applied to the collection gate 120 is deactivated and the discharge gate signal DRG applied to the discharge gate 130 is activated. For example, the collector gate signal CG can be deactivated to a relatively low voltage of about 0.0 V, and the drain gate signal DRG can be activated to a relatively high voltage of about 3.3 V.

As illustrated in FIG. 6, a potential wall can be formed between the floating diffusion region 110 and the photo-charge storage region 150 and can block the movement of photoelectrons. Photoelectrons diffused into the photocharge storage region 150 may be discharged into the drain region 140 via a channel formed between the photocharge storage region 150 and the drain region 140 near the upper surface of the semiconductor substrate 10'. Since the unit pixel has a ring structure, the photoelectrons can be moved horizontally away from the center (i.e., in the centrifugal direction), and thus can be discharged into the drain region 140.

As illustrated in Figures 5 and 6, the drain voltage DR can be maintained at a suitable voltage level bias voltage. For example, the drain voltage DR may be a power supply voltage of a photodetecting device including a unit pixel (eg, 100b).

One or more embodiments including, for example, a unit pixel (e.g., 100a, 100b) of a ring structure as described above may allow photocharges to be moved horizontally in a centripetal direction according to gate signals CG and DRG. It is collected or discharged by horizontal movement in the centrifugal direction, and the sensitivity and/or the signal-to-noise ratio of the unit pixels (for example, 100a, 100b) can be improved. One or more embodiments of unit pixels (e.g., 100a, 100b) may enable the discharge mode of the desired charge carriers to the floating diffusion region 110 and the discharge of undesired charge carriers to the drain The rejection mode of zone 140 is used to obtain accurate depth information.

Although the exemplary unit pixel 100b operating in the collection mode and the rejection mode is illustrated in FIGS. 5 and 6, respectively, the unit pixel 100b can be operated in other modes depending on the manner in which the voltage is applied. For example, an intermediate level bias voltage can be applied to the collection gate 120 and the discharge gate 130. In one or more embodiments, carriers generated in P-region 13 may be collected in photo-charge storage region 150, and drain region 140 may serve as an anti-halation dipole. Thereafter, the carriers collected in the photocharge storage region 150 may be transferred to the floating diffusion region 110 when the collection of the gate signal CG is initiated. By applying this pattern to unit pixels, correlated double sampling (CDS) can be performed, and image information and depth information can be provided.

The specific structure of the unit pixel used to implement the potential distribution illustrated in FIGS. 5 and 6 and the specific voltage levels of the gate signals CG and DRG and the drain voltage DG can be determined by process simulation and/or modeling. .

FIG. 7 illustrates a plan view of another exemplary embodiment of a unit pixel 200 of a light detecting device. 8 and 9 illustrate cross-sectional views of an exemplary embodiment of the unit pixel 200 of FIG. In general, only the difference between the unit pixel 200 of FIG. 7 and the unit pixel 100 of FIG. 2 will be described below.

Referring to FIG. 7, unit pixel 200 can include floating diffusion region 210, collection gate 220, drain gate 230, and drain region 240. Similar to the unit pixel 100 of FIG. 2, the collection gate 220 may be formed on the semiconductor substrate 101 when viewed from the top of the unit pixel 200. The collection gate 220 may have an annular shape surrounding a floating diffusion region 210 formed in the semiconductor substrate 101. The discharge gate 230 may be formed on the semiconductor substrate 101. The discharge gate 230 may have an annular shape surrounding the collection gate 220. The drain region 240 may be formed in the semiconductor substrate 101, and the drain region 240 may surround the discharge gate 230. Referring to FIG. 7, unit pixel 200 can include a fixed layer 270. The pinned layer 270 can extend between the collector gate 220 and the drain gate 230.

More specifically, referring to FIG. 8, the unit pixel 200a may further include a photocharge storage region 250 formed in the semiconductor substrate 101 and formed in a ring shape between the floating diffusion region 210 and the drain region 240. The photocharge storage region 250 may be doped with an impurity of a conductivity type opposite to that of the semiconductor substrate 101.

In the unit pixel 100 of FIG. 2, the collection gate 120 and the discharge gate 130 may be formed to cover portions of the photocharge storage region 150, respectively. In the exemplary embodiment of FIG. 8, the collection gate 220 and the drain gate 230 do not overlap the photocharge storage region 250. Referring to FIG. 8, the unit pixel 200a of FIG. 8, the collection gate 220 may be formed in a ring shape between the photocharge storage region 250 and the floating diffusion region 210, and the discharge gate 230 may be in the photocharge storage region 250 and the drain. The regions 240 are formed in a ring shape.

Referring to FIG. 8, the pinned layer 270 may be formed in a ring shape in the semiconductor substrate 101. The pinned layer 270 can cover the photo charge storage unit 250. The pinned layer 270 may be doped with an impurity of a conductivity type opposite to that of the photocharge storage unit 250. For example, the photo-charge storage unit 250 may be doped with an N-type impurity, and the fixed layer 270 may be doped with a P-type impurity. The pinned layer 270 can reduce dark current and can make the potential more uniform throughout the photocharge storage unit 250 by reducing the effects of defects that may be present at the surface of the semiconductor substrate 101. Furthermore, by reducing the doping concentration of the photo-charge storage unit 250, the potential of the discharge gate 230 and the collection gate 220 can become steep, which can result in rapid horizontal movement of the photocharge.

Compared with the unit pixel 200a of FIG. 8, the semiconductor substrate 101' of the unit pixel 200b of FIG. 9 includes a plurality of photocharge generating regions 11, 13, and 15 doped with impurities of the same conductivity type and different concentrations.

For example, in the case where the semiconductor substrate 101' has P-type conductivity, the semiconductor substrate 101' may sequentially include the P region 11, the P-region 13, and the P+ region 15 from the upper surface of the semiconductor substrate 101'. The P-region 13 is lighter than the P region 11 and the P+ region 15 is heavier than the P region 11. In this case, similar to the P+ region 15, the pinned layer 270 may be heavily doped with P-type impurities.

As described above, since the heavily doped P+ region 15 is located below the P-region 13, photoelectrons generated near the boundary between the P-region 13 and the P+ region 15 may tend to move into the N-P junction portion. Therefore, the sensitivity of the unit pixel 200b can be improved by forming a plurality of photocharge generating regions 11, 13 and 15 doped with impurities of different concentrations in the semiconductor substrate 101'.

FIG. 10 illustrates a plan view of another exemplary embodiment of a unit pixel 300 of a light detecting device. 11 and 12 illustrate cross-sectional views of an exemplary embodiment of the unit pixel 300 of FIG.

Referring to FIG. 10, the unit pixel 300 may include a floating diffusion region 310, a collection gate 320, a discharge gate 330, a drain region 340, and a photoresist gate 370. Referring to FIG. 10, similar to the unit pixel 100 of FIG. 2 and the unit pixel 200 of FIG. 7, the collection gate 320 may be formed on the semiconductor substrate 201 when viewed from the top of the unit pixel 300. The collection gate 320 may have an annular shape surrounding the floating diffusion region 310 formed in the semiconductor substrate 201. The drain gate 330 may be formed over the semiconductor substrate 201. The discharge gate 330 may have an annular shape surrounding the collection gate 320. The drain region 340 may be formed in the semiconductor substrate 201. The drain region 340 can surround the drain gate 330.

As illustrated in FIG. 11, the unit pixel 300a may further include a photo charge storage region 350. The photocharge storage region 350 may be formed in a ring shape in the semiconductor substrate 201 and between the floating diffusion region 310 and the drain region 340. The photocharge storage region 350 may be doped with an impurity of a conductivity type opposite to that of the semiconductor substrate 10.

In the unit pixel 100 of FIG. 2, the collection gate 120 and the discharge gate 130 may be formed to cover portions of the photocharge storage region 150, respectively. In the exemplary embodiment of FIG. 11, the collection gate 320 and the drain gate 330 do not overlap the photocharge storage region 350. In the unit pixel 300a of FIG. 11, the collection gate 320 is formed in a ring shape between the photo charge storage region 350 and the floating diffusion region 310, and the discharge gate 330 is between the photo charge storage region 350 and the drain region 340. Formed into a ring shape.

Referring to FIG. 11, the unit pixel 300a may include a photo-gate 370 formed over the semiconductor substrate 201 and formed in a ring shape between the collection gate 320 and the discharge gate 330 to cover the photo-charge storage unit. 350. The photogate 370 can be biased by a predetermined bias voltage VB instead of the pinned layer 270 illustrated in FIG. 8 to induce an appropriate potential distribution. The photo-gate 370 to which the bias voltage VB is applied can reduce dark current, and can make the potential more uniform throughout the photo-charge storage unit 350 by reducing the effect of defects that may exist at the surface of the semiconductor substrate 201. Furthermore, by reducing the doping concentration of the photo-charge storage unit 350, the potential of the discharge gate 330 and the collection gate 320 can become steep, which results in rapid horizontal movement of the photocharge.

Compared with the unit pixel 300a of FIG. 11, the semiconductor substrate 201' of the unit pixel 300b of FIG. 12 includes a plurality of photocharge generating regions 11, 13, and 15 doped with impurities of the same conductivity type and different concentrations.

For example, in the case where the semiconductor substrate 201' has P-type conductivity, the semiconductor substrate 201' may sequentially include the P region 11, the P-region 13, and the P+ region 15 from the upper surface of the semiconductor substrate 201'. The P-region 13 is lighter than the P region 11 and the P+ region 15 is heavier than the P region 11.

As described above, since the heavily doped P+ region 15 is located below the P-region 13, photoelectrons generated near the boundary between the P-region 13 and the P+ region 15 may tend to move into the N-P junction portion. One or more embodiments of the unit pixel 300b may enable unit pixels to be improved by forming a plurality of photocharge generating regions 11, 13 and 15 doped with impurities of different concentrations in the semiconductor substrate 201' (for example, 300b) sensitivity.

13 through 17 illustrate diagrams of an illustrative embodiment of a pixel array.

Referring to Figure 13, pixel array 410 includes a plurality of unit pixels 412 arranged in a rectangular grid. The unit pixel 412 may have a ring structure and may correspond to the unit pixels (eg, 100, 200, 300) described above with reference to FIGS. 1 through 12. The rectangular grid may comprise a square 415 defined by four adjacent unit pixels, and one unit pixel may be located at each grid point.

In the case where the unit pixels 412 are arranged in an array, the drain regions 417 adjacent to the unit pixels may be spatially coupled to each other and may be integrally formed in the semiconductor substrate. In such embodiments, since the drain region is integrally formed, the outer edge of the drain region may not be defined for a particular unit pixel. In accordance with an exemplary embodiment, in the pixel array 410 comprising unit pixels 412, since the integrated bungee region 417 performs an anti-halation function, an additional anti-halation structure may not be required.

Moreover, in using one or more of the features described above, since all of the drain regions can be substantially coupled to each other and each unit pixel can be used as a single connector detector that provides an output Operation, thus improving the overall layout tolerance.

Referring to Figure 14, pixel array 420 includes a plurality of unit pixels 412 arranged in a triangular grid. The unit pixel 412 may have the ring structure described above with reference to FIGS. 1 through 12. The triangular grid may comprise a triangle 425 defined by three adjacent unit pixels, and one unit pixel may be located at each grid point.

Referring to Figure 15, pixel array 430 includes a plurality of unit pixels 432 arranged in a rectangular grid. The unit pixel 432 may have the ring structure described above with reference to FIGS. 1 through 12. More specifically, for example, as illustrated in FIG. 15, one or more of the unit pixels 432 may have an octagonal ring structure.

Referring to Figure 16, pixel array 440 includes a plurality of unit pixels 442 arranged in a triangular grid. The unit pixel 442 may have the ring structure described above with reference to FIGS. 1 through 12. More specifically, for example, as illustrated in FIG. 16, one or more of the unit pixels 442 may have a hexagonal ring structure.

As illustrated in FIGS. 13-16, a unit pixel according to an exemplary embodiment may have a circular or any polygonal ring structure. For example, the unit pixel can have a rectangular ring structure. Further, unit pixels having any ring structure may be arranged in a rectangular grid or a triangular grid.

Referring to Figure 17, pixel array 450 includes a plurality of unit pixels 452 arranged in a triangular grid. In some embodiments, the floating diffusion regions of two or more unit pixels included in the pixel array 450 may be electrically coupled to each other, and the two or more unit pixels may form a pixel group. .

For example, as illustrated in FIG. 17, the floating diffusion regions of the seven unit pixels 452 can be electrically coupled to each other, and the seven unit pixels 452 can form a pixel group 451. FIG. 17 illustrates an example of a pixel array 450 that is regularly arranged by such pixel groups 451. The electrical connection 453 of the floating diffusion region can include an interlayer connection (such as a via) that electrically couples the floating diffusion region to the upper metal layer and patterned wiring in the metal layer. In one or more embodiments, the sensitivity of the TOF detection device can be improved and can be relatively correlated by grouping, for example, a plurality of unit pixels 452 of the pixel array 450 used in the TOF photodetection device. Higher sensitivity.

In one or more embodiments, unit pixels can be regularly omitted or skipped at certain grid points. More specifically, for example, at a region RDC where no unit pixel is configured, a readout circuit can be placed to provide an output of unit pixel 452 or pixel group 451. Each readout circuit can include a transistor as described below with reference to FIG. In one or more embodiments, as described above, the overall design tolerances of the pixel array 450 can be improved since the unit pixels 452 can be grouped and the readout circuitry can be efficiently placed.

FIG. 18 illustrates a schematic diagram of an illustrative embodiment of a readout circuit 30 for providing an output of a unit pixel (e.g., unit pixel 100 of FIG. 2).

Referring to Figure 18, readout circuitry 30 can be used to read the output of a unit pixel (e.g., unit pixel 100 of Figure 2). More specifically, readout circuitry 30 can convert the output of unit pixel 100 into an electrical signal. The converted output from the readout circuitry 30 can be provided to an external circuit (not shown). As described above, the unit pixel 100 can have a ring structure and can operate as a single connector detector. Moreover, as described above, the unit pixel 100 can include a floating diffusion region 110, a collection gate 120, a drain gate 130, and a drain region 140.

Referring to FIG. 18, the readout circuit 30 can include a source follower transistor T1, a selection transistor T2, and a reset transistor T3. The reset transistor T3 can initialize the voltage FD of the floating diffusion region 110 to the reset voltage VRST in response to the reset signal RST. Floating diffusion region 110 is coupled to the gate of source follower transistor T1. If the selection transistor T2 is turned on in response to the selection signal SEL after the photocharge is collected, the electric signal corresponding to the voltage FD of the floating diffusion region 110 is supplied to the external circuit via the output line LO.

As described above, the voltage FD of the floating diffusion region 110 corresponding to the output of the unit pixel 100 can be supplied to the external circuit by the readout circuit 30 illustrated in FIG. In one or more embodiments, readout circuitry 30 can be disposed at an unconfigured unit pixel region (e.g., RDC of Figure 17). Alternatively, for example, in one or more embodiments, readout circuitry 30 can be disposed outside of the pixel array.

FIG. 19 illustrates a block diagram of an exemplary embodiment of a light detecting device 600.

Referring to FIG. 19, the light detecting device 600 can include a sensing unit 610 and a control unit 630 that controls the sensing unit 610. The sensing unit 610 can include at least one unit pixel that converts the received light RL into an electrical signal DATA. The unit pixel can be a single connector pixel of the ring structure described above with reference to Figures 1 through 12, such as unit pixels 100, 200, 300. For example, the unit pixel may include: a floating diffusion region formed in the semiconductor substrate; an annular collecting gate formed on the semiconductor substrate such that the collecting gate surrounds the floating diffusion region; and an annular discharge gate formed on the Above the semiconductor substrate, the discharge gate surrounds the collection gate; and a drain region is formed in the semiconductor substrate such that the drain region surrounds the discharge gate.

The control unit 630 may include: a light source LS that emits light EL to the object 60; a binary signal generator BN that generates a collection gate signal CG and a discharge gate signal DRG; and a controller CTRL that controls the light detecting device 600 The overall operation.

The light source LS can emit light EL having a predetermined wavelength. For example, the light source LS can emit infrared light or near-infrared light. The emitted light EL generated by the light source LS can be focused on the object 60 by the lens 51. The light source LS can be controlled by the controller CTRL to output the emitted light EL such that the intensity of the emitted light EL periodically changes. For example, the emitted light EL can be a burst signal having a continuous pulse. The light source LS can be implemented by a light emitting diode LED, a laser diode, or the like.

The binary signal generator BN generates a collection gate signal CG and a discharge gate signal DRG for operating the ring unit pixels included in the sensing unit 610. The collection gate signal CG and the discharge gate signal DRG can be activated complementarily. As described above, if the collection gate signal CG is activated, a channel is formed in a region of the semiconductor substrate below the collection gate or in a region between the photo charge storage region and the floating diffusion region. If the discharge gate signal DRG is activated, a channel is formed in the region of the semiconductor substrate below the discharge gate or in the region between the photocharge storage region and the drain region.

Therefore, when the gate signal CG is started to be collected, the photocharge generated in the semiconductor substrate is collected in the floating diffusion region, and when the discharge gate signal DRG is activated, the photocharge generated in the semiconductor substrate is discharged into the drain region. .

As will be described later, the collection gate signal CG may include a plurality of binary signals CGi whose number of cycles is increased according to a phase difference with respect to the emitted light EL, and the light detecting device 600 may convert the received light RL by The electrical signal is derived to obtain depth information, wherein the received light RL has been reflected by the object 60 and enters the sensing unit 610 via the lens 53.

In one or more embodiments, the sensing unit 610 can include the unit pixel (or pixel group) described above and an analog digital conversion unit ADC for converting the output of the unit pixel into a digital signal.

In one or more embodiments, the sensing unit 610 can include a pixel array PX including a plurality of unit pixels (or a plurality of pixel groups) arranged in an array. In such embodiments, the sensing unit 610 can include an analog digital conversion unit ADC and selection circuits ROW, COL for selecting a particular unit pixel in the pixel array PX.

In one or more embodiments, the analog-to-digital conversion unit ADC can perform row analog digital conversion of analog signals in parallel using a plurality of analog-to-digital converters coupled to a plurality of row lines, respectively, or can perform single analog-to-digital conversion A serial analog to digital conversion of analog signals.

In one or more embodiments, the analog digital conversion unit ADC can include a correlated double sampling (CDS) unit for extracting valid signal components.

In some embodiments, the CDS unit may perform analog double sampling (ADS), which extracts valid signal components based on a proportioned signal representing a reset component and an analog data signal representing the signal component.

In other embodiments, the CDS unit may perform digital double sampling (DDS), which converts the class-specific signal and the analog data signal into two digital signals to extract between the two digital signals. The difference is taken as the effective signal component.

In still other embodiments, the CDS unit may perform dual correlation double sampling, dual correlation double sampling performing analog double sampling and digital double sampling.

Figure 20 illustrates a flow chart of an illustrative embodiment of a method of measuring distance.

Referring to Fig. 19 and Fig. 20, the light source LS emits light EL to the object 60 (S110). The sensing unit 610 converts the received light RL (which has been reflected by the object 60 and enters the sensing unit 610) into an electrical signal using a plurality of variable binary signals (S120), wherein the plurality of variable binary signals The number of cycles is increased in accordance with the phase difference with respect to the emitted light EL. The plurality of variable binary signals may be included in the complementary gate signals CG and DRG generated by the binary signal generator BN. The collection gate signal CG and the discharge gate signal DG including the plurality of variable binary signals will be described in detail below with reference to FIGS. 21 to 25. The controller CTRL calculates the distance from the object 60 based on the data signal DATA supplied from the sensing unit 610 (S130).

Figure 21 illustrates an illustrative embodiment for describing a timing diagram of signals used to convert received light into electrical signals.

Referring to Fig. 21, the emitted light EL generated by the light source LS of the photodetecting device 600 may be a burst signal including a pulse having a predetermined period To. The emitted light EL is reflected by the object 60 located at a distance Z, and reaches the photodetecting device 600 as the received light RL. The distance Z of the light detecting device 600 to the object 60 can be calculated using an equation expressed as "Tf=2Z/C", where C represents the speed of light, and Tf represents the phase between the emitted light EL and the received light RL difference.

A plurality of binary signals can be used to obtain a phase difference Tf between the emitted light EL and the received light RL. Fig. 21 illustrates a binary signal CGi whose phase difference with respect to the emitted light EL is Ti and the start duration of each cycle To is Wi. The relationship between a plurality of binary signals will be described below with reference to FIGS. 22 and 23. For example, the binary signal CGi and the inverted binary signal DRGi can be used as the gate signal of the unit pixel 100 described above with reference to FIGS. 2 through 6.

The binary signal CGi can be applied to the collection gate 120 as the collection gate signal CG, and the inverted binary signal DRGi can be applied to the discharge gate 130 as the discharge gate signal DRG. When a photocharge is generated in response to the received light RL in the semiconductor substrate 10, the generated photocharge is discharged into the drain region 140 during the first time Tr, and will be generated during the second time Tc. The photocharge is collected in the floating diffusion region 110.

This rejection and collection of photocharges is repeated during the sensing time TS, the number of repetitions corresponding to the number of cycles included in the binary signal CGi. During the readout time TR, the amount of photocharge collected in the diffusion floating region 110 can then be output by the readout circuit 30 illustrated in FIG.

22 and 23 illustrate an exemplary timing diagram of an example of a variable binary signal that can be used by the method of measuring distance illustrated in FIG.

Referring to Fig. 22, a plurality of variable binary signals CG1, CG2, ..., CGk have a number of cycles which are increased in accordance with phase differences T2, ..., Tk with respect to the emitted light EL. For example, the first binary signal CG1 having a phase difference of 0 with respect to the emitted light EL may have the lowest number of cycles, and the number of cycles may gradually increase as the phase difference with respect to the emitted light EL increases, and is relative to The kth binary signal CGk having the largest phase difference of the emitted light EL may have the highest number of cycles. In other words, the first sensing time TS1 (=To*nl) using the first binary signal CG1 is the shortest, and the kth sensing time TSk (=To*nk) using the kth binary signal CGk is the longest.

As the distance Z between the light detecting device 600 and the object 60 increases, or as the phase difference Tf between the emitted light EL and the received light RL increases, the intensity of the received light RL and the square of the distance Z It decreases in inverse proportion. Therefore, as described above, since the number of cycles included in the plurality of binary signals CGi increases according to the phase difference Ti with respect to the emitted light EL, the sensing time TSi may be from the distance from the object 60 Z increases and increases, thereby improving the signal-to-noise ratio (SNR). In addition, the gain can be improved by the viewing distance Z to improve the dynamic range of the photodetecting device 600.

In some embodiments, the plurality of binary signals CGi may be varied such that the duty ratio (Wi/To) is increased according to a phase difference Ti relative to the emitted light EL. That is, the start duration Wi of each period To of the plurality of binary signals Cgi may increase according to the phase difference Ti with respect to the emitted light EL.

In general, as the distance Z from the object 60 increases, the necessity of the accuracy of the distance Z can be reduced. Therefore, the start duration Wi of the plurality of binary signals CGi can be increased according to the distance Z to increase the gain, thereby improving the signal-to-noise ratio.

The plurality of binary signals CGi illustrated in FIG. 22 can be applied to different unit pixels, respectively. For example, in the case where a plurality of unit pixels are arranged in an array having a plurality of columns and a plurality of rows, the same binary signal can be applied to the unit pixels of the same column, and different binary signals can be applied. To the different units of the pixel. In this case, the respective sensing time TS1 may be substantially followed by a corresponding readout time TR, and thus an effective rolling frame operation may be performed in the image sensor.

FIG. 23 illustrates an exemplary timing chart of an example of applying a plurality of variable binary signals CGi to one unit pixel. For convenience, only two binary signals CG2 and CGk are amplified in FIG. 23, and the characteristics of the other binary signals may be similar. That is, the plurality of variable binary signals CGi have a number of cycles ni increased according to the phase difference Ti with respect to the emitted light EL. Therefore, the first sensing time TS1 (=To*n1) using the first binary signal CG1 which is the smallest with respect to the phase difference T1 of the emitted light EL is the shortest, and the phase difference T1 with respect to the emitted light EL is the largest. The kth sensing time TSk (=To*nk) of the kth binary carry signal CGk is the longest. As described above, the plurality of binary signals CGi may be varied such that the duty ratio (Wi/To) is increased in accordance with the phase difference Ti with respect to the emitted light EL. In the case where the plurality of binary signals CGi are applied to one unit pixel, the respective sensing times TSi may be substantially followed by corresponding reading times TR, respectively.

Figure 24 illustrates a diagram of an exemplary variable binary signal. Figure 25 illustrates a graph of an exemplary phase of the variable binary signal illustrated in Figure 24, the length of the start-up duration, and the number of cycles.

More specifically, FIG. 24 illustrates an example of a plurality of variable binary signals CG1 to CG10 that can be used to measure the phase difference Tf between the emitted light EL and the received light RL. For example, in the case where the 3D image sensor providing depth information and moving image information is operated at 30 fps, a pulse train signal containing about 30 million light pulses having a duty ratio of about 20% can be used. The emitted light EL. In such embodiments, for example, when the readout time is ignored, the number of cycles of the emitted light EL corresponding to one frame may be about one million. In FIG. 24, the width of each binary signal CGi may represent the startup duration Wi. As illustrated in Figure 24, the startup durations of adjacent binary signals may overlap each other.

For example, about 50% of the start duration W2 of the second binary signal CG2 may overlap with the start duration W3 of the third binary signal CG3, and the start duration W3 of the third binary signal CG3 may be relative to the first The start-up duration W2 of the binary carry signal CG2 is increased by about 10%. An example of the time difference Ti of the variable binary signal CGi, the startup duration Wi, and the number of cycles ni is illustrated in FIG. In Fig. 25, M represents the sum of the numbers ni of all the cycles.

As described above, the variable binary signal CGi can be used to collect the photocharge, and the distance Z from the object can be calculated based on the amount of photocharge collected and the phase of the variable binary signal CGi.

Figure 26 illustrates a flow chart of an illustrative embodiment of a method of measuring distance.

Referring to Figures 19 and 26, the light source LS emits light EL to the object 60 (S210). The sensing unit 610 converts the received light RL (which has been reflected by the object 60 and enters the sensing unit 610) into an electrical signal using a variable binary signal (S220). As described above, the number of cycles included in the variable binary signal can be increased in accordance with the phase difference with respect to the emitted light EL. Furthermore, the duty ratio of the variable binary signal can be increased in accordance with the phase difference with respect to the emitted light EL. The controller CTRL calculates the distance from the object 60 based on the data signal DATA supplied from the sensing unit 610 (S230). The controller CTRL controls the binary signal generator BN to adjust the phase of the binary signal and the duty ratio to concentrate on the phase corresponding to the calculated distance (S240). A plurality of binary signals having adjusted phases and duty ratios may be used to correct the distance from the object (S250).

Figure 27 illustrates a diagram of an exemplary variable binary signal. Figure 28 illustrates a diagram of an exemplary phase of the variable binary signal illustrated in Figure 27, the length of the start-up duration, and the number of cycles. Figure 29 illustrates a diagram of an exemplary adjusted binary signal.

More specifically, FIG. 27 illustrates an example of four variable binary signals CG1, CG2, CG3, and CG4 that can be used to measure the phase difference Tf between the emitted light EL and the received light RL. In Fig. 27, an example of the light RL received in the case of using the emitted light EL having a duty ratio of about 50% is illustrated by a broken line. An example of the time difference Ti of the four binary signals CG1, CG2, CG3, and CG4, the startup duration Wi, and the number of cycles ni is illustrated in FIG. As illustrated in FIGS. 27 and 28, the four binary signals CG1, CG2, CG3, and CG4 may have the same startup duration Wi, and the number of cycles ni is increased according to the phase difference Ti with respect to the emitted light EL.

The controller CTRL can calculate the distance from the object 60 based on the electrical signal DATA provided from the sensing unit 610 using the binary signal CGi, and can control the binary signal generator BN to adjust the phase of the binary signal CGi and the duty The rate is concentrated on the phase corresponding to the calculated distance. Fig. 29 illustrates an example of the binary carry signal CGi' adjusted in this manner.

As illustrated in Figure 29, more accurate data can be obtained and the distance Z from the object can be accurately corrected by using a binary signal CGi' adjusted to focus on the pulse of the received light RL. For example, in the face recognition security system, the average distance from the face can be measured using the carry signal CGi of FIG. 27 and FIG. 28, and the binary carry signal CGi' of FIG. 29 adjusted based on the measurement result can be used. To scan the face again around the average distance.

Figure 30 illustrates a diagram of an illustrative embodiment of a sensing unit of a three-dimensional image sensor. More specifically, FIG. 30 illustrates an example of the sensing unit 610a in the case where the light detecting device 600 of FIG. 19 is a three-dimensional image sensor.

Referring to FIG. 30, the sensing unit 610a may include a pixel array C/Z PX, a color pixel selection circuit CROW and CCOL, a depth pixel selection circuit ZROW and ZCOL, in which a plurality of color pixels and a plurality of depth pixels are arranged, Color Pixel Converter CADC, and Deep Pixel Converter ZADC. The color pixel selection circuits CROW and CCOL and the color pixel converter CADC can provide image information CDATA by controlling the color pixels contained in the pixel array C/Z PX, and the depth pixel selection circuits ZROW and ZCOL and the depth drawing The prime converter ZADC can provide depth information ZDATA by controlling the depth pixels contained in the pixel array C/Z PX.

As described above, in the three-dimensional image sensor, the components for controlling the color pixels and the components for controlling the depth pixels can operate independently to provide the color data CDATA of the image and the depth data ZDATA.

31 illustrates a diagram of an illustrative embodiment of a pixel array that can be used in the sensing unit of FIG.

Referring to Fig. 31, the pixel array C/Z PX includes a plurality of unit pixels R, G, B, and Z arranged in a triangular grid. The unit pixels R, G, B, and Z may have the ring structure described above with reference to FIGS. 2 through 12. The unit pixels R, G, B, and Z include a plurality of color pixels R, G, and B and a plurality of depth pixels Z. The color pixels R, G, and B may include a green pixel G, a red pixel R, and a blue pixel B. As illustrated in FIG. 31, color pixels R, G, and B perform light detection on a unit pixel basis to improve resolution, and depth pixel Z performs light detection on a pixel group basis. To improve sensitivity. For example, as described above, the floating diffusion regions of the four depth pixels Z included in one pixel group 80 can be electrically coupled to each other, and the four depth pixels Z of one pixel group 80 can be integrated. Operation.

The color pixel selection circuits CROW and CCOL and the color pixel converter CADC perform sensing operations and readout operations on the color pixels R, G, and B, and the depth pixel selection circuits ZROW and ZCOL and the depth pixel converter ZADC A sensing operation and a readout operation can be performed on the depth pixel Z. The plurality of variable binary signals CGi described above can be applied to the gate of the depth pixel Z to obtain the material ZDATA representing the depth information. The color pixels R, G, and B and the depth pixel Z can operate at different frequencies in response to different gate signals.

Figure 32 illustrates a block diagram of an illustrative embodiment of a camera including a three dimensional image sensor.

Referring to FIG. 32, the camera 800 includes a light receiving lens 810, a three-dimensional image sensor 900, and an engine unit 840. The 3D image sensor 900 can include a 3D image sensor wafer 820 and a light source module 830. According to an embodiment, the 3D image sensor wafer 820 and the light source module 830 may be implemented by separate devices, or at least a portion of the light source module 830 may be included in the 3D image sensor wafer 820. In some embodiments, the light receiving lens 810 can be included in the three dimensional image sensor wafer 820.

The light receiving lens 810 can focus the incident light onto a light receiving area of the three dimensional image sensor wafer 820 (eg, a depth pixel and/or a color pixel included in the pixel array). The three-dimensional image sensor wafer 820 can generate data DATA1 including depth information and/or color image information based on incident light passing through the light receiving lens 810. For example, the data DATA1 generated by the three-dimensional image sensor chip 820 may include depth data generated using infrared light or near-infrared light emitted from the light source module 830 and RGB data of a Bayer pattern generated using external visible light. The 3D image sensor wafer 820 can provide the data DATA1 to the engine unit 840 based on the clock signal CLK. In some embodiments, the 3D image sensor die 820 can interface with the engine unit 840 via the mobile industry processor interface MIPI and/or the camera serial interface CSI.

The engine unit 840 controls the three-dimensional image sensor 900. The engine unit 840 can process the data DATA1 received from the 3D image sensor wafer 820. For example, the engine unit 840 can generate three-dimensional color data based on the data DATA1 received from the three-dimensional image sensor wafer 820. In other examples, engine unit 840 may generate YUV data including luminance components, blue luminance difference components, and red luminance difference components, or compressed data based on RGB data contained in data DATA1 (eg, joint imaging expert group (joint) Photography experts group; JPEG) data). Engine unit 840 can be coupled to host/application 850 and can provide data DATA2 to host/application 850 based on primary clock MCLK. In addition, the engine unit 840 can interface with the host/application 850 via a serial peripheral interface (SPI) and/or an inter integrated circuit (I2C).

33 illustrates a block diagram of an illustrative embodiment of an interface that may be used in the computing system of FIG.

Referring to FIG. 33, computing system 1000 can include processor 1010, memory device 1020, storage device 1030, input/output device 1040, power supply 1050, and three-dimensional image sensor 900. Although not illustrated in FIG. 33, computing system 1000 can further include communication with a video card, sound card, memory card, USB device, or other electronic device.

The processor 1010 can perform various calculations or tasks. According to an embodiment, the processor 1010 can be a microprocessor or a CPU. The processor 1010 can communicate with the memory device 1020, the storage device 1030, and the input/output device 1040 via an address bus, a control bus, and/or a data bus. In some embodiments, processor 1010 can be coupled to an expansion bus, such as a peripheral component interconnection (PCI) bus. The memory device 1020 can store data for operating the computing system 1000. For example, the memory device 1020 can be implemented by: a dynamic random access memory (DRAM) device, a mobile DRAM device, and a static random access memory (SRAM) device. Phase random access memory (PRAM) device, ferroelectric random access memory (FRAM) device, resistive random access memory (RRAM) device And/or a magnetic random access memory (MRAM) device. The storage device may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like. Input/output device 1040 can include input devices (eg, a keyboard, keypad, mouse, etc.) and output devices (eg, printers, display devices, etc.). Power supply 1050 supplies an operating voltage for computing system 1000.

The three-dimensional image sensor 900 can communicate with the processor 1010 via a bus or other communication link. As described above, the three-dimensional image sensor 900 can include a unit pixel having a ring structure that operates as a single-joint detector. Moreover, as described above, the three-dimensional image sensor 900 can use a plurality of variable binary signals to measure the distance from the object. Therefore, sensitivity and signal to noise ratio can be improved. The 3D image sensor 900 can be integrated into the processor with the processor 1010, or the 3D image sensor 900 and the processor 1010 can be implemented as separate wafers.

The three-dimensional image sensor 900 can be packaged in various forms, such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic lead wafer. Plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, wafer in wafer form, on-board wafer ( Chip on board; COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP) , small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), A multi-chip package (MCP), a wafer-level fabricated package (WFP), or a wafer-level processed stack package (WSP).

Computing system 1000 can be any computing system that uses a three-dimensional image sensor. For example, computing system 1000 can include a digital camera, a mobile phone, a smart phone, a portable multimedia player (PMP), a personal digital assistant (PDA), and the like.

FIG. 34 illustrates a block diagram of an exemplary embodiment of an interface that may be used in the computing system of FIG.

Referring to Figure 34, computing system 1100 can be implemented by using or supporting a data processing device of the Mobile Industry Processor Interface (MIPI) interface. Computing system 1100 can include an application processor 1110, a three-dimensional image sensor 1140, a display device 1150, and the like. The CSI host 1112 of the application processor 1110 can perform serial communication with the CSI device 1141 of the 3D image sensor 1140 via a camera serial interface (CSI). In some embodiments, CSI host 1112 can include a deserializer (DES), and CSI device 1141 can include a serializer (SER). The DSI host 1111 of the application processor 1110 can perform serial communication with the DSI device 1151 of the display device 1150 via a display serial interface (DSI).

In some embodiments, DSI host 1111 can include a serializer (SER), and DSI device 1151 can include a deserializer (DES). Computing system 1100 can further include a radio frequency (RF) wafer 1160 that performs communication with application processor 1110. The physical layer (PHY) 1113 of the computing system 1100 and the physical layer (PHY) 1161 of the RF chip 1160 can perform data communication based on the MIPI DigRF. The application processor 1110 may further include a DigRF master (DigRF MASTER) 1114 that controls data communication of the PHY 1161.

The computing system 1100 can further include a global positioning system (GPS) 1120, a storage 1170, a MIC 1180, a DRAM device 1185, and a speaker 1190. In addition, the computing system 1100 can perform communication using: ultra wideband (UWB) 1120, wireless local area network (WLAN) 1220, and global interoperability for microwave access; WIMAX) 1230 and so on. However, the structure and interface of the electrical device 1000 are not limited thereto.

The features and/or embodiments described herein are applicable to any light detecting device, such as a three dimensional image sensor that provides image information and depth information about the object. For example, one or more embodiments may be applied to computing systems such as face recognition security systems, desktop computers, laptop computers, digital cameras, three-dimensional cameras, video camcorders, cellular phones, smart Telephones, personal digital assistants (PDAs), scanners, video phones, digital televisions, navigation systems, observing systems, autofocus systems, tracking systems, motion capture systems, image stabilization systems, and more.

The foregoing describes illustrative embodiments and is not to be considered as limiting. While a few exemplifying embodiments have been described, it will be understood by those skilled in the art that many modifications of the exemplary embodiments are possible without departing from the novel teachings and advantages of the invention. Accordingly, all such modifications are intended to be included within the scope of the inventive concepts as defined in the appended claims. Therefore, the present invention is to be understood as being limited to the specific illustrative embodiments of the invention and the invention Within the scope of the patent application.

10. . . Semiconductor substrate

10'. . . Semiconductor substrate

11. . . P area

13. . . P-zone

15. . . P+ area

30. . . Readout circuit

51. . . lens

53. . . lens

60. . . object

80. . . Pixel group

100. . . Unit pixel

100a. . . Unit pixel

100b. . . Unit pixel

101. . . Semiconductor substrate

101'. . . Semiconductor substrate

110. . . Floating diffusion zone

120. . . Collecting gate

130. . . Discharge gate

140. . . Bungee area

140i. . . Inner edge

140o. . . Outer edge

150. . . Photocharge storage area

200. . . Unit pixel

200a. . . Unit pixel

200b. . . Unit pixel

201. . . Semiconductor substrate

201'. . . Semiconductor substrate

210. . . Floating diffusion zone

220. . . Collecting gate

230. . . Discharge gate

240. . . Bungee area

250. . . Photocharge storage area

270. . . Fixed layer

300. . . Unit pixel

300a. . . Unit pixel

300b. . . Unit pixel

310. . . Floating diffusion zone

320. . . Collecting gate

330. . . Discharge gate

340. . . Bungee area

350. . . Photocharge storage area

370. . . Light gate

410. . . Pixel array

412. . . Unit pixel

415. . . square

417. . . Bungee area

420. . . Pixel array

425. . . triangle

430. . . Pixel array

432. . . Unit pixel

440. . . Pixel array

442. . . Unit pixel

450. . . Pixel array

451. . . Pixel group

452. . . Unit pixel

453. . . Electrical connection

600. . . Light detecting device

610. . . Control sensing unit

610a. . . Sensing unit

630. . . control unit

800. . . camera

810. . . Light receiving lens

820. . . 3D image sensor chip

830. . . Light source module

840. . . Engine unit

850. . . Host/application

900. . . 3D image sensor

1000. . . Computing system

1010. . . processor

1020. . . Memory device

1030. . . Storage device

1040. . . Input/output device

1050. . . Power Supplier

1100. . . Computing system

1110. . . Application processor

1111. . . DSI host

1112. . . CSI host

1113. . . Physical layer

1114. . . DigRF master control unit

1120. . . Global Positioning System

1140. . . 3D image sensor

1141. . . CSI device

1150. . . Display device

1151. . . DSI device

1160. . . RF chip

1161. . . Physical layer

1170. . . Storage

1180. . . MIC

1185. . . DRAM device

1190. . . speaker

1210. . . Ultra-wideband

1220. . . Wireless local area network

1230. . . Microwave access global interoperability

S110~S130, S210~S250. . . step

ADC. . . Analog digital conversion unit

BN. . . Binary signal generator

CADC. . . Color pixel converter

CCOL. . . Color pixel selection circuit

CDATA. . . Image information

CG. . . Collecting gate signals

CG1-CGk, CG1’-CG4’, CGi. . . Binary signal

CLK. . . Clock signal

COL. . . Selection circuit

CROW. . . Color pixel selection circuit

CTRL. . . Controller

C/ZPX. . . Pixel array

DATA. . . electric signal

DATA1. . . data

DATA2. . . data

DR. . . Buckling voltage

DRG. . . Discharge gate signal

DRGi. . . Inverted binary signal

EL. . . Emitted light

FD. . . Floating diffusion voltage

LO. . . Output line

LS. . . light source

MCLK. . . Main clock

PX. . . Pixel array

RDC. . . Unit pixels are not in the area

RL. . . The light received

ROW‧‧‧Selection circuit

RST‧‧‧Reset signal

R, G, B, Z‧‧‧ unit pixels

SEL‧‧‧Selection signal

T1‧‧‧ source follower transistor

T1-Tk‧‧‧ phase difference

T2‧‧‧Selective crystal

T3‧‧‧Reset the transistor

Tc‧‧‧ second time

Phase difference between the emitted light EL of Tf‧‧‧ and the received light RL

The phase difference of Ti‧‧‧ relative to the emitted light EL

To‧‧ cycle

Tr‧‧‧First time

TR‧‧‧Reading time

TS‧‧‧Sensing time

TS1-TSk‧‧‧Sensing time

VB‧‧‧predetermined bias voltage

VC‧‧‧ vertical center axis

VRST‧‧‧Reset voltage

W1, W2, Wi‧‧‧ start duration

Z‧‧‧ distance

ZADC‧‧‧Deep Pixel Converter

ZCOL‧‧‧Deep pixel selection circuit

ZDATA‧‧‧In-depth information

ZROW‧‧‧Deep pixel selection circuit

1 illustrates a layout of an exemplary embodiment of a unit pixel of a light detecting device.

2 illustrates a plan view of an exemplary embodiment of a unit pixel of a light detecting device.

3 and 4 illustrate cross-sectional views of an exemplary embodiment of the unit pixel of Fig. 2.

5 and 6 illustrate cross-sectional views for describing an example of horizontal movement of photocharges in the unit pixels of Figs. 3 and 4.

Figure 7 illustrates a plan view of another exemplary embodiment of a unit pixel of a light detecting device.

8 and 9 illustrate cross-sectional views of an exemplary embodiment of the unit pixel of Fig. 7.

Figure 10 illustrates a plan view of another exemplary embodiment of a unit pixel of a light detecting device.

11 and 12 illustrate cross-sectional views of an exemplary embodiment of the unit pixel of Fig. 10.

13 through 17 illustrate diagrams of an illustrative embodiment of a pixel array.

Figure 18 illustrates a schematic diagram of an illustrative embodiment of a readout circuit for providing an output of a unit pixel.

Figure 19 illustrates a block diagram of an exemplary embodiment of a light detecting device.

Figure 20 illustrates a flow chart of an illustrative embodiment of a method of measuring distance.

21 illustrates an exemplary timing diagram of an exemplary signal that can be used to convert received light into an electrical signal.

22 and 23 illustrate an exemplary timing diagram of an example of a variable binary signal that can be used by the method of measuring distance illustrated in FIG.

Figure 24 illustrates a diagram of an exemplary variable binary signal.

Figure 25 illustrates a graph of an exemplary phase of the variable binary signal illustrated in Figure 24, the length of the start-up duration, and the number of cycles.

Figure 26 illustrates a flow chart of an illustrative embodiment of a method of measuring distance.

Figure 27 illustrates a diagram of an exemplary variable binary signal.

Figure 28 illustrates a diagram of an exemplary phase of the variable binary signal illustrated in Figure 27, the length of the start-up duration, and the number of cycles.

Figure 29 illustrates a diagram of an exemplary adjusted binary signal.

Figure 30 illustrates a diagram of an illustrative embodiment of a sensing unit of a three-dimensional image sensor.

31 illustrates a diagram of an illustrative embodiment of a pixel array that can be used in the sensing unit of FIG.

Figure 32 illustrates a block diagram of an illustrative embodiment of a camera including a three dimensional image sensor.

Figure 33 illustrates a block diagram of an illustrative embodiment of a computing system including a three-dimensional image sensor.

FIG. 34 illustrates a block diagram of an exemplary embodiment of an interface that may be used in the computing system of FIG.

Claims (10)

A unit pixel included in a photodetecting device, the unit pixel comprising: a floating diffusion region in a semiconductor substrate; an annular collecting gate over the semiconductor substrate; and a semiconductor substrate An annular discharge gate; and a drain region in the semiconductor substrate, wherein the annular collector gate and the annular discharge gate are respectively disposed between the floating diffusion region and the drain region, wherein An annular collecting gate surrounds the floating diffusion region, the annular discharge gate surrounds the annular collecting gate, and the drain region surrounds the annular discharge gate. The unit pixel included in the photodetecting device according to claim 1, wherein the floating diffusion region is located at a center, and the annular collecting gate is opposite to the floating diffusion region. The drain region is at the outermost side of the annular discharge gate. The unit pixel included in the photodetecting device according to claim 1, wherein the annular collecting gate and the annular discharging gate have a circular or polygonal annular shape. The unit pixel included in the photodetecting device according to claim 1, wherein an annular collecting gate signal and an annular discharging gate signal are respectively applied to the annular collecting gate and the annular discharging gate. Wherein, when the ring collecting gate signal is activated, photocharges generated in the semiconductor substrate are collected in the floating diffusion region, and wherein the semiconductor is activated when the ring discharge gate signal is activated The photocharge generated in the substrate is discharged into the drain region. The unit pixel included in the photodetecting device according to claim 1, further comprising: ring light in the semiconductor substrate and between the floating diffusion region and the drain region In the charge storage region, the annular photocharge storage region is doped with an impurity of a conductivity type opposite to that of the semiconductor substrate. The unit pixel included in the photodetecting device of claim 5, wherein the annular collecting gate at least partially overlaps an inner portion of the annular photocharge storage region; and wherein the annular discharge The gate at least partially overlaps an outer portion of the annular photocharge storage region. The unit pixel included in the photodetecting device according to claim 5, wherein the annular collecting gate is located between the annular photocharge storage region and the floating diffusion region, and wherein the An annular discharge gate is located between the annular photocharge storage region and the drain region. The unit pixel included in the photodetecting device of claim 7, further comprising: an annular fixed layer in the semiconductor substrate for covering the annular photocharge storage region, the ring The pinned layer is doped with an impurity of a conductivity type opposite that of the annular photocharge storage region. The unit pixel included in the photodetecting device as described in claim 7 of the patent application further includes: An annular optical gate is disposed over the semiconductor substrate and between the annular collecting gate and the annular discharge gate to cover the annular photocharge storage region. The unit pixel included in the photodetecting device according to claim 1, wherein the semiconductor substrate comprises a plurality of photocharge generating regions doped with impurities of the same conductivity type and different concentrations.