TWI544486B - Memory accessing method - Google Patents

Description

Memory access method

The present invention relates to a method of accessing a memory, and more particularly to a method of reducing the word hammer effect of a memory.

Dynamic memory can occur when a particular word line needs to be repeatedly opened many times under certain application conditions. In such a case, the memory cells on the word line adjacent to the word line that is repeatedly turned on many times may mutate the stored data due to cross talk or coupling effects. The above state is referred to as a word hammer effect.

Specifically, please refer to the schematic diagram of the dynamic memory generated word line impact effect illustrated in FIG. 1 . When the word line WLA is turned on multiple times between two adjacent refresh operations, the word lines WLB and WLC adjacent to the word line WLA are generated in the memory cell due to the repeated turn-on action of the word line WLA. The phenomenon of data variability. Among them, the word line WLB and the WLC may be referred to as a victim word line, and the word line WLA may be referred to as an aggressor word line.

In the prior art, the above-mentioned word line impact effect is often solved by an additional refresh operation. This way of re-refreshing in the burst Actions cannot be implemented. In addition, in order to cope with the additional re-refresh operation to be performed, it is usually necessary to change the usage specifications of the dynamic memory, which is liable to cause difficulty in use.

The invention provides a memory device and a memory access method for effectively reducing the influence of word line impact in a dynamic random access memory.

The method for accessing the memory of the present invention comprises: calculating the number of times of access of each word line address; and according to comparing the number of times of access and a number of critical accesses, setting corresponding word line addresses as infringing word line positions Address; and set the alternate word line address, and replace the memory cell that invades the word line address with the memory cell of the alternate word line address.

Based on the above, the present invention determines whether the address of the bit line is an infringing word line address by calculating the number of times the address of the commonly used bit line is accessed. Moreover, when the address of the bit line is determined to be a violation of the word line address, the memory cell that invades the word line address is replaced by the memory cell of the alternate word line address. In this way, the phenomenon of data errors that may occur due to the impact of the word line can be effectively avoided, and the reliability of the data stored in the memory is improved.

The above described features and advantages of the invention will be apparent from the following description.

S210~S230, S510~S590, S5100~S5120‧‧‧ memory access steps

WLA, WLB, WLC, WLBA, WLBB, WLBC‧‧‧ word lines

410, 420‧‧ ‧ sense amplifier

T1~T4‧‧‧ time point

BL, BLB‧‧‧ bit line

Td‧‧‧Delayed time

600‧‧‧ memory device

610‧‧‧ memory controller

620‧‧‧ Dynamic Random Access Memory

622‧‧‧Word Line Decoder

401, 621‧‧‧ memory cell array

FIG. 1 is a schematic diagram of a dynamic memory generating a word line impact effect.

2 is a flow chart showing a method of accessing a memory according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing the replacement action of the alternate word line address and the infringing word line address.

FIG. 4A is a schematic diagram of a data copying operation according to an embodiment of the present invention.

FIG. 4B is a waveform diagram of a data copying operation according to an embodiment of the present invention.

FIG. 4C is a schematic diagram showing the restoration operation of the infringing word line address according to the embodiment of the present invention.

FIG. 5A and FIG. 5B are flowcharts showing a method for accessing a memory according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of a memory device according to an embodiment of the invention.

Please refer to FIG. 2. FIG. 2 is a flow chart of a method for accessing a memory according to an embodiment of the present invention. The present embodiment is a method flow for data access for a dynamic random access memory, and particularly relates to a method for accessing a dynamic random access memory of a DDR4 (double-data-rate 4) standard. In step S210, during the operation of the memory, an operation of calculating the number of times each word line address is accessed is performed. The above-mentioned calculation operation of the number of accesses can be started after the re-fresh action of each word line address is executed, and when each word line address is activated, In the row access action, the value of the number of times the address corresponding to each word line address is accessed may be incremented (eg, by one). In addition, when the next re-refresh operation corresponding to each word line address is performed, the value of the number of times of access corresponding to each word line address can be reset to zero.

In step S220, the number of times of accessing each word line address is compared with the number of critical accesses, and according to the result of the comparison, whether to set each word line address as the infringing word line address is determined. . Carefully, when the number of times each word line address is accessed is greater than the critical access number, the number of times the address of the word line address is accessed is too high, and a word line impact effect may be generated to make adjacent words. The data in the memory cells of the line address is mutated. Therefore, the word line address whose access number is greater than the critical access number can be set as the infringing word line address.

Incidentally, the above-mentioned critical access number is a preset value. Among them, the designer of the memory can set the value of the critical access number according to the actual working state of the memory.

In step S230, the alternate word line address is set, and the alternate word line address is used to replace the infringing word line address, so that the memory cell of the alternate word line address replaces the memory cell that invades the word line address. For the purpose of data access. Here, in the memory, a part of the word line address may be preset as a general word line address, and another part of the word line address may be set as a spare word line address. Also, a word line adjacent to the address set as a spare word line address can be set as an idle word line.

When performing the replacement of the alternate word line address and the infringing word line address, the data stored in the memory cell on the infringing word line address must first be transferred to the alternate word line address. In the memory cell, the alternate word line address is replaced by the substitution action of the infringing word line address.

On the other hand, if the infringing word line address re-refresh action occurs, it indicates that the infringing word line address can be used normally again, and therefore, in addition to resetting the value of the number of times of access corresponding to the infringing word line address. The memory cell that invades the word line address can also be replaced by the memory cell that invades the word line address so that the memory cell that invades the word line address can continue to be used.

In other words, after the re-refresh operation of the infringing word line address, the data in the memory cell of the spare word line address may be copied to the infringing word line address, and the logical bit mapped to the spare word line address may be mapped. The address is mapped to the infringing word line address, thereby restoring the infringing word line address to a normal word line address.

Please refer to FIG. 3 for a schematic diagram of the replacement action of the alternate word line address and the infringing word line address. In FIG. 3, word lines WLA, WLB, and WLC are all normal word lines, and word lines WLBA, WLBB, and WLBC are set as spare word lines. When the number of times the word line address of the word line WLA is repeated is greater than the critical access number, the word line address of the word line WLA is set to the infringing word line address, and the word line address of the word line WLB and the WLC Then it is the infringed word line address. In order to prevent the word line WLB and the data on the memory cell of the WLC from being affected by the repeated opening of the word line WLA, the word line address of the spare word line WLBA can be set as the spare word line address, and the word of the spare word line WLBA is made. The line address replaces the word line address of the word line WLA. It is worth noting that the spare word lines WLBB and WLBC adjacent to the spare word line WLBA are all idle. That is to say, the memory cells of the alternate word line WLBB and the word line address of WLBC are not used to store data.

In the portion where the word line address of the spare word line WLBA is substituted for the word line address of the word line WLA, first, the data stored in the memory cell of the word line WLA must first be transferred to the memory cell of the spare word line WLBA. Next, the logical address LA of the word line address originally mapped to the word line WLA is mapped to the word line address of the spare word line WLBA. In other words, when there is a need to perform an access operation on the logical address LA, the word line address actually provided for access is the word line address of the spare word line WLBA.

Incidentally, after the replacement operation of the word line WLA and the spare word line WLBA described above is completed, the word line WLA set to be invaded by the word line address can be set to be in an idle state.

For the part of the memory cell that copies the data of the infringing word line address memory cell to the alternate word line address, please refer to the schematic diagram of the data copying operation of the embodiment of the present invention illustrated in FIG. 4A, and the present invention illustrated in FIG. 4B. The data copy action waveform of the embodiment. The memory cell array 401 formed by a plurality of memory cells is coupled to the sense amplifiers 410 and 420 through a bit line group formed by the bit lines BL and BLB. When the action of copying the data in the memory cell set to the word line address of the word line WLA of the word line to the memory cell of the word line address of the spare word line WLBA is performed, at the time point T1, the word line WLA can be It is activated according to the received violation word line signal. Corresponding to this, the voltages of the bit lines BL and BLB start to differ after the time point T1. Also, at a time point T2 after a delay time Td of the time point T1, the voltage variations of the bit lines BL and BLB tend to be stable, and the spare word line WLBA can be activated in accordance with the received spare word line signal.

After the alternate word line WLBA is turned on, the memory of the word line WLA The data can be transmitted to the sense amplifier 420 through the bit lines BL and BLB, and the data of the memory cells of the word line WLA is written into the memory cells of the spare word line WLBA through the action of the sense amplifier 420.

Incidentally, in the initial stage of the standby word line WLBA being activated, the voltages on the bit lines BL and BLB may be slightly disturbed due to the activated operation of the spare word line WLBA, however, the degree of these micro perturbations does not occur. The action of causing data to be written to the memory cell of the alternate word line WLBA produces an error.

Incidentally, regarding the restoration action of the infringing word line address. After a new re-refresh action is performed on the infringing word line address, an action of replacing the infringing word line address with the alternate word line address may be performed, thereby restoring the infringing word line address to a normal line address. When performing the restoration operation of the infringing word line address, please refer to FIG. 4C for a schematic diagram of the restoration operation of the infringing word line address according to the embodiment of the present invention. The first word line WLBA is turned on at the time point T3 through the spare word line signal, and the word line WLA is turned on at a time point T4 after a delay time Td at the time point T3. As a result, the data in the memory cells of the spare word line WLBA can be copied into the memory cells of the word line WLA through the voltages of the bit lines BL and BLB and the actions of the sense amplifiers 410 and 420. Then, by mapping the corresponding relationship between the alternate word line WLBA and the word line address of the word line WLA, the restoration operation of the infringing word line address can be completed.

Referring to FIG. 5A and FIG. 5B, FIG. 5A and FIG. 5B are flowcharts showing a method for accessing a memory according to another embodiment of the present invention. Referring to FIG. 5A first, in step S510, the number of times of access of each word line is counted, and the number of times of access of each word line corresponding to the statistics is recorded. Among them, the number of times each word line is accessed can be used Store devices (such as static memory) for storage. In step S520, it is determined whether or not there is a case where the number of accesses of the word line is greater than the critical access number. When the number of times the word line is accessed is greater than the critical access number, the general operation of step S530 can be performed. In contrast, if the number of times the word line is accessed is greater than the critical access number, step S540 is executed to set the word line address whose access number is greater than the critical access number as the infringing word line address.

Next, in step S550, the data in the memory cell that invades the word line address is copied into the memory cell of the selected alternate word line address. Also, it is determined in step S560 whether a new access request has occurred for the infringing word line address. If the result of the determination in step S560 is NO, the general operation of step S570 is performed. If the result of the determination in step S560 is YES, please refer to FIG. 5B.

In FIG. 5B, following the node A of FIG. 5A, when the result of the determination in step S560 is YES, step S580 is performed to replace the memory cell invading the word line address with the memory cell of the alternate word line address, and The memory cell of the alternate word line address provides the new access action determined in step S560. In addition, in step S590, it is continuously determined whether or not the operation of re-refreshing the address line address is violated. If the operation of re-refreshing the word line address is not performed, it is determined that the access to the word line address requires data access. (Step S5100), step S580 is executed to replace the memory cell invading the word line address with the memory cell of the alternate word line address to perform the access operation. In contrast, when S5100 determines that the operation of invading the word line address does not require data access, the general operation of step S5110 is performed.

On the other hand, when it is determined in step S590 that the infringing word line address is re-brushed In the new action, step S5120 is performed to replace the spare word line address with the infringing word line address to restore the infringing word line address to a general word line address.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a memory device according to an embodiment of the invention. The memory device 600 includes a memory controller 610, a word line decoder 622, and a dynamic random access memory 620. The dynamic random access memory 620 includes a memory cell array 621 composed of memory cells, a plurality of word lines WLA, and a plurality of spare word lines WLBA. The memory controller 610 is coupled to the word line WLA and the spare word line WLBA. The memory controller 610 calculates the number of accesses of the word line address of each word line WLA, and sets the corresponding word line address of each word line as the infringing word line position according to the compared number of times of access and the number of critical accesses. site. In addition, the memory controller 610 sets the alternate word line address and replaces the memory cell that invades the word line address with the memory cell of the alternate word line address.

The memory controller 610 can generate a word line signal through the word line decoder 622 to turn on or off the word line WLA and the spare word line WLBA.

The details of the operation of the memory controller 610 are described in detail in the foregoing embodiments and embodiments, and will not be further described below.

In summary, the present invention determines whether the corresponding word line address is an infringing word line address by detecting the number of times the word line is accessed, and replaces the infringing word line address by the alternate word line address to execute the data. Access action. Thereby, the number of accesses of any word line address can be effectively controlled so that the word line impact effect does not occur. In this way, the data stored in the memory can be correctly saved and the reliability of the data can be improved.

S210~S230‧‧‧ memory access step

Claims (6)

A memory access method, the memory having a plurality of word line addresses, comprising: calculating an accessed number of each of the word line addresses; setting the number of accessed times and a critical access number to compare Corresponding each of the word line addresses is an infringing word line address; and setting a spare word line address, and using the memory cell of the spare word line address to replace the memory cell of the infringing word line address, wherein setting The alternate word line address, and replacing the memory cell of the infringing word line address with the memory cell of the spare word line address includes: copying the data of the memory cell of the infringing word line address to the spare word line a memory cell of the address; mapping the alternate word line address to a logical address of the infringing word line address mapping; and setting the invasive word line address to an idle state, wherein the memory cell of the infringing word line address is copied The data to the memory cell of the spare word line address includes: opening a memory cell of the infringing word line address through a word line signal; and a delay time when the memory cell of the infringing word line address is turned on After passing through a spare word line signal Open the spare memory cell word line address, wherein the word line address against the memory cell in the data in the spare When the memory cell of the word line address is turned on, it is transmitted to the memory cell of the spare word line signal through a plurality of bit line groups. The method for accessing a memory according to claim 1, wherein the step of calculating the number of accesses of each of the word line addresses comprises: incrementing each of the word lines when an access event occurs The number of times the word line address was accessed. The method for accessing a memory according to the first aspect of the invention, wherein the step of comparing the accessed times with the number of critical accesses to set the corresponding word line address is the step of the infringing word line address. The method includes: comparing the accessed times with the critical access number; and when the accessed number is greater than the critical access number, setting the corresponding word line address to the infringing word line address. The method for accessing the memory according to claim 1, further comprising: replacing the spare word line with the memory cell of the invading word line address after the one refresh operation of the infringing word line address is performed The memory of the address. The method for accessing a memory according to claim 4, wherein the step of replacing the memory cell of the spare word line address by the memory cell of the infringing word line address comprises: copying the spare word line address And storing the data of the memory cell to the memory cell of the infringing word line address; mapping the infringing word line address to a logical address of the alternate word line address mapping; And setting the alternate word line address to be idle. The method for accessing a memory according to claim 5, wherein the step of copying the data of the memory cell of the spare word line address to the memory cell of the infringing word line address comprises: transmitting a spare word line signal To turn on the memory cell; and after a delay time when the memory cell of the spare word line address is turned on, a word line signal is used to turn on the memory cell of the infringing word line address, wherein the spare word line bit The data in the memory cell of the address is transmitted to the memory cell of the invading word line address through a plurality of bit line groups in the case where the memory cell is turned on.