TWI543678B - Circuit layout structure and layout method thereof - Google Patents

Description

Circuit layout structure and its layout method

The present invention relates to a circuit layout structure and a layout method thereof, and more particularly to a circuit layout structure of a circuit board having a ceramic capacitor and a layout method thereof.

Multi-layer Ceramic Capacitor (MLCC) is a kind of ceramic capacitor. Due to the advancement of ceramic film stacking technology, the capacitance value is getting higher and higher, and gradually replaces medium and low capacitance, such as electrolytic capacitor and tantalum capacitor. In addition to the market application, MLCC can be directly attached to the circuit board through SMT, making production processing faster. With the miniaturization of electronic products, MLCC is easy to wafer and has a small size, and has gradually become the mainstream product of the capacitor industry.

Generally, the dielectric material of a high-capacity multilayer ceramic capacitor is composed of ferroelectric material, which causes structural distortion of the ceramic body after an applied electric field. This phenomenon is a piezoelectric effect (Piezoelectric Effect). The resulting Electrostrictive Effect causes it to resonate with Acoustic emission or Noise. When the ceramic capacitor is attached to the printed circuit board (PCB), the mechanical energy generated by the ceramic capacitor is transmitted to the circuit board through the solder joint. At this time, the circuit board is sharpened like the same speaker. Noise, sometimes too much vibration will also cause damage to the internal structure of the component.

Therefore, in order to reduce this noise, the manufacturer has developed a symmetrical manner for the surface and the back of the board, or installed in a spaced manner. The structure of a pair of ceramic capacitors mutually suppresses the resonance generated by the ceramic capacitor on the circuit board, thereby achieving the effect of reducing noise.

However, the above-mentioned conventional ceramic capacitor mounting structure can indeed reduce the noise decibel, but the ceramic capacitors must be separately mounted on the surface and the back surface of the circuit board in a symmetrical manner, or spaced apart from each other. Therefore, the design freedom of the circuit board on which the ceramic capacitor is mounted is greatly limited, which causes difficulty in circuit layout design, and at the same time, it needs to be achieved with a large circuit board, which leads to an increase in production cost. Another manufacturer chooses a ceramic capacitor with a high-pad design to avoid the resonance with the circuit board and reduce the noise. However, the unit price of the ceramic capacitor is too high and is limited by height. Set on a board with a height limit. Therefore, how to make the ceramic capacitor reduce its noise in the working environment, and does not cause inconvenience in circuit design, and at the same time, the need to reduce the cost is a problem that the creators of this technical field want to solve.

In view of the above problems, the present invention provides a circuit layout structure and a layout method thereof, thereby solving the problem that a conventional ceramic capacitor easily resonates with a circuit board to generate a sharp noise.

The present invention provides a circuit layout structure including a circuit board and at least one piezoelectric element, wherein the circuit board includes a substrate, a copper foil layer and a solder resist layer, the copper foil layer is laminated on the substrate, and the solder resist layer The copper foil layer is covered so that the copper foil layer is sandwiched between the substrate and the solder resist layer, and the circuit board has a recessed portion to remove the copper foil layer and the solder resist layer. The piezoelectric element is electrically disposed on a surface of the circuit board, and the position of the piezoelectric element corresponds to the recessed area, so that there is a gap between the piezoelectric element and the recessed area of the circuit board.

The present invention also provides a method for laying out a circuit structure, comprising the steps of: providing a circuit board, the circuit board comprising a substrate, a copper foil layer and a solder mask layer, the copper foil layer being sandwiched on the substrate and the protection Between the solder layers; removing the copper foil layer and the solder resist layer to form a recessed region on the circuit board a surface; an at least one piezoelectric element is electrically disposed on the surface of the circuit board, and the piezoelectric element corresponds to the recessed area, so that a gap exists between the piezoelectric element and the recessed area of the circuit board.

The effect of the invention lies in that the circuit layout structure and the layout method thereof not only utilize the structural design of the circuit board having the recessed area, but also the vibration amplitude of the circuit board is not expanded, thereby achieving the effect of reducing noise. At the same time, the gap between the piezoelectric element and the recessed region can also provide a space for the deformation of the piezoelectric element, so that the piezoelectric element does not rub against the circuit board due to shape deformation, and can prevent sharp noise caused by friction, and Avoid damage to the piezoelectric components.

The features, implementations, and utilities of the present invention are described in detail below with reference to the drawings.

10‧‧‧Circuit layout structure

100‧‧‧ boards

110‧‧‧Substrate

120‧‧‧copper layer

130‧‧‧ solder mask

140‧‧‧ recessed area

150‧‧‧ surface

200‧‧‧Piezoelectric components

210‧‧‧ solder pads

G‧‧‧ gap

1 is a cross-sectional view showing a circuit board of a circuit layout structure according to an embodiment of the present invention.

Fig. 2 is a schematic view showing the copper foil layer and the solder resist layer of the circuit board of the circuit layout structure according to an embodiment of the present invention.

Fig. 3 is an exploded perspective view showing a circuit board and a piezoelectric element of a circuit layout structure according to an embodiment of the present invention.

Fig. 4 is a schematic diagram showing the combination of piezoelectric elements of a circuit layout structure according to an embodiment of the present invention.

FIG. 5 is a flow chart showing the steps of a circuit structure layout method according to an embodiment of the present invention.

The circuit layout structure 10 of the embodiment of the present invention is described as an embodiment of the circuit board structure of the circuit board 100 of the display card, but is not limited to the type disclosed in the embodiment. The technician can change the number and layout position of the piezoelectric elements of the circuit layout structure 10 of the present invention according to actual design requirements or usage requirements.

Chen Qianming, the circuit board 100 described in this embodiment is similar to the basic composition of the conventional printed circuit board, and can also be used as a carrier for electronic components, and provides a function of connecting the components of the electronic components, so the applicant does not elaborate here, only The electronic components and structures involved in the present embodiment will be described in detail.

Please refer to the disassembled schematic diagram and the combined schematic diagram of the circuit layout structure disclosed in an embodiment of the present invention shown in FIG. 1 to FIG. 4, and the step flow chart of the circuit structure layout method shown in FIG. 5. The circuit layout structure 10 of the present embodiment includes a circuit board 100 and at least one piezoelectric element 200. The circuit board 100 includes a substrate 110, a copper foil layer 120 and a solder resist layer 130. The copper foil layer 120 is laminated on the substrate. 110, the solder resist layer 130 covers the copper foil layer 120, and the copper foil layer 120 is interposed between the substrate 110 and the solder resist layer 130, as in step S101.

The material of the substrate 110 may be made of materials such as electric wood board (FR-1), glass fiber board (FR-4), and various plastic plates (Plastic), but is not limited thereto. The copper foil layer 120 is a circuit layer, and the material thereof may be a material such as electrolytic copper or rolled copper, and can function as a conduction circuit and a ground. The solder resist layer 130 is a solder mask layer, and the material thereof may be an epoxy resin, a polyimide (PI), or a polyphenylene oxide (PPE). material.

The piezoelectric element 200 of the present embodiment is a ceramic capacitor such as a multilayer ceramic capacitor (MLCC) or a single-layer type ceramic capacitor, but is not limited to the type disclosed in the present invention. The outer shape of the piezoelectric element 200 is a rectangular parallelepiped, and the piezoelectric element 200 has two solder pads 210 respectively wrapped on the left and right ends of the piezoelectric element 200 to be electrically connected to the circuit board 100.

Further, the detailed structure and layout method of the circuit layout structure 10 of the present embodiment: as shown in FIG. 2, the circuit board 100 of the present embodiment further has a recessed area 140. Step S102 shown in FIG. 5, the circuit is A portion of the copper foil layer 120 and the solder resist layer 130 of the board 100 are removed, thereby forming a recessed region 140 on one surface 150 of the circuit board 100, wherein the recessed region 140 forms a contoured shape and the piezoelectric element 200 The shape of the bottom surface corresponds. The above step S102 only needs to adjust the layout range of the copper foil layer 120 and the solder resist layer 130 during the circuit layout (LAYOUT), and the layout range thereof can be avoided by the region where the piezoelectric element 200 is disposed at a lower position. Processing, therefore, does not add any cost and does not affect the function of the circuit board 100.

The step S103 is shown in FIG. 5, and then the piezoelectric element 200 is electrically disposed on the surface 150 of the circuit board 100. As shown in FIG. 4, the piezoelectric element 200 of the embodiment is two. The solder pad 210 is electrically connected to the surface 150 of the circuit board 100 and electrically connected to the circuit board 100, and the bottom surface of the piezoelectric element 200 corresponds to the position of the recessed area 140, and the bottom surface of the piezoelectric element 200 and the circuit board A gap G exists between the recessed regions 140 of 100 such that the bottom surface of the piezoelectric element 200 and the circuit board 100 can be spaced apart and maintained at a distance.

It should be noted that the piezoelectric element 200 disclosed in the present invention may be provided in a number of one, two or more. The person skilled in the art may change the piezoelectric element 200 of the present invention according to actual needs. The number of configurations. Moreover, the above-mentioned piezoelectric element 200 and the circuit board 100 can be combined by solder paste or directly by surface adhesion technology (SMT).

Based on the above structure, the piezoelectric element 200 of the present embodiment is itself a material of a ceramic structure. When an applied electric field forms a high-frequency working environment, the piezoelectric element 200 itself is deformed by the electrostrictive effect and mechanically generated. The vibration is transmitted to the circuit board 100 by the electrically connected two pads 210. At this time, due to the gap G formed by the corresponding recessed region 140 under the piezoelectric element 200, the resonance of the circuit board 100 due to the piezoelectric element 200 can be effectively suppressed, so that the vibration amplitude of the circuit board 100 is not enlarged, thereby achieving Reduce the effectiveness of noise. At the same time, the gap G can also provide a space for the deformation of the piezoelectric element 200, so that the piezoelectric element 200 is not deformed by the shape. Rubbing to the circuit board 100 prevents sharp noise due to friction and prevents damage of the piezoelectric element 200.

In addition, in application, when the circuit layout structure 10 of the present invention is simultaneously disposed on the circuit board 100 with a plurality of piezoelectric elements 200, since the circuit board 100 has a structural design of the recessed regions 140, in addition to enabling the respective piezoelectric elements 200 The overall height of the piezoelectric element 200 does not increase even if it is connected and adjacent to each other, so that the size of the circuit board 100 can be greatly reduced, and the circuit layout structure 10 can meet the requirements of highly limited electronic products, thereby improving The applicability of the circuit layout structure 10.

The following table shows the experimental data of the ceramic capacitor (MLCC), which is the value measured by the ceramic capacitor on the model GV-N660OC-2GD display card (the fan noise value has been excluded).

It can be clearly seen from the above data verification that the circuit layout structure of the present invention is the display card of the above numbers D1 and D2, and the ceramic capacitor can effectively reduce the noise during actual operation, and the actual measured value. At 17dB, the ratio of the noise reduction value is reduced by about 10% compared with the conventional display card numbers A1 and A2. Therefore, it is sufficient to prove that the circuit layout structure of the present invention can significantly reduce the ceramic capacitor due to mechanical vibration. High frequency noise generated.

It can be clearly seen from the above description of the embodiment of the present invention and the data verification that the circuit layout structure of the present invention is removed by removing electricity. The technical means of the copper foil layer and the solder resist layer in the range of the road plate can not only solve the problem that the conventional ceramic capacitor easily resonates with the circuit board and emits a sharp noise.

Compared with the prior art, the circuit layout structure of the present invention also utilizes a design in which a plurality of piezoelectric elements are simultaneously connected and disposed adjacent to the circuit board, which not only greatly reduces the size of the circuit board, but also the overall height of the piezoelectric element. It will not increase, so that the circuit layout structure can meet the requirements of highly restricted electronic products, thereby improving the applicability of the circuit layout structure.

Although the embodiments of the present invention are disclosed above, it is not intended to limit the present invention, and those skilled in the art, regardless of the spirit and scope of the present invention, the shapes, structures, and features described in the scope of the present application. And the number of modifications may be made, and the scope of patent protection of the present invention shall be determined by the scope of the patent application attached to the specification.

10‧‧‧Circuit layout structure

100‧‧‧ boards

110‧‧‧Substrate

120‧‧‧copper layer

130‧‧‧ solder mask

140‧‧‧ recessed area

150‧‧‧ surface

200‧‧‧Piezoelectric components

210‧‧‧ solder pads

G‧‧‧ gap

Claims (5)

A circuit layout structure comprising: a circuit board comprising a substrate, a copper foil layer and a solder mask layer, the copper foil layer being sandwiched between the substrate and the solder resist layer, the circuit board further having a recessed area The recessed area removes the copper foil layer and the solder resist layer; and at least one piezoelectric element is electrically disposed on a surface of the circuit board, and the position of the piezoelectric element corresponds to the recessed area, There is a gap between the piezoelectric element and the recessed region of the circuit board, wherein the recessed region forms a contour corresponding to the shape of the bottom surface of the piezoelectric element. The circuit layout structure of claim 1, wherein the piezoelectric element has two pads, and the piezoelectric element is electrically connected to the surface of the circuit board by the two pads. The circuit layout structure of claim 1, wherein the piezoelectric element is a multilayer ceramic capacitor (MLCC) or a single layer type ceramic capacitor. A method for laying out a circuit structure, comprising the steps of: providing a circuit board, the circuit board comprising a substrate, a copper foil layer and a solder resist layer, the copper foil layer being sandwiched between the substrate and the solder resist layer Removing the copper foil layer and the solder resist layer to form a recessed surface on one surface of the circuit board; and electrically providing at least one piezoelectric element on the surface of the circuit board, and the piezoelectric element corresponds to In the recessed region, there is a gap between the piezoelectric element and the recessed region of the circuit board, wherein the recessed region forms a contour corresponding to the shape of the bottom surface of the piezoelectric element. The layout method of the circuit structure as described in claim 4, wherein the electrical setting The step of the piezoelectric element on the surface of the circuit board is electrically connected to the surface of the circuit board by a solder pad disposed on the piezoelectric element.