TWI543527B - Power on reset circuit - Google Patents

Description

Power-on reset circuit

The present invention relates to a power-on reset circuit, and more particularly to an electrical reset circuit having a lower quiescent current.

In a large-scale digital integrated circuit, a register and a logic circuit are disposed in the digital integrated circuit as a common functional unit. In order to avoid the logic function of the integrated circuit and the logic circuit due to the initial state uncertainty, it is usually necessary to set the power-on reset circuit to ensure that the functional units are accurately in the initial reset state, so that the digital integrated circuit works. Normal logic state.

The power-on reset circuit usually uses a resistor-capacitor (RC) reset circuit to generate a reset signal. However, the reset signal outputted by the RC reset circuit often contains more noise, thereby increasing the failure of the aforementioned functional components to be restored. The probability of reaching the initial reset state results in a lower operational reliability of the digital integrated circuit.

In view of this, it is necessary to provide a power-on reset circuit with less noise and noise.

A power-on reset circuit is configured to output a reset signal, including an input end, a charge and discharge circuit, a shaping circuit and an output end, for receiving the power signal, the power source is received from the beginning of receiving the power signal, and the input terminal is configured to receive the power signal, the power source The charging circuit charges the charging and discharging circuit, and the charging circuit outputs a first control voltage. The shaping circuit is configured to obtain a reset signal according to the first control signal, and the reset signal is outputted from the output signal. End output. The charging and discharging circuit includes a charging circuit and a discharging circuit, wherein the charging circuit is configured to perform charging according to the power signal, and the discharging circuit discharges the charging circuit during charging of the charging circuit to slow down the charging speed of the discharging circuit. The noise signal of the first control voltage and the reset signal is reduced.

Compared with the prior art, the discharge circuit increases the discharge speed during the reset process, thereby effectively ensuring noise-free noise in the reset signal, and ensuring that the integrated circuit receiving the reset signal can be accurately reset.

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10, 30‧‧‧ Power-on reset circuit

20‧‧‧ integrated circuit

101, 301‧‧‧ input

102, 302‧‧‧ output

110‧‧‧reference voltage generating circuit

R1‧‧‧first resistance

MP1‧‧‧First P-type transistor

MP2‧‧‧Second P-type transistor

MP3‧‧‧ Third P-type transistor

MP4‧‧‧4th P-type transistor

MP5‧‧‧ Fifth P-type transistor

MN1‧‧‧First N-type transistor

MN2‧‧‧Second N-type transistor

MN3‧‧‧ Third N-type transistor

MN4‧‧‧4th N-type transistor

MN5‧‧‧ fifth N-type transistor

R2‧‧‧second resistance

111‧‧‧reference voltage output

130, 330‧‧‧Charge and discharge circuit

131,331‧‧‧Switch circuit

132, 332‧‧‧Charging circuit

133, 333‧‧‧ discharge circuit

134, 334‧‧‧ first control voltage output

R3‧‧‧ third resistor

R4‧‧‧fourth resistor

R5‧‧‧ fifth resistor

150‧‧‧Control circuit

151‧‧‧second control voltage output

170‧‧‧Shaping circuit

INV1‧‧‧First Inverter

INV2‧‧‧Second inverter

INV3‧‧‧ third inverter

171‧‧‧Low-voltage detection terminal

351‧‧‧ input of the third inverter

352‧‧‧Output of the third inverter

A, B, C, D‧‧‧ nodes

1 is a block diagram of a circuit of a power-on reset circuit in accordance with a preferred embodiment of the present invention.

FIG. 2 is a specific circuit diagram of the power-on reset circuit shown in FIG. 1 according to an embodiment of the present invention.

Figure 3 is a voltage waveform diagram of a corresponding node in the power-on reset circuit as shown in Figure 2.

4 is a circuit block diagram of a power-on reset circuit in a modified embodiment of the present invention.

FIG. 5 is a specific circuit diagram of the power-on reset circuit shown in FIG. 4 according to an embodiment of the present invention.

Figure 6 is a voltage waveform diagram of a corresponding node in the power-on reset circuit as shown in Figure 5.

The specific circuit structure of the power-on reset circuit of the present invention will be specifically described below with reference to the accompanying drawings.

Please refer to FIG. 1, which is a circuit block diagram of a power-on reset circuit 10 (POWER ON RESET, POR) according to a preferred embodiment of the present invention. The power-on reset circuit 10 is used for other integrated circuits 20, especially The large-scale digital integrated circuit provides a reset signal Rs to ensure that all the memory cells (not shown) and the logic cells are reliably initialized after the integrated circuit 20 is powered up, so that after the integrated circuit is powered on normally, quasi- Work reliably. In this embodiment, the integrated circuit is in a reset state when the reset signal Rs is at a low potential, and is in a normal operation state when the reset signal Rs is at a high potential.

In addition, it should be noted that the "power-on" described in this specification means that the integrated circuit 20 starts receiving the power signal VDD. Of course, the power-on reset circuit 10 can also be integrated in the integrated circuit 20.

The power-on reset circuit 10 includes a reference voltage generating circuit 110, a charge and discharge circuit 130, a control circuit 150, and a shaping circuit 170. The reference voltage generating circuit 110 is electrically connected to the input terminal 101 and the charging and discharging circuit 130 for receiving the power signal VDD from the input terminal 101, and outputting the reference voltage Vr to the charging and discharging circuit 130 according to the power signal VDD. The charging and discharging circuit 130 is electrically connected to the control circuit 150, charges or discharges according to the reference voltage Vr, and outputs a first control voltage V1 to the control circuit 150. The control circuit 150 is electrically connected to the reference voltage generating circuit 110, the charging and discharging circuit 130, and the shaping circuit 170. The control circuit 150 selectively outputs the power signal VDD and the second control voltage V2 under the control of the reference voltage Vr and the first control voltage V1. Shaping circuit 170. The shaping circuit 170 is configured to amplify and shape the power signal VDD and the second control voltage V2 to obtain the reset signal Rs, and output the obtained reset signal Rs from the output terminal 102.

Please refer to FIG. 2 , which is a specific circuit structure diagram of the power-on reset circuit 10 shown in FIG. 1 . The reference voltage generating circuit 110 includes a first resistor R1, a first P-type transistor MP1, a first N-type transistor MN1, and a second resistor R2. One end of the first resistor R1 is electrically connected to the input end 101, and the other end is electrically connected to the source of the first P-type transistor MP11. The gate of the first P-type transistor MP1 is directly electrically connected to the drain, and the first P-type transistor MP1 constitutes a diode-connected transistor. The gate of the first N-type transistor MN1 The drain is directly electrically connected, and is electrically connected to the gate and the drain of the first P-type transistor MP1. The source of the first N-type transistor MN1 is electrically connected to the second resistor R2, and the first N-type is electrically connected. The crystal MN1 also constitutes a diode-connected transistor. The second resistor R2 is electrically connected to the first N-type transistor MN1 at one end, and the other end is connected to the ground GND. A node A between the drain of the first P-type transistor MP1 and the drain of the first N-type transistor MN1 serves as a reference voltage output terminal 111 for outputting the reference voltage Vr. In this embodiment, the resistance values of the first resistor R1 and the second resistor R2 are the same, and the on-resistances of the first P-type transistor MP1 and the first N-type transistor MN1 are also substantially the same, whereby the reference voltage Vr is 1 /2VDD.

The first P-type transistor MP1 and the first N-type transistor MN1 are both connected by a diode, so when the voltage applied to the first P-type transistor MP1 and the first N-type transistor MN1 is greater than the turn-on voltage Vth thereof, They are all in a saturated conduction state, thereby exhibiting a relatively constant resistance characteristic.

The charge and discharge circuit 130 includes a switch circuit 131, a charge circuit 132, and a discharge circuit 133. The switch circuit 131 is configured to selectively transmit the power signal VDD to the charging circuit 132 under the control of the reference voltage Vr. The charging circuit 132 is configured to store the charge provided by the power signal VDD for charging. The discharge circuit 133 is used to provide a discharge path for the charging circuit 132 to release the stored charge to delay or slow down the charging time of the charging circuit 132, thereby obtaining a sufficient reset time.

Specifically, the switch circuit 131 includes a second P-type transistor MP2, the gate of the second P-type transistor MP2 is electrically connected to the reference voltage output terminal 111, and the source of the second P-type transistor is electrically connected to the input terminal 101. The drain of the second P-type transistor is electrically connected to the charging circuit 132.

The charging circuit 132 includes a third resistor R3 and a first capacitor C1. The third resistor R3 and the first capacitor C1 are sequentially connected in series from the drain of the second P-type transistor MP2 to the ground GND. its The node B between the third resistor R3 and the first capacitor C1 serves as the first control voltage output terminal 134.

The discharge circuit 133 includes a fourth resistor R4, a fifth resistor R5, a second N-type transistor MN2, and a third N-type transistor MN3.

One end of the fourth resistor R4 is electrically connected to the drain of the second P-type transistor MP2, and the other end is electrically connected to the fifth resistor R5. It can be understood that the resistance value of the fourth resistor R4 can be adjusted according to different power supply voltages.

The fifth resistor R5 is configured to perform hysteresis detection on the power signal VDD, one end is electrically connected to the fourth resistor R4, and the other end is electrically connected to the second N-type transistor MN2. The gate of the second N-type transistor MN2 is electrically connected to the reference voltage output terminal 111, the drain of the second N-type transistor MN2 is electrically connected to the fifth resistor R5, and the source of the second N-type transistor MN2 is electrically connected. Ground GND.

The gate of the third N-type transistor MN3 is electrically connected to the shaping circuit 170. The drain and the source of the third N-type transistor MN3 are electrically connected to the two ends of the fourth resistor R4, respectively. The third N-type transistor MN3 is used as a low-voltage detecting unit for detecting the power signal VDD. When the power signal VDD is detected to be lower than the predetermined value, the discharge speed of the discharge circuit 133 is accelerated, and the first control voltage V1 outputted by the charging circuit 132 is prevented from being unstable due to the repeated increase and decrease of the power signal VDD. The reset circuit 10 can output a reset signal in a timely and reliable manner when the power signal VDD is abnormally powered down.

The control circuit 150 is electrically connected to the reference voltage output terminal 111 and the first control voltage output terminal 134 for selectively outputting the power signal VDD and the second control voltage V2 under the control of the reference voltage Vr and the first control voltage V1.

Specifically, the control circuit 150 includes a third P-type transistor MP3 and a fourth N-type transistor. MN4, the gate of the third P-type transistor MP3 is electrically connected to the reference voltage output terminal 111, the source is electrically connected to the input terminal 111, and the drain is electrically connected to the fourth N-type transistor MN4. The gate of the fourth N-type transistor MN4 is electrically connected to the first control voltage output terminal 134, the drain is electrically connected to the drain of the third P-type transistor MP3, and the source is connected to the ground GND. The node C between the drain of the third P-type transistor MP3 and the drain of the fourth N-type transistor MN4 serves as the second control voltage output terminal 151.

The shaping circuit 170 is electrically connected to the control circuit for shaping the power signal VDD and the second control voltage V2. Specifically, the shaping circuit 170 includes a first inverter INV1, a second inverter INV2 and a third inverter INV3 connected in series, that is, an input end (not labeled) of the first inverter INV1 is electrically connected to the second The control voltage output terminal 151, the output end of the first inverter INV1 is electrically connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is electrically connected to the input end of the third inverter INV3. The output end of the third inverter INV3 is electrically connected to the output terminal 102. The node D between the output end of the second inverter INV2 and the input end of the third inverter INV3 serves as the low voltage detecting end 171, and the low voltage detecting end 171 and the third N-type transistor MN3 are blocked. Extremely electrical connection.

In other embodiments of the present invention, the first inverter INV1 may also be changed to a Schmitt trigger to improve the noise immunity of the reset signal Rs.

Please refer to FIG. 3 , which is a voltage waveform diagram of a corresponding node in the power-on reset circuit 10 shown in FIG. 2 , where VDD represents a waveform diagram of the power signal VDD received by the input terminal 101, and Vr represents a reference outputted by the reference voltage output terminal 111. A waveform diagram of the voltage Vr, V1 represents a waveform diagram of the first control voltage V1 outputted by the first control voltage output terminal 134, Rs represents a waveform diagram of the reset signal Rs outputted by the output terminal 102, and V2 represents a waveform diagram of the second control voltage V2. . The power-on reset circuit 10 and the power-down detection are specifically described with reference to FIG. 2 . work process.

At time t1, the integrated circuit 20 (see FIG. 1) starts to be powered up, and the power signal VDD rises from zero potential (0).

At time t2, when the power signal VDD is greater than 2Vth, where Vth represents the turn-on voltage of the P-type transistor or the N-type transistor, the first P-type transistor MP1 is turned on with the first N-type transistor due to the reference voltage output terminal 111. The output reference voltage Vr is 1/2 VDD, and the reference voltage Vr is Vth at this time.

For the second P-type transistor MP2, the voltage applied to the gate of the control electrode is the reference voltage Vr (Vth), and the source of the transfer electrode is loaded with the power signal VDD (2Vth), thereby, the second P-type When the gate-drain voltage Vgs of the crystal MP2 is Vth, the second P-type transistor MP2 is turned on. The power signal VDD is loaded into the charging circuit 131 by the second P-type transistor, thereby charging the third resistor R3 and the first capacitor C1, and the first control voltage output terminal 134 outputs the first control voltage V1 to rise to zero potential. . Correspondingly, the gate of the fourth N-type transistor MN4 receives the first control voltage V1, whereby the fourth N-type transistor MN4 is in an off state.

For the second N-type transistor MN2, the gate as the control electrode is loaded with the reference voltage Vr, and the source of the transfer electrode is loaded with a zero potential, whereby the gate-drain voltage Vgs of the second N-type transistor MN2 When Vth, the second N-type transistor MN2 is turned on, and the power signal VDD is also released from the discharge circuit 133 to the ground.

For the third P-type transistor MP3, similarly, the working state of the second P-type transistor MP2, the third P-type transistor MP3 is turned on, whereby the power signal VDD is loaded from the third P-type transistor MP3 to The second control voltage output terminal 151, the second control voltage V2 is the same as VDD and changes synchronously. Correspondingly, since the power signal VDD is larger than the inverter Voltage, whereby when the second control voltage V2 is the same as the power signal, the three inverters in the shaping circuit 170 output a reset signal Rs that is opposite in phase (180 degrees difference) from the second control voltage V2, that is, the output is low. The potential is the reset signal Rs, whereby the integrated circuit 20 starts to be in the reset state.

In addition, the low voltage detecting terminal 171 of the shaping circuit 170 outputs the same voltage as the second control voltage V2, that is, equivalent to the power signal VDD, whereby the fourth N-type transistor MN4 is in an on state, and the fourth in the discharging circuit 133 The resistor R4 is directly discharged by the drain-source of the fourth N-type transistor MN4, thereby increasing the discharge speed.

At time t3, when the power signal VDD gradually rises and stabilizes, the first control voltage V1 on the first capacitor C2 in the charging circuit 131 is greater than the turn-on voltage of the third N-type transistor MN3, and the third transistor MN3 is turned on. The second control voltage output terminal 151 is pulled down to a zero potential, and the second control voltage V2 outputs a zero potential. The shaping circuit 170 performs an amplification and shaping process on the second control control voltage V2, and the shaping circuit 170 includes three inverters connected in series, whereby the second shaping circuit outputs a phase opposite to the second control voltage V2. The voltage, that is, the output of a high-potential reset signal, indicates that the integrated circuit 20 is reset. At the same time, the voltage of the low voltage detecting terminal 171 in the shaping circuit 170 is the same as the second control voltage V2, and the third N-type transistor MN3 is turned off, so that the first control voltage V1 can be in a stable state. It can be seen that the time period from the time t1 when the power signal VDD starts to rise to the time t3 after the power signal VDD is in the steady state is the reset time of the integrated circuit 20.

At time t4, during the operation of the power-on reset circuit 10, when the power signal VDD is lowered due to an abnormality, the reference voltage Vr and the first control voltage V1 start to decrease.

At time t5, the first control voltage V1 is smaller than the turn-on voltage of the fourth N-type transistor MN4, The fourth N-type transistor MN4 is turned off, and the second control voltage V2 is equivalent to the power signal VDD, whereby the shaping circuit 170 outputs a low-potential reset signal Rs, and the integrated circuit 20 enters a reset state, thereby protecting the integrated circuit 20 Circuit and work stability.

Compared with the prior art, the first N-type transistor MN1 increases the discharge speed during the reset process, thereby effectively ensuring noise-free noise in the reset signal Rs, and ensuring that the integrated circuit 20 can be accurately reset.

Further, the power-on reset circuit 10 is provided with a low-voltage detecting unit, that is, a third N-type transistor MN3, so that the reset signal Rs is quickly output after the power signal VDD is abnormally powered down, so that the integrated circuit 20 is reset.

Please refer to FIG. 4 , which is a circuit block diagram of a power-on reset circuit 30 according to a modified embodiment of the present invention. The power-on reset circuit 30 includes an input terminal 301 , a charge and discharge circuit 330 , a control circuit 350 , a shaping circuit 370 , and an output terminal 302 . The electrical reset circuit 30 disclosed in the modified embodiment is different from the electrical reset circuit 10 disclosed in the previous embodiment, and the reference voltage generating circuit 110 and the low voltage detecting unit (the third N-type transistor MN3) are not disposed. Other specific differences are detailed in the following.

Specifically, the charging and discharging circuit 330 is electrically connected to the input terminal 301 and the shaping circuit 370 and the control circuit 150, receives the power signal VDD, and is charged or discharged according to the power signal VDD, and correspondingly outputs the first control voltage V1 to the shaping circuit. 370. The shaping circuit 370 is electrically connected to the output terminal 302 for directly amplifying and shaping the first control voltage V1 to obtain the reset signal Rs, and outputting the obtained reset signal Rs from the output terminal 302. The control circuit 150 is electrically connected to the output terminal 302 for outputting the second control voltage V2 to the charging and discharging circuit 310 according to the reset signal Rs to control the charging and discharging circuit 310 to be in a low power consumption state after the power-on reset is completed.

Please refer to FIG. 5, which is a detailed circuit diagram of the power-on reset circuit 30 shown in FIG. The charge and discharge circuit 330 includes a switch circuit 331, a charge circuit 332, a discharge circuit 333, and a hold circuit 335. The switch circuit 331 is configured to transmit the power to the charging circuit 332 according to the power signal VDD. The charging circuit 332 is charged by the power signal VDD. The discharge circuit 333 is used to provide a discharge path to the charging circuit 332 to release the stored charge to delay or slow down the charging time of the charging circuit 332. The hold circuit 335 is for causing the hold charging circuit 331 to be stably maintained in the completed reset state after the power reset on the power-on reset circuit 30 is completed.

Specifically, the switch circuit 331 includes a fourth P-type transistor MP4, and the source of the fourth P-type transistor MP4 is electrically connected to the input terminal 301 for receiving the power signal VDD, and the gate of the fourth P-type transistor MP4 The drain is directly electrically connected, and the charging circuit 332 and the discharging circuit 333 are electrically connected. The fourth P-type transistor MP4 is a diode-connected transistor, so when the voltage applied to the fourth P-type transistor MP4 is greater than its turn-on voltage (Vth), it is in a saturated conduction state, thereby exhibiting a relatively constant state. Resistance characteristics.

The charging circuit 332 includes a third resistor R3 and a first capacitor C1. The third resistor R3 and the first capacitor C1 are sequentially connected in series from the drain of the fourth P-type transistor MP4 to the ground GND. The node B between the third resistor R1 and the first capacitor C1 serves as the first control voltage output terminal 334.

The discharge circuit 333 includes a fourth resistor R4, a fifth resistor R5, and a fifth N-type transistor MN5.

One end of the fourth resistor R5 is electrically connected to the drain of the fourth P-type transistor MP4, and the other end is electrically connected to the fifth resistor R5. It can be understood that the resistance value of the fourth resistor R4 can be adjusted according to different power signal VDD.

The fifth resistor R5 is used for detecting the power signal VDD, and one end is electrically connected to the fourth resistor R4, and the other end is electrically connected to the fifth N-type transistor MN5. The gate of the fifth N-type transistor MN5 is electrically connected to the control circuit 350. The drain of the fifth N-type transistor MN5 is electrically connected to the fifth resistor R5, and the source of the fifth N-type transistor MN5 is electrically connected to the ground. GND.

The holding circuit 335 includes a fifth P-type transistor MP5, wherein the gate of the fifth P-type transistor MP5 is electrically connected to the control circuit 350, and the drain of the fifth P-type transistor MP5 is electrically connected to the fourth P-type The drain of the crystal MP4 is electrically connected to the input terminal 301.

The shaping circuit 370 is electrically connected to the first control voltage output terminal 334 for shaping the first control voltage V1. Specifically, the shaping circuit 370 includes a first inverter INV1 and a second inverter INV2 connected in series, that is, an input end (not labeled) of the first inverter INV1 is electrically connected to the first control voltage output terminal 334, An output terminal of the inverter INV1 is electrically connected to the input end of the second inverter INV2, and an output terminal of the second inverter INV2 is electrically connected to the output terminal 302 for outputting the reset signal Rs.

The control circuit 350 is electrically connected to the output end 302 for outputting the second control voltage V2 according to the reset signal Rs. The control circuit 350 includes a third inverter INV3. The input end 351 of the third inverter INV3 is electrically connected to the output end 302, and the output end 352 of the third inverter INV3 is electrically connected to the gate of the fifth P-type transistor MP5 and the gate of the fifth N-type transistor MN5. The pole is used to output the bottom and control the voltage V2 to control the fifth P-type transistor MP5 and the fifth N-type transistor MN5 to be turned on or off.

Please refer to FIG. 6 , which is a voltage waveform diagram of the output terminal of the corresponding node in the power-on reset circuit 30 shown in FIG. 4-5 , where VDD represents a waveform diagram of the power signal VDD received by the input terminal 301, and V1 represents the first control voltage. A waveform diagram of the first control voltage V1 outputted from the output terminal 334, Rs represents a waveform diagram of the reset signal Rs outputted from the output terminal 302, and V2 represents a waveform diagram of the second control voltage V2. The power-on reset circuit 10 will be specifically described with reference to FIG. 2 . Work with it.

At time t1, the integrated circuit 20 (see FIG. 4) starts to be powered up, and the power signal VDD rises from zero potential (0).

At time t2, when the power signal VDD is greater than Vth, where Vth represents the turn-on voltage of the P-type transistor or the N-type transistor, the fourth P-type transistor MP4 is turned on, and the power signal VDD is transmitted by the fourth P-type transistor MP4. The charging circuit 332 starts charging the first capacitor C1, whereby the first control voltage V1 outputted by the first control voltage output terminal 334 starts to gradually increase from the zero potential. At the same time, since the first control voltage V1 has not reached the voltage value that causes the shaping circuit 370 to reverse, the shaping circuit 370 outputs the low potential reset signal Rs having the same phase as the first control voltage V1, whereby the integrated circuit 20 Start to enter the reset state.

Correspondingly, the third inverter INV3 of the control circuit 350 is used to invert the reset signal Rs, that is, the second control signal signal V2 is high, and the fifth N-type transistor MN5 is turned on, and the discharge circuit 333 A discharge path is formed to discharge the charging circuit 331 to slow down the charging speed of the charging circuit 331. The fifth P-type transistor MP5 is in an off state under the control of the high potential second control signal V2.

At time t3, after the power signal VDD gradually rises and stabilizes, the first control voltage V1 on the first capacitor C1 in the charging circuit 131 is greater than the reverse voltage of the shaping circuit 370, so that the shaping circuit 370 outputs a high potential. The reset signal Rs is thereby completed, and the integrated circuit 20 is reset and enters a stable operating state. That is, the integrated circuit 20 is in the reset state during the reset time period from the time t1 to time t3.

Correspondingly, when the reset signal Rs is high, the second control voltage V2 is low, and the fifth N-type transistor MN5 is turned off, and the discharge path of the discharge circuit 333 is turned on and off. The discharge to the charging circuit 331 is stopped. The fifth P-type transistor MP5 is turned on under the control of the low potential second control signal V2, whereby the power signal VDD charges the charging circuit 331 via the fifth P-type transistor MP5, thereby maintaining the first control voltage in the charging circuit 331. V1 is stably maintained at a high potential state, so that the power-on reset circuit 30 outputs a stable high-potential reset signal Rs.

Compared with the prior art, the fifth N-type transistor MN5 is in an off state after the reset is completed, so that the discharge circuit 333 is electrically disconnected without current passing, whereby the discharge circuit 333 does not generate work after the reset is completed. The power consumption is effectively reduced, and the static power consumption of the power-on reset circuit is effectively reduced, and the reset signal Rs is guaranteed to have no noise.

It should be noted that since the functional circuit corresponding to the low voltage detection is not provided in the modified embodiment, the present embodiment only introduces the power-on reset process.

As described above, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application.

10‧‧‧Power-on reset circuit

101‧‧‧ input

102‧‧‧output

110‧‧‧reference voltage generating circuit

R1‧‧‧first resistance

MP1‧‧‧First P-type transistor

MP2‧‧‧Second P-type transistor

MP3‧‧‧ Third P-type transistor

MN1‧‧‧First N-type transistor

MN2‧‧‧Second N-type transistor

MN3‧‧‧ Third N-type transistor

MN4‧‧‧4th N-type transistor

R2‧‧‧second resistance

111‧‧‧reference voltage output

130‧‧‧Charge and discharge circuit

131‧‧‧Switch circuit

132‧‧‧Charging circuit

133‧‧‧Discharge circuit

134‧‧‧First control voltage output

R3‧‧‧ third resistor

R4‧‧‧fourth resistor

R5‧‧‧ fifth resistor

150‧‧‧Control circuit

151‧‧‧second control voltage output

170‧‧‧Shaping circuit

INV1‧‧‧First Inverter

INV2‧‧‧Second inverter

INV3‧‧‧ third inverter

171‧‧‧Low-voltage detection terminal

A, B, C, D‧‧‧ nodes

Claims (18)

A power-on reset circuit is configured to output a reset signal, including an input end, a charge and discharge circuit, a shaping circuit and an output end, for receiving the power signal, the power source is received from the beginning of receiving the power signal, and the input terminal is configured to receive the power signal, the power source The charging circuit charges the charging and discharging circuit, and the charging circuit outputs a first control voltage, and the shaping circuit is configured to obtain a reset signal according to the first control signal, and the reset signal is output from the output end, wherein the reset signal is outputted from the output end, wherein the reset signal is outputted from the output terminal The charging and discharging circuit comprises a charging circuit and a discharging circuit, wherein the charging circuit is configured to perform charging according to the power signal, and the discharging circuit discharges the charging circuit during charging of the charging circuit to slow down the charging speed of the discharging circuit and reduce The first control voltage and the noise signal of the reset signal; the charging circuit includes a third resistor, a first capacitor and a first control voltage output end, the third resistor receives the power signal at one end, and the other end is electrically connected to the first control a voltage output end, the first capacitor is electrically connected to the first control voltage output end, and the other end is electrically A ground terminal. The power-on reset circuit of claim 1, wherein the power-on reset circuit further includes a reference voltage generating circuit electrically connected to the input terminal and the charging and discharging circuit for receiving from the input terminal The power signal outputs a reference voltage to the charging and discharging circuit according to the power signal to control the charging and discharging circuit to start charging and discharging. The electrical reset circuit of claim 1, wherein the reference voltage generating circuit comprises a first resistor, a first P-type transistor, a first N-type transistor, and a second resistor and a reference voltage output, the first One end of the resistor is electrically connected to the input end, and the other end is electrically connected to the source of the first P-type, and the gate and the drain of the first P-type transistor are directly electrically connected to the reference voltage output end, the first The gate and the drain of the N-type transistor are directly electrically connected to the reference voltage output end, and the source of the first N-type transistor is electrically connected to the second resistor, and the second resistor is electrically connected to the first end. N-type transistor, the other end is connected to the ground, and the reference voltage output is used to output the reference Pressure. The electrical reset circuit of claim 3, wherein the first resistor and the second resistor have the same resistance value, and the first P-type transistor has the same on-resistance as the first N-type transistor. The electrical reset circuit of claim 1, wherein the charge and discharge circuit further comprises a switch circuit for selectively transmitting a power signal to the charging circuit under the control of the reference voltage, the switch circuit comprising a second a P-type transistor, the gate of the second P-type transistor is electrically connected to the reference voltage output terminal for receiving the reference voltage, and the source of the second P-type transistor is electrically connected to the input terminal, and the second P-type battery The anode of the crystal is electrically connected to the third resistor. The electrical reset circuit of claim 1, wherein the discharge circuit comprises a fourth resistor, a fifth resistor, and a second N-type transistor, wherein the fourth resistor is electrically connected to one end of the third resistor receiving power signal. The other end is electrically connected to the fifth resistor, the fifth resistor is electrically connected to the fourth resistor at one end, the other end is electrically connected to the second N-type transistor, and the gate of the second N-type transistor is electrically connected to the reference voltage. The output terminal, the second N-type transistor is electrically connected to the fifth resistor, and the source of the second N-type transistor is electrically connected to the ground. The electrical reset circuit of claim 6, wherein the discharge circuit further comprises a third N-type transistor as a low voltage detection of the power signal, and the gate of the third N-type transistor is electrically connected to the shaping circuit, The drain and the source of the third N-type transistor are electrically connected to the two ends of the fourth resistor, respectively, and the third N-type transistor increases the discharge speed of the discharge circuit when the power signal is detected to be lower than a predetermined threshold. The power-on reset circuit of claim 6, wherein the power-on reset circuit further comprises a control circuit electrically connected to the reference voltage output terminal and the first control voltage output terminal for using the reference voltage and the first The power supply signal and the second control voltage are selectively output under the control of the control voltage. The electrical reset circuit of claim 8, wherein the control circuit comprises a third P-type transistor and a fourth N-type transistor, wherein a gate of the third P-type transistor is electrically connected to the reference voltage output terminal, The source is electrically connected to the input end, the drain is electrically connected to the fourth N-type transistor, the gate of the fourth N-type transistor is electrically connected to the first control voltage output end, and the drain is electrically connected to the third P-type electric a drain of the crystal, the source being connected to the ground, wherein a node between the drain of the third P-type transistor and the drain of the fourth N-type transistor serves as a second control voltage output for outputting the second The control voltage is electrically connected to the shaping circuit. The electrical reset circuit of claim 8, wherein the shaping circuit comprises a first inverter, a second inverter and a third inverter connected in series, and the input end of the first inverter is electrically Connecting the second control voltage output end, the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter is electrically connected to the input of the third inverter The output end of the third inverter is electrically connected to the output end. The power-on reset circuit of claim 10, wherein the output of the second inverter is a low-voltage detection terminal, and the low-voltage detection terminal is electrically connected to the gate of the third N-type transistor. The electrical reset circuit of claim 1, wherein the charging circuit comprises a third resistor, a first capacitor, and a first control voltage output end, the third resistor receiving the power signal at one end and electrically connecting the other end a control voltage output end, the first capacitor is electrically connected to the first control voltage output end, and the other end is electrically connected to the ground end, and the first control voltage output end is used for outputting the first control voltage. The electrical reset circuit of claim 12, wherein the charge and discharge circuit further comprises a switch circuit, the switch circuit comprising a fourth P-type transistor, the source of the fourth P-type transistor being electrically connected to the input end And for receiving a power signal, the gate and the drain of the fourth P-type transistor are directly electrically connected to the charging circuit. The power-on reset circuit of claim 12, wherein the power-on reset circuit further includes a control circuit electrically connected to the output terminal for outputting the second control voltage according to the reset signal, the control circuit An inverter is included, and an input end of the inverter is electrically connected to the output end, and an output end of the inverter is electrically connected for outputting the second control voltage, and the second control circuit is The voltage is opposite to the phase of the reset signal. The electrical reset circuit of claim 14, wherein the charge and discharge circuit further comprises a holding circuit, the holding circuit comprising a fifth P-type transistor, wherein the gate of the fifth P-type transistor is electrically Connected to the second control voltage output terminal, the drain of the fifth P-type transistor is electrically connected to the drain of the fifth P-type transistor, and the source is electrically connected to the input end. The electrical reset circuit of claim 14, wherein the discharge circuit comprises a fourth resistor, a fifth resistor, and a fifth N-type transistor, wherein the fourth resistor is electrically connected to one end of the third resistor receiving power signal. The other end is electrically connected to the fifth resistor, the fifth resistor is electrically connected to the fourth resistor, and the other end is electrically connected to the fifth N-type transistor, and the gate of the fifth N-type transistor is electrically connected to the first resistor. The second N-type transistor is electrically connected to the fifth resistor, and the source of the second N-type transistor is electrically connected to the ground. The electrical reset circuit of claim 12, wherein the shaping circuit is electrically connected to the first control voltage output terminal for amplifying and shaping the first control voltage to form the reset signal, wherein the shaping circuit comprises a first inverter connected in series with a second inverter, wherein an input end of the first inverter is electrically connected to the first control voltage output end, and an output end of the first inverter is electrically connected to the second reverse The output end of the phase converter is electrically connected to the output end of the second inverter for outputting the reset signal. The electrical reset circuit of claim 17, wherein the first inverter is a Schmitt trigger.