TWI543333B - Chip package and method for forming the same - Google Patents

Description

Chip package and method of manufacturing same

The present invention relates to a chip package technology, and more particularly to a chip package and a method of fabricating the same.

The wafer packaging process is an important step in the process of forming electronic products. In addition to protecting the wafer from the external environment, the chip package also provides an electrical connection path between the electronic components inside the wafer and the outside.

The fabrication process of a chip package having a sensing device typically includes forming a cap on a wafer having a sensing device and forming an opening in the cap to expose the sensing device.

However, the sensing device is susceptible to contamination or damage during conventional processes and during the sensing function of the chip package, thereby reducing the reliability or quality of the chip package.

Therefore, it is necessary to find a novel chip package and a method of manufacturing the same that can solve or ameliorate the above problems.

Embodiments of the present invention provide a chip package including a first substrate, wherein a surface of the first substrate has a sensing device. A second substrate is bonded to the surface of the first substrate and includes a first opening to expose the sensing device. a spacer layer is disposed between the first substrate and the second substrate, and is disposed in the spacer layer A first aperture is included in communication with the first opening to expose the sensing device. The spacer layer further includes at least one of the first substrate and the second substrate exposed by the meandering channel and is not in communication with the first hole, wherein the meandering channel has at least one open end extending inwardly from a sidewall of the spacer layer.

Embodiments of the present invention provide a method of fabricating a chip package, comprising providing a first substrate and a second substrate, wherein a surface of the first substrate has a sensing device. The second substrate is bonded to the surface of the first substrate through a spacer layer. A first opening is formed in the second substrate, aligned with the sensing device, wherein the spacer layer includes a first hole in communication with the first opening to expose the sensing device. The spacer layer further includes at least one meandering channel, exposing a portion of the first substrate and the second substrate, and not communicating with the first hole. The meandering channel has at least one open end extending inwardly from a side wall of the spacer layer.

100‧‧‧ first base

100a, 100b‧‧‧ surface

120‧‧‧ wafer area

140‧‧‧Electrical mat

160‧‧‧Sensing device

200‧‧‧ spacer

200a, 200b, 200c, 200d‧‧‧ side walls

220‧‧‧ first hole

240‧‧‧Zigzag channel

250‧‧‧Open end

260, 270, 280‧ ‧ path

290‧‧‧Second hole

300‧‧‧second base

305‧‧‧ first opening

310‧‧‧ second opening

320‧‧‧Insulation

340‧‧‧Rewiring layer

360‧‧‧passivation protective layer

380‧‧‧ third opening

400‧‧‧Electrical structure

420‧‧‧Fixed layer

SC‧‧‧Cut Road

1A to 1F are cross-sectional views showing a method of manufacturing a chip package in accordance with an embodiment of the present invention.

2 and 3 are schematic plan views showing patterned spacer layers in a chip package in accordance with various embodiments of the present invention.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions only For the purpose of simplicity and clarity of the invention, it is not intended to represent any of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

A chip package in accordance with an embodiment of the present invention can be used to package a microelectromechanical system wafer. However, the application is not limited thereto. For example, in the embodiment of the chip package of the present invention, it can be applied to various active or passive elements, digital circuits or analog circuits. The electronic components of the integrated circuit are, for example, related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat, light, and A physical sensor that measures physical quantities such as pressure. In particular, wafer scale package (WSP) processes can be used for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Semiconductor wafers such as accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads Package.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also suitable for stacking by means of stacking. A plurality of wafers of a circuit to form a chip package of multi-layer integrated circuit devices.

Referring to FIGS. 1F and 2, there are shown schematic cross-sectional views of a chip package and a plan view of a patterned spacer layer in a chip package, respectively, in accordance with an embodiment of the present invention. Further, Fig. 1F is a schematic cross-sectional view taken along line I-I' in Fig. 2; In this embodiment, the chip package includes a first substrate 100, a sensing device 160, a spacer layer 200, and a second substrate 300. The first substrate 100 has a surface 100a and another surface 100b opposite thereto. In an embodiment, the first substrate 100 can be a germanium substrate or other semiconductor substrate. In another embodiment, the first substrate 100 is a germanium wafer to facilitate a wafer level packaging process. In the present embodiment, the first substrate 100 has a plurality of conductive pads 140 therein that can be adjacent to the surface 100a. In an embodiment, the conductive pad 140 may be a single conductive layer or a conductive layer structure having multiple layers.

The sensing device 160 is disposed on the surface 100a of the first substrate 100. In one embodiment, sensing device 160 includes a temperature sensing element, a humidity sensing element, combinations of the foregoing, or other suitable sensing elements. In one embodiment, the sensing component in the sensing device 160 can be electrically connected to the conductive pad 140 through an interconnect structure (not shown). In another embodiment, the surface 100a of the first substrate 100 has a light sensitive area (not shown) disposed between the conductive pad 140 and the sensing device 160, and the light sensitive area needs to be protected from light to ensure The sensing device 160 can operate smoothly. Although the sensing device 160 depicted in FIG. 2 has a circular shape, the sensing device 160 can have a rectangular shape, an elliptical shape, or other suitable shape.

a spacer layer (or called a dam) 200 disposed on the first substrate The surface 100a of 100 is over and covered with a conductive pad 140. In the present embodiment, the spacer layer 200 has a first hole 220 therein to expose the sensing device 160. In the present embodiment, the size of the first hole 220 is larger than the size of the sensing device 160, and the first hole 220 may include various shapes such as a circle, a rectangle, an ellipse, a sector, or a polygon.

Furthermore, the spacer layer 200 also has one or more meandering channels 240 extending through the upper and lower surfaces of the spacer layer 200 to expose a portion of the surface 100a of the first substrate 100 and not to the first hole 220. Connected, wherein the second figure is illustrated by a plurality of meandering channels 240 as an example. In one embodiment, the plurality of meandering channels 240 each have one or more open ends 250 adjacent the sidewalls 200a, 200b or 200c of the spacer layer 200 and extend inwardly from the sidewalls 200a, 200b or 200c of the spacer layer 200.

In an embodiment, the path of the meandering channel 240 includes a trifurcated path (eg, path 260), a zigzag path (eg, path 270), or a combination of the foregoing (eg, path 280). In other embodiments, the path of the meandering channel 240 can include any non-straight path. In an embodiment, the meandering channel 240 includes only vertical corners, as shown in FIG. In another embodiment, the meandering channel 240 includes vertical corners, rounded corners, and combinations of the foregoing, as shown in FIG. In other embodiments, the meandering channel 240 can also include corners of other angles. In addition, although not shown in the drawings, it can be understood that as long as at least one of the side walls 200a, 200b, 200c, and 200d of the spacer layer 200 is adjacent to the at least one open end 250, the meandering channel 240 in the spacer layer 200 The number and path, the number and location of the corresponding open ends 250, can all have other configurations.

In an embodiment, the spacer layer 200 further includes a second hole. 290, through the upper surface and the lower surface of the spacer layer 200, expose a portion of the first substrate 100, and is not in communication with the first hole 220 and the meandering channel 240, as shown in FIG. In another embodiment, a pair of second holes 290 may be included in the spacer layer 200 as alignment marks for the bonding process, as shown in FIG. Although the second holes 290 illustrated in Figures 2 and 3 have a rectangular outer shape, the second holes 290 may have a circular shape, an elliptical shape, or other shape suitable as an alignment mark.

In the present embodiment, the area ratio of the spacer layer 200 having the meandering channel 240 to the first substrate 100 is less than 50%, so that excessive bubbles are generated in the spacer layer 200 to reduce the adhesion benefit. Moreover, from a top view, the meandering channel 240 is not overlapped with the conductive pad 140, so that the spacer layer 200 is disposed on the first substrate 100 outside the conductive pad 140 to provide a structure disposed on the opposite side of the conductive pad 140. (For example, the through-hole electrode 340) has sufficient supporting force.

In this embodiment, the spacer layer 200 can cover the light sensitive area (not shown) to prevent the light sensitive area from being exposed to light. In an embodiment, the spacer layer 200 does not substantially absorb moisture. In an embodiment, the spacer layer 200 is not viscous, and thus the spacer layer 200 can be in contact with an additional adhesive. In another embodiment, the spacer layer 200 can be viscous so that the spacer layer 200 can be out of contact with any adhesive to ensure that the spacer layer 200 is not moved by the adhesive. At the same time, since the adhesive is not required, the adhesive overflow device can be prevented from contaminating the sensing device 160.

In the present embodiment, the spacer layer 200 may include an epoxy resin, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), an organic polymer material (for example, poly phthalate) Polyimide, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, acrylic acid Acrylates, photoresist materials or other suitable insulating materials.

The second substrate 300 is bonded to the surface 100a of the first substrate 100 through the spacer layer 200 such that the meandering channels 240 and the second holes 290 in the spacer layer 200 also expose a portion of the second substrate 300. In an embodiment, the second substrate 300 can be a cover, a glass cover or other suitable cover without any active or passive components therein. In the present embodiment, the second substrate 300 has a first opening 305 therein, which is aligned with the sensing device 160 and communicates with the first hole 220 of the spacer layer 200 to expose the sensing device 160. In an embodiment, the size of the first opening 305 is greater than the size of the sensing device 160. In other embodiments, the size of the first opening 305 can be equal to or less than the size of the sensing device 160. The first opening 305 can include various shapes such as a circle, a rectangle, an ellipse, a sector, or a polygon. In an embodiment, the sidewalls of the first opening 305 are not coplanar with the sidewalls of the first aperture 220 of the spacer layer 200. In another embodiment, the sidewalls of the first opening 305 can be coplanar with the sidewalls of the first aperture 220 of the spacer layer 200.

In other embodiments, an insulating layer (not shown) may be selectively included between the second substrate 300 and the spacer layer 200, and the first opening 305 passes through the insulating layer to expose the sensing device 160. Furthermore, the insulating layer may comprise an oxide or other suitable insulating material.

In this embodiment, the chip package further includes an insulating layer 320, a redistribution layer (RDL) 340, a passivation layer 360, and a conductive structure (eg, solder balls, bumps, or conductive pillars). 400 is disposed on the surface 100b of the first substrate 100.

For example, the first substrate 100 has a second opening 310 (labeled in FIG. 1C) extending from the surface 100b of the first substrate 100 toward the surface 100a. The conductive pad 140 is exposed. The insulating layer 320 is disposed on the surface 100b of the first substrate 100 and extends to the sidewall of the second opening 310 of the first substrate 100 and exposes the surface of the conductive pad 140. In the present embodiment, the insulating layer 320 may include an epoxy resin, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), an organic polymer material (for example, poly phthalate) Amine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate) or other suitable insulating material.

The redistribution layer 340 is disposed on the insulating layer 320 and extends to the bottom of the second opening 310 of the first substrate 100. The redistribution layer 340 is in direct contact with the exposed conductive pad 140 to be electrically connected to the conductive pad 140 and electrically isolated from the first substrate 100 through the insulating layer 320. Therefore, the redistribution layer 340 in the second opening 310 is also referred to as a through silicon via (TSV) as shown in FIG. 1F. In an embodiment, the redistribution layer 340 can comprise copper, aluminum, gold, platinum, nickel, tin, combinations of the foregoing, or other suitable electrically conductive materials. In another embodiment, the redistribution layer 340 may comprise a conductive high molecular material or a conductive ceramic material (eg, indium tin oxide or indium zinc oxide).

In another embodiment, the second opening 310 of the first substrate 100 exposes the sidewall of the conductive pad 140, and the redistribution layer 340 is electrically isolated from the first substrate 100 through the insulating layer 320, and the exposed conductive pad 140 The sidewalls are in direct contact and are electrically connected to the conductive pads 140 in a T-contact manner. In still another embodiment, the second opening 310 of the first substrate 100 may pass through the conductive pad 140 or further into the spacer layer 200 such that the redistribution layer 340 may be in direct contact with the interior of the conductive pad 140, A ring-contact is electrically connected to the conductive pad 140.

The passivation protective layer 360 is disposed on the redistribution layer 340 and filled in the second opening 310 of the first substrate 100 to cover the redistribution layer 340. The passivation protective layer 360 has a third opening 380 (labeled in FIG. 1E) to expose a portion of the redistribution layer 340 on the surface 100b. In the present embodiment, the passivation protective layer 360 may include an epoxy resin, a powder mask, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), and organic high. Molecular materials (eg, polyimine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate), photoresist materials, or other suitable insulating materials.

The conductive structure 400 is disposed in the third opening 380 of the passivation protection layer 360 to directly contact the exposed redistribution layer 340 and electrically connected to the redistribution layer 340. In this embodiment, the electrically conductive structure 400 can comprise tin, lead, copper, gold, nickel, combinations of the foregoing, or other suitable electrically conductive materials.

According to the above embodiment of the present invention, since the area ratio of the spacer layer 200 to the first substrate 100 is more than 50%, it is easy to generate bubbles in the spacer layer 200 to reduce the adhesion effect, and thus the meandering of the spacer layer 200 is formed in the spacer layer 200. The spacer 240 is patterned by the via 240 such that the area ratio of the spacer layer 200 to the first substrate 100 is reduced (eg, less than 50%), and the adhesion of the spacer layer 200 can be increased. Moreover, the meandering channel 240 extending through the spacer layer 200 can help slow the stress between the spacer layer 200 and the first substrate 100 and 300, improving the reliability of the chip package.

Additionally, a wafer package system having a temperature or humidity sensing device is used to contact ambient air to measure the temperature or humidity of the environment. However, moisture in the environment may remain in the chip package, resulting in reduced sensitivity of the sensing device. According to the above embodiment of the invention, due to the tortuous path in the spacer layer 200 The opening 240 has an open end 250 extending inwardly from the side wall 200a, 200b or 200c of the spacer layer 200, so that a path to the external environment can be provided in the spacer layer 200 to prevent moisture from remaining in the spacer layer 200 and affecting sensing. The sensing capabilities of device 160.

Moreover, since the path of the open end 250 toward the meandering channel 240 includes a non-straight path, and the meandering channel 240 includes a plurality of corners, the path from the open end 250 to the sensing device 160 is extended and can be made non-straight The path and corners intercept and block various residues generated in the process (eg, etching process or cutting process) to prevent residue contamination of the sensing device 160, thereby improving the reliability of the chip package. In addition, the spacer layer 200 has a plurality of meandering channels 240 and corresponding open ends 250, which can further enhance the protection effect of the sensing device 160.

Hereinafter, a method of manufacturing a chip package according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1F and 2, wherein FIGS. 1A to 1F are schematic cross-sectional views showing a method of manufacturing a chip package according to an embodiment of the present invention. And FIG. 2 is a schematic plan view showing a patterned spacer layer in a chip package according to an embodiment of the invention. Further, Fig. 1F is a schematic cross-sectional view taken along line I-I' in Fig. 2;

Referring to FIG. 1A, a first substrate 100 having a surface 100a and another surface 100b opposite thereto is provided and includes a plurality of wafer regions 120. In an embodiment, the first substrate 100 can be a germanium substrate or other semiconductor substrate. In another embodiment, the first substrate 100 is a germanium wafer to facilitate a wafer level packaging process.

In the present embodiment, each of the wafer regions 120 of the first substrate 100 is There are a plurality of conductive pads 140 that can be adjacent to surface 100a. In an embodiment, the conductive pad 140 may be a single conductive layer or a conductive layer structure having multiple layers.

In the present embodiment, a sensing device 160 is disposed on the surface 100a of the first substrate 100 in each of the wafer regions 120. In one embodiment, sensing device 160 includes a temperature sensing element, a humidity sensing element, combinations of the foregoing, or other suitable sensing elements. In an embodiment, the sensing device 260 can be electrically connected to the conductive pad 140 through an interconnect structure (not shown).

Referring to FIG. 1B, a spacer layer may be formed on the surface 100a of the first substrate 100 through a deposition process (eg, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process) (or It is called a dam 200 and covers the conductive pad 140.

Next, the spacer layer 200 is patterned, and a plurality of first holes 220 are formed in the spacer layer 200 to expose the sensing devices 160 in each of the wafer regions 120, respectively. For example, the spacer layer 200 in each wafer region 120 has a first hole 220 that exposes the sensing device 160, as shown in FIG. In the present embodiment, the size of the first hole 220 is larger than the size of the sensing device 160, and the first hole 220 may include various shapes such as a circle, a rectangle, an ellipse, a sector, or a polygon.

As shown in FIG. 2, in the present embodiment, the step of patterning the spacer layer 200 further includes forming a plurality of meandering channels 240 in the spacer layer 200 that penetrate the upper surface and the lower surface of the spacer layer 200 to expose portions. The first substrate 100. Moreover, the meandering channel 240 is not in communication with the first aperture 220 and includes a vertical corner. In another embodiment, the meandering channel 240 includes vertical corners, rounded corners, and combinations of the foregoing, as shown in FIG. In other embodiments, the meandering channel 240 can be packaged Includes corners from other angles.

In an embodiment, the step of patterning the spacer layer 200 further includes forming a second hole 290 in the spacer layer 200, which penetrates the upper surface and the lower surface of the spacer layer 200 to expose a portion of the first substrate 100, and It is not in communication with the first hole 220 and the meandering channel 240, as shown in FIG. In another embodiment, a pair of second holes 290 may be formed in the spacer layer 200 as alignment marks for the bonding process, as shown in FIG. Additionally, a pair of second holes 290 as alignment marks may also be formed in different wafer regions 120. Although the second holes 290 illustrated in Figures 2 and 3 have a rectangular outer shape, the second holes 290 may have a circular shape, an elliptical shape, or other shape suitable as an alignment mark.

In an embodiment, the spacer layer 200 may include a photoresist material, and thus the step of patterning the spacer layer 200 includes performing an exposure process and a development process on the spacer layer 200. In other embodiments, the spacer layer 200 may comprise a non-photoresist material, such as an inorganic material (eg, hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide, or a combination thereof), an organic polymeric material (eg, benzene) Cyclocyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, acrylates, or other suitable insulating materials, thus patterning the spacer layer 200 The steps include performing a lithography process and an etch process on the spacer layer 200 (eg, a dry etch process, a wet etch process, a plasma etch process, a reactive ion etch process, or other suitable process).

In an embodiment, the spacer layer 200 does not substantially absorb moisture. In an embodiment, the spacer layer 200 is not viscous, and thus the spacer layer 200 can be in contact with an additional adhesive. In another embodiment, the spacer layer 200 may have a viscosity due to The spacer layer 200 may not be in contact with any adhesive to ensure that the spacer layer 200 is not moved by the adhesive. At the same time, since the adhesive is not required, the adhesive overflow device can be prevented from contaminating the sensing device 160.

In the present embodiment, the area ratio of the spacer layer 200 to the first substrate 100 is less than 50% to avoid generation of bubbles in the spacer layer 200 to reduce the adhesion benefit. Moreover, from a top view, the meandering channel 240 is not overlapped with the conductive pad 140, so that the spacer layer 200 is disposed on the first substrate 100 outside the conductive pad 140 to provide a structure disposed on the opposite side of the conductive pad 140. (For example, the through-hole electrode 340 in FIG. 1D) has sufficient supporting force. In this embodiment, the spacer layer 200 can cover the light sensitive area (not shown) to prevent the light sensitive area from being exposed to light.

Next, after the spacer layer 200 is patterned, the first substrate 100 may be bonded to the second substrate 300 through the spacer layer 200. In an embodiment, the second substrate 300 can be a cover, a cover glass or other suitable cover without any active or passive components therein. In other embodiments, an insulating layer (not shown) may be selectively included between the second substrate 300 and the spacer layer 200, and the insulating layer may include an oxide or other suitable insulating material.

In another embodiment, the patterned spacer layer 200 may be formed on the second substrate 300 first, and the meandering channels 240 and the first holes 220 in the spacer layer 200 expose a portion of the second substrate 300. Next, the second substrate 300 is bonded to the first substrate 100 through the spacer layer 200 on the second substrate 300 such that the spacer layer 200 covers the conductive pad 140, and the first hole 220 in the spacer layer 200 is aligned with the first substrate 100. The sensing device 160 is on, and the meandering channel 240 in the spacer layer 200 does not overlap the conductive pad 140 from a top view.

Referring to FIG. 1C, the second substrate 300 is used as a carrier substrate. The lithography process and the etch process (eg, dry etch process, wet etch process, plasma etch process, reactive ion etch process, or other suitable process) form a plurality of numbers in the first substrate 100 in each wafer region 120. The second opening 310. The second opening 310 extends from the surface 100b of the first substrate 100 toward the surface 100a and exposes each of the conductive pads 140 adjacent to the surface 100a, respectively.

Then, an insulating layer 320 is formed on the surface 100b of the first substrate 100 through a deposition process (for example, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process), which extends to the first A second opening 310 of a substrate 100. In the present embodiment, the insulating layer 320 may include an epoxy resin, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), an organic polymer material (for example, poly phthalate) Amine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate) or other suitable insulating material.

Referring to FIG. 1D, the insulating layer 320 on the bottom of the second opening 310 may be removed through a lithography process and an etching process to expose the surface of the conductive pad 140. Then, through the deposition process (for example, coating process, physical vapor deposition process, chemical vapor deposition process, electroplating process, electroless process or other suitable process), lithography process and etching process, on the insulating layer 320 A patterned redistribution layer 340 is formed.

The redistribution layer 340 extends to the bottom of the second opening 310 of the first substrate 100 and is in direct contact with the exposed conductive pad 140 to be electrically connected to the conductive pad 140 and electrically connected to the first substrate 100 through the insulating layer 320. isolation. Therefore, the redistribution layer 340 in the second opening 310 is also referred to as a via via electrode. In an embodiment, the redistribution layer 340 may include copper, aluminum, gold, platinum, nickel, tin, the aforementioned group A conductive polymer material, a conductive ceramic material (for example, indium tin oxide or indium zinc oxide) or other suitable conductive material.

In another embodiment, the second opening 310 of the first substrate 100 may expose sidewalls of the conductive pad 140, and the redistribution layer 340 is electrically isolated from the first substrate 100 through the insulating layer 320, and the exposed conductive pads The sidewalls of 140 are in direct contact and are electrically connected to the conductive pads 140 in a T-contact. In still another embodiment, the second opening 310 of the first substrate 100 may pass through the conductive pad 140 or further into the spacer layer 200 such that the redistribution layer 340 may be in direct contact with the interior of the conductive pad 140, and The contact is electrically connected to the conductive pad 140.

Then, a passivation protective layer 360 is formed on the redistribution layer 340 through the deposition process, and is filled into the second opening 310 of the first substrate 100 to cover the redistribution layer 340. Then, a plurality of third openings 380 are formed in the passivation protective layer 360 in each of the wafer regions 120 to expose a portion of the redistribution layer 340 on the surface 100b of the first substrate 100 through a lithography process and an etching process. . In the present embodiment, the passivation protective layer 360 may include an epoxy resin, a powder mask, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), and organic high. Molecular materials (eg, polyimine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate) or other suitable insulating materials. In another embodiment, the passivation protective layer 360 may include a photoresist material and may pass through an exposure and development process to form a third opening 380.

Referring to FIG. 1E, a conductive structure (eg, solder balls, bumps, or conductive pillars) 400 is formed in the third opening 380 of the passivation protective layer 360 to directly contact the exposed redistribution layer 340, and patterned The redistribution layer 340 is electrically connected. For example, a solder may be formed in the third opening 380 of the passivation protective layer 360 through an electroplating process, a screen printing process, or other suitable process, and a reflow process may be performed to form the conductive structure 400. . In this embodiment, the electrically conductive structure 400 can comprise tin, lead, copper, gold, nickel, combinations of the foregoing, or other suitable electrically conductive materials.

Next, a pinned layer 420 (eg, tape) is formed over the passivation protective layer 360 and the conductive structure 400 to provide a planar surface and to protect the conductive structure 400. Then, with the fixed layer 420 as a support, through the lithography process and the etching process (for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable processes), in the second substrate 300 Forming a plurality of first openings 305 that are respectively aligned with the sensing devices 160 in each of the wafer regions 120 and in communication with corresponding first holes 220 in the spacer layer 200 to expose the sensing devices in each of the wafer regions 120 160.

In an embodiment, the size of the first opening 305 is greater than the size of the sensing device 160. In other embodiments, the size of the first opening 305 can be equal to or less than the size of the sensing device 160. The first opening 305 can include various shapes such as a circle, a rectangle, an ellipse, a sector, or a polygon. In an embodiment, the sidewalls of the first opening 305 are not coplanar with the sidewalls of the first aperture 220 of the spacer layer 200. In another embodiment, the sidewalls of the first opening 305 can be coplanar with the sidewalls of the first aperture 220 of the spacer layer 200. In other embodiments, when an insulating layer (not shown) is included between the second substrate 300 and the spacer layer 200, the first opening 305 passes through the insulating layer to expose the sensing device 160.

In this embodiment, before the first opening 305 is formed, the second layer 300 may be thinned by using the fixing layer 420 as a support. For example, a mechanical polishing process, a chemical mechanical polishing process, an etching process, a combination of the foregoing, or other suitable processes) to reduce the thickness of the second substrate 300.

Next, the first substrates 100 and 300 and the spacer layer 200 may be diced along the scribe lines SC between adjacent wafer regions 200, and the pinned layer 420 may be removed to form a plurality of individual chip packages, as shown in FIG. 1F.

In the present embodiment, the meandering channels 240 in each of the wafer regions 200 are in communication with the meandering channels 240 in the adjacent at least one wafer region 200, as shown in FIG. 1D. That is, the scribe lines SC between adjacent wafer regions 200 will pass through the meandering channels 240, so after cutting the spacer layer 200, at least one open end 250 of the meandering channel 240 may be formed in each of the wafer packages, adjacent to The sidewalls 200a, 200b or 200c of the spacer layer 200 extend inwardly from the sidewalls 200a, 200b or 200c of the spacer layer 200, as shown in FIG.

In an embodiment, the path of the meandering channel 240 includes a trifurcated path (eg, path 260), a zigzag path (eg, path 270), or a combination of the foregoing (eg, path 280). In other embodiments, the path of the meandering channel 240 can include any non-straight path. In addition, although not shown in the drawings, it can be understood that as long as at least one of the side walls 200a, 200b, 200c, and 200d of the spacer layer 200 is adjacent to the at least one open end 250, the meandering channel 240 in the spacer layer 200 The number and path, the number and location of the corresponding open ends 250, can all have other configurations.

According to the above embodiment of the present invention, the meandering channel 240 is formed in the spacer layer 200, and the area ratio (for example, less than 50%) of the spacer layer 200 to the first substrate 100 is reduced, and the adhesion of the spacer layer 200 can be increased. Moreover, since the meandering channel 240 in the spacer layer 200 has an open end 250, moisture is prevented from remaining in the spacer layer. The sensing capability of the sensing device 160 is affected within 200. Moreover, by forming a non-flat path in the tortuous path 240, the path from the open end 250 to the sensing device 160 is extended, and it is advantageous to intercept and block various residues generated in the process to avoid residual pollution. The measuring device 160 further enhances the reliability of the chip package.

In addition, since a through-hole electrode, a ring contact or a T-contact is used as a path for external electrical connection of a substrate having a sensing device, without using a bonding wire and a lead frame, cost can be saved and the chip package can be made The size can be further reduced.

While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

100‧‧‧ first base

100a‧‧‧ surface

160‧‧‧Sensing device

200‧‧‧ spacer

200a, 200b, 200c, 200d‧‧‧ side walls

220‧‧‧ first hole

240‧‧‧Zigzag channel

250‧‧‧Open end

260, 270, 280‧ ‧ path

290‧‧‧Second hole

Claims (20)

A chip package comprising: a first substrate, wherein a surface of the first substrate has a sensing device; a second substrate bonded to the surface of the first substrate and including a first opening Exposing the sensing device; and a spacer layer disposed between the first substrate and the second substrate, and the spacer layer includes: a first hole communicating with the first opening to expose the feeling Measuring device; and at least one meandering channel exposing a portion of the first substrate and the second substrate and not communicating with the first hole, wherein the at least one meandering channel has at least one open end, one from the spacer layer The side walls extend inward. The chip package of claim 1, wherein the path of the at least one meandering channel comprises a three-pronged path, a zigzag path, or a combination thereof. The chip package of claim 1, wherein the at least one meandering channel comprises a vertical corner, a rounded corner, or a combination thereof. The chip package of claim 1, wherein the at least one meandering channel has a plurality of open ends adjacent to different sidewalls of the spacer layer. The chip package of claim 1, wherein an area ratio of the spacer layer to the first substrate is less than 50%. The chip package of claim 1, wherein the spacer layer further comprises at least one second hole exposing a portion of the first substrate and the second substrate, and not the first hole and at least A zigzag channel is connected. The chip package of claim 6, wherein the spacer layer includes a pair of second holes as alignment marks. The chip package of claim 1, wherein the first substrate has a conductive pad adjacent to the surface and does not overlap the at least one meandering channel from a top view. The chip package of claim 8, wherein the first substrate has a second opening extending from the first substrate relative to a surface of the surface, and the conductive pad is exposed, and wherein The chip package further includes: an insulating layer disposed on the other surface and extending into the second opening; a redistribution layer disposed on the insulating layer and contacting the exposed conductive pad; a passivation a protective layer disposed on the redistribution layer and exposing the portion of the redistribution layer on the other surface; and a conductive structure disposed on the exposed redistribution layer. The chip package of claim 1, wherein the sensing device comprises a temperature sensing element, a humidity sensing element or a combination thereof. A method of manufacturing a chip package, comprising: providing a first substrate and a second substrate, wherein a surface of the first substrate has a sensing device; bonding the second substrate to the first through a spacer layer Forming a first opening in the second substrate, and aligning with the sensing device; wherein the spacer layer comprises: a first hole communicating with the first opening to expose the Sensing device And at least one meandering channel exposing a portion of the first substrate and the second substrate and not communicating with the first hole, wherein the at least one meandering channel has at least one open end, inward from a side wall of the spacer layer extend. The method of manufacturing a chip package according to claim 11, wherein the path of the at least one meandering channel comprises a three-pronged path, a zigzag path or a combination thereof. The method of manufacturing a chip package according to claim 11, wherein the at least one meandering channel comprises a vertical corner, a rounded corner, or a combination thereof. The method of manufacturing a chip package according to claim 11, wherein the at least one meandering channel has a plurality of open ends adjacent to different side walls of the spacer layer. The method of manufacturing a chip package according to claim 11, wherein an area ratio of the spacer layer to the first substrate is less than 50%. The method of manufacturing the chip package of claim 11, wherein the spacer layer further comprises at least one second hole exposing a portion of the first substrate and the second substrate, and not the first The hole is connected to at least one zigzag passage. The method of manufacturing a chip package according to claim 16, wherein the spacer layer includes a pair of second holes as alignment marks. The method of manufacturing a chip package according to claim 11, wherein the first substrate has a conductive pad adjacent to the surface and does not overlap the at least one meandering channel from a top view. . The method of manufacturing the chip package of claim 18, further comprising: forming a second opening in the first substrate extending from the first substrate relative to a surface of the surface, and Exposing the conductive pad; forming an insulating layer on the other surface and extending into the second opening; forming a redistribution layer on the insulating layer and contacting the exposed conductive pad; in the redistribution layer Forming a passivation protective layer thereon and exposing a portion of the redistribution layer on the other surface; and forming a conductive structure on the exposed redistribution layer. The method of manufacturing a chip package according to claim 11, wherein the sensing device comprises a temperature sensing element, a humidity sensing element or a combination thereof.