TWI542146B - A Method for Eliminating Zero Crossing Point Noise in Digital Power Supply - Google Patents

A Method for Eliminating Zero Crossing Point Noise in Digital Power Supply Download PDF

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TWI542146B
TWI542146B TW104127111A TW104127111A TWI542146B TW I542146 B TWI542146 B TW I542146B TW 104127111 A TW104127111 A TW 104127111A TW 104127111 A TW104127111 A TW 104127111A TW I542146 B TWI542146 B TW I542146B
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signal
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zero
judgment
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TW201709673A (en
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Shun-Zhong Wang
Yi-Hua Liu
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Description

一種用於數位電源之零交越點雜訊消除方法 Zero crossover point noise cancellation method for digital power supply

本發明係有關於用於數位電源之雜訊消除方法,特別是關於一種用於數位電源之零交越點雜訊消除方法。 The present invention relates to a noise cancellation method for a digital power supply, and more particularly to a zero crossover point noise cancellation method for a digital power supply.

能源開發及應用一直伴隨著人類文明的成長,但由於人口增長對於能源的需求也同步增加,因此如何產生新能源及提高能源應用效率就成為近代能源的重要議題。現行的輸配電網路大都使用50Hz或60Hz的交流電形態,而再生能源電能轉換的裝置大都由電力電子裝置進行轉換,而電力電子裝置為了獲得高的轉換效率,因此大都使用切換式(switching mode)技術進行電能轉換,此形態轉換器易因電力開關元件及電路的寄生電感、電容產生電壓及電流突波進而干擾電路。交換式電源轉換器(switching mode power converter)為了與輸配電系統聯結因此通常使用高壓的模式操作,開關元件操作的過程中,因為線路寄生電感、電容產生許多不必要的振盪,同時也產生了相當數量的雜訊分散於線路上。DSP(digital signal processor;數位訊號處理器)或MCU(microcontroller unit;微控制器)為獲得高速的運作效率,操作電壓由5V、3.3V、1.8V一路往下降,雖然獲得了更高的運轉速度,但由於操作電壓的下降,對雜訊的抗拒能力也就同步的下降。數位式電源系統,所有的控制輸出均由DSP或MCU對外界訊號的偵測(Sensing)再經過內部的 計算而產生。倘若偵測的訊號是錯誤的,相對產生的控制輸出也會是錯誤的。如何在一連串的動作訊號中將正確訊號與錯誤訊號分離出來,使系統能正確且穩定的運作也就相當重要。 Energy development and application have been accompanied by the growth of human civilization. However, due to the increasing demand for energy from population growth, how to generate new energy and improve energy application efficiency has become an important issue in modern energy. Most of the current transmission and distribution networks use the 50 Hz or 60 Hz AC mode, and most of the devices for regenerative energy conversion are converted by power electronic devices. In order to obtain high conversion efficiency, power electronic devices mostly use switching mode. The technology performs power conversion, and the form converter is susceptible to voltage and current surges due to parasitic inductances and capacitances of the power switching elements and circuits, thereby interfering with the circuit. In order to connect with the transmission and distribution system, the switching mode power converter usually uses high-voltage mode operation. During the operation of the switching element, because the line parasitic inductance and capacitance generate many unnecessary oscillations, it also produces considerable The amount of noise is scattered on the line. DSP (digital signal processor) or MCU (microcontroller unit; microcontroller) for high-speed operation efficiency, operating voltage is reduced by 5V, 3.3V, 1.8V all the way, although higher operating speed However, due to the drop in operating voltage, the resistance to noise is also reduced. Digital power system, all control outputs are detected by the DSP or MCU for external signals (Sensing) and then internal Generated by calculation. If the detected signal is wrong, the resulting control output will be wrong. How to separate the correct signal from the error signal in a series of motion signals, so that the system can operate correctly and stably is very important.

為解決前述的問題,吾人亟需一新穎的零交越點雜訊消除方法。 In order to solve the aforementioned problems, we need a novel zero-crossing point noise cancellation method.

數位式電源系統,所有的控制輸出均由DSP或MCU對外界訊號的偵測(Sensing)再經過內部的計算而產生。倘若偵測的訊號是錯誤的,相對產生的控制命令也會是錯誤的。如何在一連串偵測到的訊號中將正確訊號與錯誤訊號分離出來,使系統能正確且穩定的運作,是亟待解決的問題。本發明的目的即為解決該問題。 In the digital power system, all control outputs are generated by the DSP or MCU's external signal detection (Sensing) and then internal calculations. If the detected signal is wrong, the resulting control command will be wrong. How to separate the correct signal from the error signal in a series of detected signals, so that the system can operate correctly and stably is an urgent problem to be solved. The object of the present invention is to solve this problem.

為達前述目的,一種用於數位電源之零交越點雜訊消除方法乃被提出,其係以複數個零點訊號之對應時間值為資料來源,其中,所述複數個零點訊號包含複數個真實零點訊號,且任二相鄰的所述真實零點訊號間之時間差係介於一最小週期和一最大週期之間,該方法包括以下步驟:第一步驟:選定所述複數個零點訊號之第一個零點訊號之時點為一起始參考點;第二步驟:判斷在所述複數個零點訊號中是否有在該起始參考點之後且和該起始參考點之時間差介於所述最小週期和所述最大週期之間的至少一可能合格訊號,若判斷結果為否,則將位於該起始參考點的訊號定義為雜訊並將該起始參考點移至最接近該參考點之一所述零點訊號的時點,並重新執行所述第二步驟;若判斷結果為是,則將該起始參考點定 義為合格訊號點並將所述至少一可能合格訊號之時點設為至少一後續參考點;第三步驟:依序取所述至少一後續參考點中之一時點作為所述起始參考點並據以執行所述第二步驟;第四步驟:重複執行所述第三步驟複數次並產生至少一組時序資料,其中各組所述時序資料係各由複數個所述合格訊號點組成;以及第五步驟:對所述至少一組時序資料之各組資料分別執行一週期變動量累加計算以產生至少一週期變動量累計值,並以所述至少一週期變動量累計值中之最小者所對應的一組所述時序資料作為所述複數個真實零點訊號的時序資料。 To achieve the foregoing objective, a zero-crossing point noise cancellation method for a digital power supply is proposed, which uses a corresponding time value of a plurality of zero-point signals as a data source, wherein the plurality of zero-point signals include a plurality of real numbers. a zero point signal, and the time difference between the two adjacent real zero signals is between a minimum period and a maximum period, the method comprising the following steps: the first step: selecting the first of the plurality of zero signals The time point of the zero signal is a starting reference point; the second step: determining whether there is a time difference between the starting zero point and the starting reference point in the plurality of zero signals is between the minimum period and the Determining at least one possible qualified signal between the maximum periods. If the determination result is no, the signal at the initial reference point is defined as noise and the starting reference point is moved to the one closest to the reference point. The time point of the zero signal, and re-execute the second step; if the judgment result is yes, the starting reference point is determined Determining a qualified signal point and setting a time point of the at least one possible qualified signal as at least one subsequent reference point; and a third step: sequentially taking one of the at least one subsequent reference point as the starting reference point Performing the second step; the fourth step: repeatedly performing the third step and generating at least one set of time series data, wherein each of the sets of the time series data is composed of a plurality of the qualified signal points; a fifth step: performing a one-cycle variation amount accumulation calculation on each group of data of the at least one set of timing data to generate at least one period variation amount cumulative value, and using the smallest one of the at least one period variation amount cumulative value A corresponding set of the timing data is used as timing information of the plurality of real zero signals.

為使 貴審查委員能進一步瞭解本發明之結構、特徵及其目的,茲附以圖式及較佳具體實施例之詳細說明如后。 The detailed description of the drawings and the preferred embodiments are set forth in the accompanying drawings.

圖1繪示本發明之市電零點訊號除錯方法的基本原理。 FIG. 1 is a schematic diagram showing the basic principle of the method for debugging the mains zero signal of the present invention.

圖2a-2d繪示兩個零點訊號的二進制排列組合。 Figures 2a-2d illustrate the binary arrangement of two zero signals.

圖3a-3d繪示起始點為0之三個相鄰零點訊號的二進制排列組合。 Figures 3a-3d illustrate a binary permutation combination of three adjacent zero signals with a starting point of zero.

圖4a-4d繪示起始點為1之三個相鄰零點訊號的二進制排列組合。 4a-4d illustrate a binary permutation combination of three adjacent zero signals with a starting point of one.

圖5為所有訊號均為真實的零點訊號之示意圖。 Figure 5 is a schematic diagram of all the zero signals that are true.

圖6為所有零點訊號均為雜訊之示意圖。 Figure 6 is a schematic diagram of all zero signals being noise.

圖7為真實零點訊號及雜訊交互排列之示意圖。 FIG. 7 is a schematic diagram of real zero signal and noise interaction arrangement.

圖8為第一訊號為真實訊號的訊號判斷示意圖。 FIG. 8 is a schematic diagram of signal determination in which the first signal is a real signal.

圖9為第一訊號為真實訊號且雜訊分布於條件判斷區內之示意圖。 FIG. 9 is a schematic diagram of the first signal being a real signal and the noise being distributed in the condition determination area.

圖10-11為本發明在判斷區內增加訊號複驗功能之示意圖。 10-11 are schematic diagrams showing the function of adding a signal re-inspection in the judgment area according to the present invention.

圖12-14為以本發明之方法處理判斷區內出現兩個以上雜訊問題之示意圖。 12-14 are schematic diagrams showing the occurrence of more than two noise problems in the determination zone by the method of the present invention.

圖15a-15d為以本發明之方法處理多個判斷區間均出現兩個以上訊號之示意圖。 15a-15d are schematic diagrams showing the occurrence of more than two signals in a plurality of judgment intervals by the method of the present invention.

圖16-19為以本發明之方法處理第一個零點訊號為雜訊之序列訊號之示意圖。 16-19 are schematic diagrams showing the processing of the first zero signal as a sequence signal of noise by the method of the present invention.

圖20-21繪示本發明對第一個零點雜訊落於條件判斷區內且第二個零點雜訊也落於條件判斷區內之處理情況。 20-21 illustrate the processing of the first zero point noise in the conditional decision area and the second zero point noise also falls within the conditional decision area.

圖22繪示本發明一實施例之流程圖。 FIG. 22 is a flow chart of an embodiment of the present invention.

圖23為未經處理所得頻率值與經本發明方法處理所得頻率值,經計算相對於模擬市電頻率的誤差百分比對照圖。 Fig. 23 is a graph showing the error percentage of the unprocessed frequency value and the frequency value obtained by the method of the present invention, calculated relative to the simulated mains frequency.

圖24為經傳統週期比對方式處理所得頻率值與經本發明所提方法處理所得之頻率值經計算相對於模擬市電頻率的誤差百分比對照圖。 Figure 24 is a graph comparing the error percentages of the frequency values processed by the conventional period comparison method and the frequency values obtained by the method of the present invention with respect to the simulated mains frequency.

本發明係以市電電源系統的頻率不易變動的特性作為將市電的真實零點訊號與雜訊分離的判斷根據,藉以消除雜訊所造成的頻率誤判。 The invention adopts the characteristic that the frequency of the commercial power supply system is not easily changed as the judgment basis for separating the true zero signal of the commercial power from the noise, thereby eliminating the frequency misjudgment caused by the noise.

範例說明:圖1繪示本發明之市電零點訊號除錯方法的基本原理。 Example Description: FIG. 1 illustrates the basic principle of the method for debugging the commercial zero point signal of the present invention.

n號圓圈代表硬體電路所擷取到的第n個零點訊號,其對應有 一計數值,其中,1號圓圈代表第1個零點訊號,2號圓圈代表第2個零點訊號,3號圓圈代表第3個零點訊號,4號圓圈代表第4個零點訊號等等。另外,若圈內留空(除了數字以外),表示該次零點訊號為正確的零點訊號;若圈內填滿一灰色,表示該次零點訊號為錯誤的零點訊號。 The circle n represents the nth zero point signal captured by the hardware circuit, and the corresponding A count value, where circle 1 represents the first zero signal, circle 2 represents the second zero signal, circle 3 represents the third zero signal, circle 4 represents the fourth zero signal, and so on. In addition, if the circle is left blank (except for the number), it means that the zero signal is the correct zero signal; if the circle is filled with a gray, the zero signal is the wrong zero signal.

圖中的箭頭曲線表示以一正確的零點訊號為參考點,和隨後 之一零點訊號產生一計數值差值,或時間差;步驟n F代表第n次計數值差值係一不合格的差值,也就是說該次計數值差值大於允許的最大週期或小於允許的最小週期,而步驟n Y則代表第n次計數值差值係一合格的差值,也就是說該次計數值差值小於允許的最大週期且大於允許的最小週期。 The arrow curve in the figure indicates that a correct zero signal is used as a reference point, and subsequently One of the zero signals generates a difference in count value, or a time difference; step n F represents a difference in the difference of the nth count value, that is, the difference of the count value is greater than the maximum period allowed or less than The minimum period allowed, and the step n Y represents that the difference of the nth count value is a qualified difference, that is, the difference value of the count value is less than the maximum period allowed and greater than the minimum period allowed.

圖中虛線的範圍表示允許的時間差值,其範圍為Max Cycle-Min Cycle(最大週期-最小週期)。本發明先以第1個零點訊號為基本參考點。由於第2個零點訊號和第1個零點訊號間的計數值差值小於最小週期,故第2個零點訊號為不合格的零點訊號,其判斷結果以步驟1 F代表,且仍以第1個零點訊號為基本參考點。接著,由於第3個零點訊號和第1個零點訊號間的計數值差值小於最大週期且大於最小週期,故第3個零點訊號為合格的零點訊號,其判斷結果以步驟2 Y代表。接著,改以第3個零點訊號為基本參考點。由於第4個零點訊號和第3個零點訊號間的計數值差值小於最大週期且大於最小週期,故第4個零點訊號為合格的零點訊號,其判斷結果以步驟3 Y代表。亦即,在計數值差值小於最大週期且大於最小週期時,基本參考點便會移動到此次判斷時的相對變動點,再進行下一次的差值判斷。差值判斷就如此重複往下判斷直至資料結束或區間連續成立次數達到設定值,最終再進行誤差判斷,以確定最佳的訊號點並達到消除錯誤訊號 的目的。 The range of dashed lines in the figure indicates the allowed time difference, which is in the range Max. Cycle-Min Cycle (maximum cycle - minimum cycle). The invention first uses the first zero point signal as a basic reference point. Since the difference between the count value of the second zero point signal and the first zero point signal is less than the minimum period, the second zero point signal is an unqualified zero point signal, and the judgment result is represented by step 1 F, and still is the first one. The zero signal is the basic reference point. Then, since the difference between the count value of the third zero point signal and the first zero point signal is less than the maximum period and greater than the minimum period, the third zero point signal is a qualified zero point signal, and the judgment result is represented by step 2 Y. Then, the third zero point signal is used as the basic reference point. Since the difference between the count value of the fourth zero point signal and the third zero point signal is less than the maximum period and greater than the minimum period, the fourth zero point signal is a qualified zero point signal, and the judgment result is represented by step 3 Y. That is, when the difference between the count values is less than the maximum period and greater than the minimum period, the basic reference point moves to the relative change point at the time of the judgment, and the next difference judgment is performed. The difference judgment is repeated until the end of the data or the interval is continuously established to reach the set value, and finally the error judgment is performed to determine the optimal signal point and eliminate the error signal. the goal of.

零點訊號形態分析:不論是真實的零點訊號或是雜訊所產生的訊號,於時間軸上都是以排列方式循序進入DSP或MCU的取樣電路。但訊號排列的不同就會影響判斷方式,因此需逐一加以整理分類。零點訊號可分為兩種,一為真實的零點訊號,一為雜訊所產生的訊號,而且又以時間軸進行排列。此種排列形態可用二進制的方式表示,例如將正確的訊號定義為0,錯誤的訊號定義為1。圖2a-2d繪示兩個零點訊號的二進制排列組合,其中,(a)訊號為00、(b)訊號為01、(c)訊號為10、(d)訊號為11。圖3a-3d繪示起始點為0之三個相鄰零點訊號的二進制排列組合,其中,(a)訊號為000、(b)訊號為001、(c)訊號為010、(d)訊號為011。 Zero-point signal morphological analysis: Whether it is a real zero-point signal or a signal generated by noise, it is a sampling circuit that sequentially enters the DSP or MCU in a sequence on the time axis. However, the difference in the arrangement of the signals will affect the way of judging, so it is necessary to sort them one by one. The zero signal can be divided into two types, one is the real zero signal, the other is the signal generated by the noise, and is arranged in the time axis. This arrangement can be expressed in binary form, for example, the correct signal is defined as 0, and the wrong signal is defined as 1. 2a-2d illustrate a binary arrangement of two zero signals, wherein (a) the signal is 00, the (b) signal is 01, the (c) signal is 10, and the (d) signal is 11. 3a-3d illustrate a binary arrangement of three adjacent zero signals with a starting point of 0, wherein (a) the signal is 000, the (b) signal is 001, the (c) signal is 010, and the signal is (d). Is 011.

圖3a-3d為起始點為0的三個相鄰零點訊號排列方式,若以起始點為1,依二進制的排列規則,同樣的會再有四種排列方式。圖4a-4d繪示起始點為1之三個相鄰零點訊號的二進制排列組合,其中,(a)訊號為100、(b)訊號為101、(c)訊號為110、(d)訊號為111。 Figures 3a-3d show the arrangement of three adjacent zero signals with a starting point of 0. If the starting point is 1, according to the binary arrangement rule, there will be four more arrangements. 4a-4d illustrate a binary arrangement of three adjacent zero signals with a starting point of 1, wherein (a) the signal is 100, (b) the signal is 101, (c) the signal is 110, and the signal is (d). Is 111.

由圖4a-4d中可看出,正確的零點訊號將會正確的處於週期判斷區內,但錯誤的零點訊號就不一定會處於哪一個區段間,因此在後續的訊號處理討論中,將會針對錯誤零點訊號是否處於週期判斷區內分開加以討論。圖4a-4d為起始零點訊號即為錯誤零點訊號的排列方式。由圖中可看出,錯誤零點訊號與正確零點訊號之排列仍然是符合二進制的排列方式。若依二進制的方式進行四點訊號排列,將會產生十六種排列的方式,但在這些排列的形態中,又可將其分類為三類,而不需分類為十六種,如 此便可有效的對訊號進行分析判斷。 As can be seen from Figures 4a-4d, the correct zero signal will be correctly in the period of the period judgment, but the wrong zero signal will not necessarily be in which section, so in the subsequent signal processing discussion, It will be discussed separately whether the error zero signal is in the period of judgment. Figures 4a-4d show the starting zero signal as the arrangement of the error zero signal. As can be seen from the figure, the arrangement of the error zero signal and the correct zero signal is still in binary arrangement. If the four-point signal arrangement is performed in binary mode, there will be 16 ways of arrangement, but in the form of these arrangements, it can be classified into three categories without being classified into sixteen types, such as This can effectively analyze and judge the signal.

圖5為所有訊號均為真實的零點訊號之示意圖。在此狀況下 無須進行訊號除錯,只需連續對零點訊號判斷若干次數,以獲得較佳的平均值供系統使用零點訊號。 Figure 5 is a schematic diagram of all the zero signals that are true. In this situation There is no need to perform signal debugging. It is only necessary to continuously judge the zero signal several times to obtain a better average value for the system to use the zero signal.

圖6為所有零點訊號均為雜訊所產生的訊號之示意圖。由於 真實的零點訊號為週期訊號,因此在一定的週期時間內必定會出現真實的零點訊號。圖6另外可看出,若雜訊所產生的零點訊號都集中於兩個真實的零點訊號週期內,代表系統擁有極高的雜訊,即使能正確的消除錯誤的零點訊號,在系統的其他電路同時也必須承受如此高的雜訊,系統的動作將極不穩定,此狀況並不是單一因素所造成,若要使用本發明所討論的方式處理零點訊號,將造成相當大的運算時間及記憶體資源的消耗,此屬於多因素問題,在此乃不進行進一步的討論。 Figure 6 is a schematic diagram of signals generated by all zero signals being noise. due to The true zero signal is a periodic signal, so a true zero signal will appear in a certain period of time. In Figure 6, it can be seen that if the zero signal generated by the noise is concentrated in two real zero signal periods, the system has extremely high noise, even if the wrong zero signal can be correctly eliminated, in the system other The circuit must also withstand such high noise, and the operation of the system will be extremely unstable. This situation is not caused by a single factor. If the zero signal is processed in the manner discussed in the present invention, considerable computation time and memory will be caused. The consumption of physical resources, which is a multi-factor problem, is not discussed further here.

圖5及圖6若以二進制方式討論,於順序的排列上,分別處於 排列的最前端及最後端,分屬於較極端的例子。圖5為全部為真實的零點訊號,這是電路設計想要達成的狀況,但由二進制排列分佈的狀況可知,這是不易發生的,正確的零點訊號與異常的零點訊號都會出現才是一般較常出現的狀況。 Figure 5 and Figure 6 are discussed in binary mode, in the order of the arrangement, respectively The front end and the last end of the arrangement are divided into more extreme examples. Figure 5 shows all the real zero signals. This is the situation that the circuit design wants to achieve. However, it can be seen that the binary distribution is not easy to occur. The correct zero signal and the abnormal zero signal will appear. A situation that often occurs.

圖7為真實零點訊號及雜訊交互排列之示意圖。若以真實的 週期訊號為分界的依據,可看出異常雜訊分布於真實零點訊號之間,單一區間內可能分佈一個或數個異常雜訊。但若是異常雜訊過多,就會產生如同圖6所示之現象,而不在本發明討論之列。 FIG. 7 is a schematic diagram of real zero signal and noise interaction arrangement. If true The periodic signal is the basis of the demarcation. It can be seen that the abnormal noise is distributed between the real zero signals, and one or several abnormal noises may be distributed in a single interval. However, if there are too many abnormal noises, a phenomenon like that shown in Fig. 6 will occur, and it will not be discussed in the present invention.

真實零點訊號判斷方式: 零點訊號的判斷方式仍然沿用二進制的方式進行分類。本發 明先以一零點訊號為參考基準點,再以此點出發對後續的零點訊號進行判斷。但在取用第一個參考基準點時,並不一定會取到真實的零點訊號,因此就以取用第一參考基準點時為真實或異常雜訊來進行分類討論。圖8為第一訊號為真實訊號的訊號判斷示意圖。由圖8中的判斷標示中可知,由於其係先以真實零點訊號1為參考基準點,故可刪除雜訊並正確找出後續的真實零點訊號。如此連續進行判斷直到判斷資料結束或可以得到連續符合條件判斷X次(X為由程式使用者訂立之正整數,次數越多準確率愈高),若得到符合條件判斷X次,表示於訊號資料中找出一組可用的資料,再根據此資料進行週期平均計算。 True zero signal judgment method: The way the zero signal is judged is still classified in binary mode. This hair First, use the zero-point signal as the reference point, and then use this point to judge the subsequent zero-point signal. However, when the first reference datum point is taken, the real zero signal is not necessarily obtained, so the classification or discussion is performed when the first reference datum point is taken as real or abnormal noise. FIG. 8 is a schematic diagram of signal determination in which the first signal is a real signal. It can be seen from the judgment mark in FIG. 8 that since the real zero signal 1 is used as the reference point, the noise can be deleted and the subsequent true zero signal can be correctly found. In this way, the judgment is continued until the data is judged or the continuous conditional judgment can be obtained X times (X is a positive integer made by the program user, and the higher the number of times, the higher the accuracy rate). If the condition is judged X times, it is indicated in the signal data. Find a set of available data, and then calculate the cycle average based on this data.

雜訊分佈於條件判斷區內問題處理:於圖8中所有的異常零點訊號均未落於條件判斷區內,實際零點訊號的狀況並不會如此理想,事實上,異常零點訊號有相當大的機會訊號會落於條件判斷區內。圖9為第一訊號為真實訊號且雜訊分布於條件判斷區內之示意圖。於圖9中可看出零點訊號3正好落於條件判斷區內,若依照前述的判斷方式,將會出現錯誤判斷。如圖9中的步驟3,圖中零點訊號4為真實訊號,但由於零點訊號3的誤判,將連帶著將零點訊號4認為是錯誤訊號,因此需增加判斷區內訊號複驗的功能,以處理此一問題。 The noise is distributed in the conditional judgment area. All the abnormal zero signals in Figure 8 do not fall within the conditional judgment area. The actual zero signal condition is not so ideal. In fact, the abnormal zero signal has considerable size. The opportunity signal will fall within the conditional judgment area. FIG. 9 is a schematic diagram of the first signal being a real signal and the noise being distributed in the condition determination area. It can be seen in Fig. 9 that the zero signal 3 falls within the conditional judgment area, and if the judgment method is as described above, an erroneous judgment will occur. As shown in step 3 in Figure 9, the zero signal 4 in the figure is a real signal. However, due to the misjudgment of the zero signal 3, the zero signal 4 will be considered as an error signal. Therefore, it is necessary to increase the function of re-inspection in the judgment area. Handle this problem.

圖10-11為本發明在判斷區內增加訊號複驗功能之示意圖。在圖10中,當流程進行到步驟2時,雖然判斷式是符合條件的,此時不會立即將參考基準點變由點1移動到點3,而是再加入步驟3的測試,若測試是符合條件的,則將步驟3當時的測試結果存放於一測試結果暫存資料矩陣中, 再將參考基準點變由點1移動到點3,繼續後續的判斷直到判斷資料結束或可以得到連續符合條件判斷X次,X為正整數。 10-11 are schematic diagrams showing the function of adding a signal re-inspection in the judgment area according to the present invention. In FIG. 10, when the flow proceeds to step 2, although the judgment formula is qualified, the reference datum point is not immediately moved from point 1 to point 3, but the test of step 3 is added again, if the test is performed. If the condition is met, the test result at the time of step 3 is stored in a temporary data matrix of the test result. Then, the reference datum point is changed from point 1 to point 3, and the subsequent judgment is continued until the end of the judgment data or the continuous conditional judgment can be obtained X times, and X is a positive integer.

當流程執行到圖10的步驟a時,便會對所述測試結果暫存資 料矩陣內的資料進行判斷,若資料筆數不為零,則表示出現了兩個以上的零點訊號(含兩個零點訊號)位在同一個判斷區內的狀況。此時,便將所述測試條件暫存資料矩陣中的資料讀出,並按照存放的次序回存到相關的訊號判斷指標,再次進行判斷。如圖11步驟a+1所示,可看出此時本發明的流程並不會對點2、點3進行判斷,而是直接進行點4的判斷,如此便可以消除雜訊分布於條件判斷區內的問題。 When the process proceeds to step a of FIG. 10, the test result is temporarily saved. The data in the material matrix is judged. If the number of data is not zero, it indicates that two or more zero signals (including two zero signals) are in the same judgment area. At this time, the data in the test condition temporary storage data matrix is read out, and is returned to the relevant signal judgment index according to the order of storage, and the judgment is performed again. As shown in step a+1 of FIG. 11, it can be seen that the flow of the present invention does not judge the point 2 and the point 3 at this time, but directly judges the point 4, so that the noise distribution can be eliminated in the condition judgment. Problems in the area.

圖12-14為以本發明之方法處理判斷區內出現兩個以上雜訊 問題之示意圖。在圖12中,當執行到資料複驗功能時,如圖12的步驟3,會將當時訊號的處理指標及相關參數進行儲存。當此次序列資料判斷完成後,再重新將儲存的訊號處理指標及相關參數回存到相對的工作暫存器中,此時就如同圖13的步驟a+1的狀態,但與圖11的步驟a+1不同的是,圖13的步驟a+2是符合判斷區內訊號複驗條件的,因此程式執行到資料複驗功能,就如同圖13的步驟a+2,會再次將當時訊號的處理指標及相關參數進行儲存。 Figure 12-14 shows the presence of more than two noises in the judgment area by the method of the present invention. Schematic diagram of the problem. In FIG. 12, when the data re-inspection function is executed, as shown in step 3 of FIG. 12, the processing index of the current signal and related parameters are stored. After the sequence data is judged, the stored signal processing index and related parameters are restored to the relative working register, which is the same as the state of step a+1 of FIG. 13 but with FIG. Step a+1 is different. Step a+2 of FIG. 13 is in compliance with the signal re-inspection condition in the judgment area, so the program executes the data re-inspection function, just like step a+2 of FIG. 13, the current signal is again The processing indicators and related parameters are stored.

當此次序列資料判斷完成時,如圖13的步驟b,本發明的流 程會再次對所述測試條件暫存資料矩陣內的資料進行判斷,由於資料筆數不為零,故會重新將先前儲存的訊號處理指標及相關參數回存到相對的工作暫存器中,如圖14步驟b+1的執行步驟。依此判定方式,不論判斷區內訊號出現多少個,均可使用此方法逐一進行判斷而不會流失任何一個訊號 的判斷。 When the determination of the sequence data is completed, as shown in step b of FIG. 13, the flow of the present invention Cheng will once again judge the data in the test condition temporary data matrix. Since the number of data is not zero, the previously stored signal processing indicators and related parameters will be restored to the relative working register. Figure 14 shows the execution steps of step b+1. According to this determination method, no matter how many signals appear in the judgment area, this method can be used to judge one by one without losing any signal. Judgment.

雖然本發明的流程對每一符合條件判斷序列的資料都有進 行判斷,但何者序列為正確序列就必須加以討論。由圖9及圖12的示意圖中可看出,圖9的點3及圖12的點3、點5均不在判斷區的中心區域,這表示了圖9步驟2及圖12步驟2、圖14步驟b+1的判斷值雖然符合判斷條件,但必定遠小於或遠大於訊號週期值。因此便可利用此一特性,對每筆符合條件判斷的資料序列進行一最小變動量判斷程序:首先計算出每一訊號點與點的差距值;再計算每一次差距值的變化量;將此變化量絕對值累積計算;變化量最小的資料序列組,即為最有可能的真實訊號序列。依此判斷程序,即使有雜訊混入,對系統整體判斷的影響也是有限的,因其變化量必定有限,若同樣的在連續的兩組訊號判斷區間都出現兩個或兩個以上的訊號時,同樣使用所述的訊號複驗功能,依然可以正確的處理訊號,只是處理指標及相關參數儲存陣列必須多一組,以記憶複驗的次數及相關資料的位置。圖15a-15d為以本發明之方法處理多個判斷區間均出現兩個以上訊號之示意圖,其中,(a)第一次序列資料判斷順序、(b)第二次序列資料判斷順序、(c)第三次序列資料判斷順序、(d)第四次序列資料判斷順序。 Although the flow of the present invention has a Line judgment, but which sequence is the correct sequence must be discussed. As can be seen from the schematic diagrams of FIGS. 9 and 12, point 3 of FIG. 9 and point 3 and point 5 of FIG. 12 are not in the central area of the determination area, which indicates step 2 of FIG. 9 and step 2 and FIG. 14 of FIG. Although the judgment value of step b+1 meets the judgment condition, it must be much smaller or farther than the signal period value. Therefore, using this feature, a minimum variation determination procedure can be performed for each data sequence that meets the conditional judgment: first, the difference value between each signal point and the point is calculated; and the amount of change of each difference value is calculated; The absolute value of the change is cumulatively calculated; the data sequence group with the smallest change is the most likely real signal sequence. According to this judgment procedure, even if there is noise mixing, the impact on the overall judgment of the system is limited, because the amount of change must be limited, if two or more signals appear in the continuous two sets of signal judgment intervals. Similarly, using the signal re-inspection function, the signal can still be processed correctly, but only one set of processing indicators and related parameter storage arrays must be used to memorize the number of re-inspections and the location of related data. 15a-15d are schematic diagrams showing the occurrence of two or more signals in a plurality of judgment intervals by the method of the present invention, wherein (a) the first sequence data judgment order, (b) the second sequence data judgment order, (c) The third sequence data judgment order, and (d) the fourth sequence data judgment order.

在圖15a-15d之點3及點5的判斷區間內,均出現兩個訊號符合 判斷的條件,不論先判斷的訊號為異常或後判斷的訊號為異常,訊號判斷的順序均是相同的,最終仍會利用最小週期變動量的方式進行判斷,以取出最穩定的訊號序列。圖15a的步驟3及步驟6均為執行判斷區內訊號複驗功能,此兩個步驟的判斷結果均是符合限制的,因此先後會被存放到處理指標及相關參數儲存陣列中,在此情況下儲存陣列儲存了兩筆資料,同樣的 於本次序列判斷完畢時,便會對儲存陣列進行檢查,查看內部是否有資料儲存於內,若有則依後進先出的方式讀取儲存陣列的資料,再回存到處理指標及相關參數,再次進行如圖15b之序列資料判斷,如此依序進行序列資料判斷直到結束。 In the judgment interval of points 3 and 5 of Figures 15a-15d, two signals appear to match The condition for judging, whether the signal judged first is abnormal or the signal after judging is abnormal, the order of signal judgment is the same, and finally the judgment is still made by the method of minimum period variation to take out the most stable signal sequence. Steps 3 and 6 of Figure 15a are both performing the signal re-inspection function in the judgment area. The judgment results of the two steps are all in compliance with the limit, so they are stored in the processing index and the related parameter storage array. The next storage array stores two pieces of data, the same After the sequence is judged, the storage array is checked to see if any data is stored inside. If there is, the data of the storage array is read in a last-in, first-out manner, and then returned to the processing index and related parameters. Then, the sequence data judgment as shown in Fig. 15b is performed again, so that the sequence data judgment is sequentially performed until the end.

當圖15b的資料判斷序列完成時,因先前已讀取一筆儲存陣 列的資料,因此內部還剩一筆陣列資料,故再度讀取儲存陣列的資料,再回存到處理指標及相關參數,以及再次進行序列資料判斷如圖15c,此時點1為參考基準點,點4為相對變動訊號點,當參考基準點往點4移動時,因步驟b+2同樣符合判斷條件因此會再次進行判斷區內訊號複驗功能,如圖15c的步驟b+3。由於步驟b+3的判斷是符合條件的,故乃對此次複驗的狀況進行儲存,以待此次序列判斷結束後再回存處理指標及相關參數,並再次進行序列判斷,如圖15d。由圖15a到15d可看出,若訊號重複出現在判斷區內愈多,重複執行資料序列判斷的次數就愈多,雖然如此,即使訊號異常數再多,仍會逐一被判斷到,只是執行的次數較多。因此只要再配合先前所提的最小週期變動量的方式,仍然可有效的找出最小變動量的序列資料,以供給頻率計算或零點判斷程式使用,進而達到訊號除錯及穩定的功能。 When the data judgment sequence of Fig. 15b is completed, a storage array has been read previously. The data of the column, so there is still an array of data left inside, so the data of the storage array is read again, and then the processing index and related parameters are restored, and the sequence data is judged again as shown in Fig. 15c. At this time, point 1 is the reference datum point. 4 is a relative change signal point. When the reference reference point moves to point 4, since step b+2 also meets the judgment condition, the signal re-inspection function in the judgment area is performed again, as shown in step b+3 of Fig. 15c. Since the judgment of step b+3 is in accordance with the condition, the condition of the re-inspection is stored, and after the end of the sequence judgment, the processing index and related parameters are restored, and the sequence judgment is performed again, as shown in Fig. 15d. . It can be seen from Fig. 15a to 15d that if there are more repeated signals in the judgment area, the more times the data sequence is repeatedly executed, the more the number of signal abnormalities will be judged one by one, but only executed. More times. Therefore, as long as the minimum period variation amount mentioned above is used, the sequence data of the minimum variation can be effectively found to be used for the frequency calculation or the zero point judgment program, thereby achieving the function of signal debugging and stabilization.

第一個零點訊號為雜訊之序列訊號處理:圖16-19為以本發明之方法處理第一個零點訊號為雜訊之序列訊號之示意圖。如圖16所示,本發明先以第一個零點訊號為參考基準點,再以此點出發對後續的零點訊號進行判斷。 The first zero signal is the sequence signal processing of the noise: FIG. 16-19 is a schematic diagram of the sequence signal of the first zero signal being the noise processed by the method of the present invention. As shown in FIG. 16, the present invention first uses the first zero point signal as a reference point, and then determines the subsequent zero point signal from this point.

同樣的,在此仍然以二進制方式進行序列訊號排列,並針對 序列訊號不同的排列進行討論。在圖16中,零點訊號1為雜訊,但其後的零點訊號均為真實的零點訊號。步驟1依本發明之判斷是不合格的,不合格的原因為點1、點2兩點的間距小於最小的間距限制,因此繼續往下一點進行判斷。步驟2依本發明之判斷是不合格的,不符合的原因為點1、點3兩點的間距大於最大限制週期。由於零點訊號為週期訊號,在最大限制週期內必定會有兩點真實的零點訊號發生,由此可知第一零點訊號點必定為雜訊。 在知道第一個零點訊號點為雜訊後,本發明便會將此點放棄,將第一參考訊號點移動至點2,再進行後續訊號判斷,而以點2為第一參考訊號點,其判斷方式就如同前面所述的訊號判斷方式,如圖17所示。 Similarly, the sequence signal arrangement is still performed in binary mode, and The different arrangements of the sequence signals are discussed. In Figure 16, the zero signal 1 is a noise, but the subsequent zero signal is a true zero signal. Step 1 is unqualified according to the present invention. The reason for the failure is that the distance between point 1 and point 2 is less than the minimum spacing limit, so the judgment is continued to the next point. Step 2 is unqualified according to the judgment of the present invention. The reason for the non-conformity is that the distance between point 1 and point 3 is greater than the maximum limit period. Since the zero signal is a periodic signal, there must be two true zero signals in the maximum limit period. It can be seen that the first zero signal point must be noise. After knowing that the first zero signal point is noise, the present invention will give up this point, move the first reference signal point to point 2, and then perform subsequent signal judgment, and point 2 is the first reference signal point. The way of judging is just like the signal judgment method described above, as shown in FIG.

第一個零點訊號為雜訊且位於條件判斷區內之序列訊號處 理:由圖18中可看出,零點訊號1雖然為雜訊但卻落於條件判斷區內。由於步驟1的判斷結果是符合條件的,訊號參考點乃移動至訊號點2,再進行後續的序列訊號判斷。若以此條件持續進行序列訊號判斷,最終將產生一組符合判斷條件的序列訊號,但對此組訊號進行最小週期變動量判斷時,由於其變動量加總值會大於正確訊號的變動量加總值,因此便可將該序列訊號視為錯誤的序列訊號並予以去除。 The first zero signal is noise and is located at the sequence signal in the conditional decision area. Reason: As can be seen from Figure 18, the zero signal 1 is a noise but falls within the conditional judgment area. Since the judgment result of the step 1 is that the condition is met, the signal reference point is moved to the signal point 2, and then the subsequent sequence signal judgment is performed. If the sequence signal judgment is continued under this condition, a sequence of signals corresponding to the judgment condition will be generated. However, when the minimum period variation of the group signal is judged, the total value of the variation will be greater than the variation of the correct signal. The total value, so the sequence signal can be regarded as the wrong sequence signal and removed.

在圖19中先討論第一個零點訊號落於條件判斷區內,但第二 個零點訊號未落於條件判斷區內。圖19的訊號判斷方式就如同前述的判斷方式,而其所產生的訊號序列會在最小週期變動量判斷程序中被去除。 In Figure 19, the first zero signal is discussed first in the conditional judgment area, but the second The zero signal does not fall within the conditional judgment area. The signal judging method of Fig. 19 is like the above-described judging method, and the signal sequence generated by it is removed in the minimum period variation amount judging program.

第一個零點訊號為雜訊且連續雜訊落於條件判斷區內訊號處理: The first zero signal is noise and the continuous noise falls within the conditional judgment area.

圖20-21繪示本發明對第一個零點雜訊落於條件判斷區內且第二個零點雜訊也落於條件判斷區內之處理情況。如圖所示,在進行零點訊號1與零點訊號2的條件判斷時,結果是符合條件的,本發明乃將判斷點由零點訊號1移動到零點訊號2,但在此之前會先進行判斷區內訊號複驗功能。在進行判斷區內訊號複驗功能後,可知零點訊號1與零點訊號3是符合條件的,因此會對此條件狀況進行記憶,待此次序列資料判斷結束後,根據記憶的條件狀況再次進行序列資料的判斷。 20-21 illustrate the processing of the first zero point noise in the conditional decision area and the second zero point noise also falls within the conditional decision area. As shown in the figure, when the condition of the zero signal 1 and the zero signal 2 is judged, the result is qualified. The present invention moves the judgment point from the zero signal 1 to the zero signal 2, but the judgment area is first performed before this. Internal signal retest function. After performing the signal re-inspection function in the judgment area, it can be seen that the zero signal 1 and the zero signal 3 are in compliance with the condition, so the condition condition is memorized, and after the judgment of the sequence data is finished, the sequence is again performed according to the condition of the memory. Judgment of the data.

由圖20及圖21可看出零點訊號不論是否為真實的零點訊號,只要零點訊號落於條件判斷區內,其處理方式均相同。之後,再經一最小週期變動量判斷程序,便可達到真實零點訊號取出的目的。其原因在於雜訊不具有良好的週期性,故即使其符合週期判斷條件,其變化量的累積值也必定大於週期訊號值的變化量累積值,而這也是本發明運作的基礎之一。 It can be seen from Fig. 20 and Fig. 21 that the zero signal is processed in the same manner as long as it is a true zero signal, as long as the zero signal falls within the conditional judgment area. After that, the final zero point signal can be taken out by a minimum period variation amount judgment program. The reason is that the noise does not have a good periodicity, so even if it meets the period judgment condition, the cumulative value of the change amount must be greater than the cumulative value of the change amount of the periodic signal value, and this is one of the foundations of the operation of the present invention.

在圖21中,連續兩雜訊分佈於二相鄰條件判斷區內,而接連的真實的零點訊號則出現於隨後的條件判斷區內。由於真實的零點訊號是不可能出現於條件判斷區外的,於計算式(3)可知Signaln+2必定落於判斷區間外。 In Fig. 21, two consecutive noises are distributed in the two adjacent conditional decision areas, and successive true zero signals appear in the subsequent conditional decision area. Since the real zero signal is unlikely to appear outside the conditional decision area, it can be seen from the calculation formula (3) that Signal n+2 must fall outside the judgment interval.

Minimum Cycle<Signaln+1-Signaln<Maximum Cycle (1) Minimum Cycle<Signal n+1 -Signal n <Maximum Cycle (1)

Maximum Cycle<Signaln+2-Signaln (2) Maximum Cycle<Signal n+2 -Signal n (2)

Maximum Cycle-Minimum Cycle<Signaln+2-Signaln+1 (3) Maximum Cycle-Minimum Cycle<Signal n+2 -Signal n+1 (3)

在第一零點訊號為雜訊的討論中可看出,在序列資料進行判斷時,只要序列資料判斷程序在進行參考判斷點移動時其中有一點為真實 的零點訊號,本發明便會以此點為出發點進行後續的序列資料判斷,因此就類似於第一訊號為真實訊號的判斷法。在此得到一個結論,若不能完成完整的序列訊號判斷,且並未記憶任何判斷區內的訊號複驗紀錄,就可知第一零點訊號為雜訊,而可將其忽略,並改以第二零點訊號為起始判斷訊號。若第二零點訊號仍然為雜訊,便依此類推,定能找到一真實的零點訊號作為起始訊號以進行判斷。 In the discussion of the first zero signal as noise, it can be seen that when the sequence data is judged, as long as the sequence data judgment program moves the reference judgment point, one of them is true. The zero point signal, the present invention will use this point as a starting point for subsequent sequence data judgment, and thus is similar to the judgment method that the first signal is a real signal. Here, we can conclude that if the complete sequence signal judgment cannot be completed and the signal re-inspection record in any judgment area is not memorized, the first zero-point signal is known as noise, but it can be ignored and changed to The 2020 signal is the initial judgment signal. If the second zero signal is still noise, and so on, it will be able to find a real zero signal as the starting signal for judgment.

依前述原理,本發明乃提出一種用於數位電源之零交越點雜 訊消除方法,其係以複數個零點訊號之對應時間值為資料來源,其中,所述複數個零點訊號包含複數個真實零點訊號,且任二相鄰的所述真實零點訊號間之時間差係介於一最小週期和一最大週期之間,該方法,請參照圖22所示本發明之一實施例之流程圖,包括以下步驟:第一步驟:選定所述複數個零點訊號之第一個零點訊號之時點為一起始參考點;第二步驟:判斷在所述複數個零點訊號中是否有在該起始參考點之後且和該起始參考點之時間差介於所述最小週期和所述最大週期之間的至少一可能合格訊號,若判斷結果為否,則將位於該起始參考點的訊號定義為雜訊並將該起始參考點移至最接近該參考點之一所述零點訊號的時點,並重新執行所述第二步驟;若判斷結果為是,則將該起始參考點定義為合格訊號點並將所述至少一可能合格訊號之時點設為至少一後續參考點;第三步驟:依序取所述至少一後續參考點中之一時點作為所述起始參考點並據以執行所述第二步驟; 第四步驟:重複執行所述第三步驟複數次並產生至少一組時序資料,其中各組所述時序資料係各由複數個所述合格訊號點組成;以及第五步驟:對所述至少一組時序資料之各組資料分別執行一週期變動量累加計算以產生至少一週期變動量累計值,並以所述至少一週期變動量累計值中之最小者所對應的一組所述時序資料作為所述複數個真實零點訊號的時序資料。 According to the foregoing principle, the present invention proposes a zero crossover point for a digital power supply. The signal cancellation method is characterized in that the corresponding time value of the plurality of zero signals is a data source, wherein the plurality of zero signals comprise a plurality of real zero signals, and the time difference between the two adjacent real zero signals is introduced. For a method between a minimum period and a maximum period, refer to the flowchart of an embodiment of the present invention shown in FIG. 22, including the following steps: First step: selecting the first zero point of the plurality of zero signals The time point of the signal is a starting reference point; the second step: determining whether there is a time difference between the initial reference point and the starting reference point in the plurality of zero signals between the minimum period and the maximum At least one possible qualified signal between the cycles, if the determination result is no, the signal at the initial reference point is defined as noise and the starting reference point is moved to the zero point closest to the reference point And the second step is re-executed; if the determination result is yes, the initial reference point is defined as a qualified signal point and the time point of the at least one possible qualified signal is set to Less a subsequent reference point; a third step of: sequentially taking said at least one point in a subsequent reference point as the starting point and the reference data to perform the second step; a fourth step: repeatedly performing the third step and generating at least one set of time series data, wherein each of the sets of the time series data is composed of a plurality of the qualified signal points; and a fifth step: the at least one Each group of data of the group timing data respectively performs a one-cycle variation amount accumulation calculation to generate at least one period variation amount cumulative value, and uses a set of the time series data corresponding to the smallest one of the at least one period variation amount cumulative value as Timing data of the plurality of real zero signals.

實驗結果:為確認本發明分離雜訊與市電模擬訊號的正確率,本發明乃將高頻雜訊模擬產生電路的責任週期統一調整至25%,低頻雜訊模擬產生電路的責任週期則由10%逐步調整到90%,以每10%為一個步階進行調整,每個步驟進行模擬訊號取樣2000點,並進行累積及平均計算,再對每步驟進行測試及記錄,其結果如表1所示。其中Fre(頻率)為經本發明所提方法除錯處理後輸出的訊號頻率。Fre1為直接對輸入的模擬訊號進行週期計算,換算為頻率值,累加2000個訊號點再平均的輸出值。Fre2為以傳統方式對模擬訊號進行點對點計算後,再進行最大及最小可能週期比對判斷,若不符合條件則予以放棄,符合條件則進行累加最終再進行平均所獲得的輸出頻率值,另外Fre Err%、Fre1 Err%及Fre2 Err%則為Fre、Fre1及Fre2經計算所得頻率與市電模擬頻率的誤差百分比。 Experimental results: In order to confirm the correct rate of the separation noise and the commercial analog signal of the present invention, the present invention uniformly adjusts the duty cycle of the high frequency noise simulation generating circuit to 25%, and the responsibility cycle of the low frequency noise analog generating circuit is 10 % is gradually adjusted to 90%, and is adjusted every 10%. Each step is to sample 2000 points of analog signals, and perform cumulative and average calculations. Then test and record each step. The results are shown in Table 1. Show. Where Fre is the frequency of the signal output after the error processing by the method of the present invention. Fre1 is a periodical calculation of the input analog signal directly, converted into a frequency value, and accumulated by 2000 signal points and then averaged output value. Fre2 is a point-to-point calculation of analog signals in the traditional way, and then the maximum and minimum possible period comparisons are judged. If the conditions are not met, they are discarded. If the conditions are met, the output frequency values obtained by accumulating and finally averaging are obtained. Err%, Fre1 Err% and Fre2 Err% are the error percentages of the calculated frequency of Fre, Fre1 and Fre2 and the mains simulation frequency.

依表1製作圖23、圖24。圖23為未經處理所得頻率值與經本 發明方法處理所得頻率值,經計算相對於模擬市電頻率的誤差百分比對照圖,係以低頻雜訊模擬訊號之責任週期百分比為橫軸,而其縱座標則為Fre Err%及Fre1 Err%誤差百分比值。由圖23中可得知Fre1 Err%的誤差值遠大於經本發明所提方法處理後輸出的誤差值,可知本發明所提方式是有效的。圖24為經傳統週期比對方式處理所得頻率值與經本發明所提方法處理所得之頻率值經計算相對於模擬市電頻率的誤差百分比對照圖。由圖24中可得知Fre2 Err%的誤差值雖小於圖23的Fre1 Err%,但仍遠大於經本發明所提方法處理後輸出的誤差值Fre Err%,可知本發明所提方式比傳統週期比對方式可更有效地將誤差減小。另外,由圖中也可看出,隨著雜訊調整比例的上升,未經處理的訊號輸出值快速的產生誤差,經傳統週期限制比對處理的訊號輸出值也逐漸偏離標準值,而經本發明所提方法處理的輸出訊號值則仍然維持極小的誤差。在此實測結果中,經本發明處理完成的頻率數 值最大誤差值為0.023%,其與以傳統週期區間判斷處理方式所得的最小誤差值0.685%相比較,兩者之間的差距可達30倍。 Figure 23 and Figure 24 are produced according to Table 1. Figure 23 shows the untreated frequency value and the The method of the invention processes the obtained frequency value and calculates a percentage error percentage comparison with respect to the simulated mains frequency, wherein the percentage of the duty cycle of the low frequency noise analog signal is the horizontal axis, and the ordinate is the Fre Err% and Fre1 Err% error percentage. value. It can be seen from Fig. 23 that the error value of Fre1 Err% is much larger than the error value outputted by the method of the present invention, and it is understood that the proposed method of the present invention is effective. Figure 24 is a graph comparing the error percentages of the frequency values processed by the conventional period comparison method and the frequency values obtained by the method of the present invention with respect to the simulated mains frequency. It can be seen from Fig. 24 that the error value of Fre2 Err% is smaller than Fre1 Err% of Fig. 23, but is still much larger than the error value Fre Err% outputted by the method of the present invention, and it can be seen that the proposed method is longer than the conventional cycle. The alignment method can reduce the error more effectively. In addition, as can be seen from the figure, as the noise adjustment ratio increases, the unprocessed signal output value rapidly produces an error, and the signal output value processed by the conventional period limit comparison gradually deviates from the standard value, and The output signal values processed by the method of the invention still maintain a very small error. The number of frequencies processed by the present invention in the measured results The maximum error value of the value is 0.023%, which is compared with the minimum error value of 0.685% obtained by the traditional period interval judgment processing method, and the difference between the two can reach 30 times.

本案所揭示者,乃較佳實施例,舉凡局部之變更或修飾而源 於本案之技術思想而為熟習該項技藝之人所易於推知者,俱不脫本案之專利權範疇。 The present invention is the preferred embodiment, and the source is changed or modified locally. Those who are acquainted with the technical idea of the case and who are familiar with the skill can not deduct the patent right of the case.

綜上所陳,本案無論就目的、手段與功效,在在顯示其迥異 於習知之技術特徵,且其首先發明合於實用,亦在在符合發明之專利要件,懇請 貴審查委員明察,並祈早日賜予專利,俾嘉惠社會,實感德便。 In summary, this case shows its difference in terms of purpose, means and function. In the technical characteristics of Xizhi, and its first invention is practical and practical, it is also in compliance with the patent requirements of the invention. Please ask your review committee to inspect it and pray for an early patent.

Claims (1)

一種用於數位電源之零交越點雜訊消除方法,其係以複數個零點訊號之對應時間值為資料來源,其中,所述複數個零點訊號包含複數個真實零點訊號,且任二相鄰的所述真實零點訊號間之時間差係介於一最小週期和一最大週期之間,該方法包括以下步驟:第一步驟:選定所述複數個零點訊號之第一個零點訊號之時點為一起始參考點;第二步驟:判斷在所述複數個零點訊號中是否有在該起始參考點之後且和該起始參考點之時間差介於所述最小週期和所述最大週期之間的至少一可能合格訊號,若判斷結果為否,則將位於該起始參考點的訊號定義為雜訊並將該起始參考點移至最接近該參考點之一所述零點訊號的時點,並重新執行所述第二步驟;若判斷結果為是,則將該起始參考點定義為合格訊號點並將所述至少一可能合格訊號之時點設為至少一後續參考點;第三步驟:依序取所述至少一後續參考點中之一時點作為所述起始參考點並據以執行所述第二步驟;第四步驟:重複執行所述第三步驟複數次並產生至少一組時序資料,其中各組所述時序資料係各由複數個所述合格訊號點組成;以及第五步驟:對所述至少一組時序資料之各組資料分別執行一週期變動量累加計算以產生至少一週期變動量累計值,並以所述至少一週期變動量累計值中之最小者所對應的一組所述時序資料作為所述複數個真實零點訊號的時序資料。 A zero-crossing point noise cancellation method for a digital power supply, wherein the corresponding time value of the plurality of zero signals is a data source, wherein the plurality of zero signals comprise a plurality of real zero signals, and any two adjacent The time difference between the real zero signals is between a minimum period and a maximum period, and the method includes the following steps: the first step: selecting a first zero point signal of the plurality of zero signals as a start point a reference point; a second step: determining whether at least one of the plurality of zero signals is after the start reference point and the time difference from the start reference point is between the minimum period and the maximum period Possible test signal. If the judgment result is no, the signal at the start reference point is defined as noise and the start reference point is moved to the time point closest to the zero point signal of the reference point, and is re-executed. The second step; if the determination result is yes, the initial reference point is defined as a qualified signal point and the time point of the at least one possible qualified signal is set to at least one subsequent reference a third step: sequentially taking one of the at least one subsequent reference point as the starting reference point and performing the second step; and fourth step: repeatedly performing the third step and performing the third step Generating at least one set of timing data, wherein each of the sets of timing data is composed of a plurality of the qualified signal points; and a fifth step: performing a one-cycle variation accumulation on each of the at least one set of time series data Calculating to generate at least one period of the variation amount cumulative value, and using the set of the time series data corresponding to the smallest one of the at least one period variation amount cumulative value as the time series data of the plurality of real zero point signals.
TW104127111A 2015-08-20 2015-08-20 A Method for Eliminating Zero Crossing Point Noise in Digital Power Supply TWI542146B (en)

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