TWI540862B - Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect - Google Patents

Description

Effectiveness and power optimization computer system architecture and method for effectively utilizing power optimization tree organization interconnection structure Priority claim / related application

The present application claims priority from U.S. Patent Application Serial No. 12/794,996, filed on Jun. 7, 2010, entitled, <RTIgt;<RTIID=0.0>> The entire contents of this application are incorporated herein by reference. In addition, the present patent application claims the U.S. Provisional Patent Application No. 61/383,585, entitled "Performance and Power Optimized Computer System Architectures and Methods Leveraging Power Optimized Tree Fabric Interconnect", filed on September 16, 2010. The entire contents of this application are hereby incorporated by reference.

Field of invention

The present invention relates to a computer system architecture and method for efficient performance and power optimization for efficient use of power optimized tree organization interconnect structures.

Background of the invention

Figures 1 and 2 illustrate a conventional data center network aggregation as is currently known. 1 is a simplified diagram of a typical network data center architecture 100 in which top-level switches 101a-n are on top of brackets 102a-n, brackets 102a-n are filled with blade-type servers 107a-n, blade-type servers 107a -n is distributed with local routers 103a-f. 105a-b and additional bracket units 108a-n contain additional servers 104e-k and routers 106a-g. 2 illustrates an exemplary physical view 110 of a system having peripheral servers 111a-bn disposed around edge router systems 112a-h, with edge router systems 112a-h placed around central positioning core switching system 113. Typically, this aggregation 110 has a 1-Gb Ethernet network from the rack server to the top-of-rack switches of the rack servers, and typically 10 Gb Ethernet ports to the edge and core routers.

According to an embodiment of the present invention, a computing device is specifically provided, the computing device comprising: a plurality of server nodes, wherein each server node includes a processor, a memory, an input/output interconnected with each other a circuit and a tissue switch; a tissue switch interconnecting the plurality of server nodes by a plurality of organization links; and one or more Ethernet outlets, the one or more B The Ethernet out port is from the organization switch, and the one or more Ethernet outlets form a power optimized server organization.

According to another embodiment of the present invention, a computing device is specifically provided, the computing device comprising: a storage device having a shape factor; a server node, wherein the server node includes a processor, a memory Body, an input/output circuit, an exchange organization, and one or more SATA interfaces for the storage device, the server node having the same form factor as the storage device.

According to still another embodiment of the present invention, a method for generating a high-density computing system is specifically provided, the method comprising the steps of: providing a server node having a processor, a memory, and a An input/output circuit, an exchange organization, and one or more SATA interfaces; and packaging the server node into a form factor of a hard disk drive.

In accordance with still another embodiment of the present invention, a method for generating a high density computing system is provided, the method comprising the steps of: providing a standard form factor disc drive; and integrating a server node into the standard In a form factor disc drive machine, the server node has a processor, a memory, an input/output circuit, an exchange organization, and one or more SATA interfaces, wherein the standard form factor disc drive is provided Integrated computing power.

In accordance with another embodiment of the present invention, a computing device is provided, the computing device comprising: a circuit board; one or more dynamic memory chips mounted on the circuit board; one or more mounted to the circuit board a multi-computing wafer; one or more flash memory chips mounted to the circuit board; wherein the circuit board is mounted vertically such that the one or more flash memory wafers are below the one or more computing wafers, and The one or more dynamic memory chips are above the one or more computing wafers; one of the vertically mounted circuit boards is a chimney cooler.

According to still another embodiment of the present invention, a computing device is provided, the computing device comprising: one or more processors; a bus bar organization connected to one of the one or more processors; an organization switch, the organization A switch is connected to the bus organization, the organization switch outputs data from the computing device to one or more ports; and one or more routing header processors, wherein each routing header processor is configured to be routed A particular transport stream is streamed so that the organization switch handles different transport streams.

According to still another embodiment of the present invention, a computing device is provided, the computing device comprising: one or more processors; a bus bar organization connected to one of the one or more processors; an organization switch, the organization a switch connected to the bus organization, the organization switch outputting data from the computing device to one or more ports; a bus bar protocol bridge connected between the bus bar organization and the exchange organization; and one or More routing header processors, where each routing header processor is used to route a particular transport stream by routing so that the organization switch handles different transport streams.

In accordance with another embodiment of the present invention, a method for exchanging different transport streams is specifically provided, the method comprising the steps of: providing one or more processors and connecting to one of the one or more processors Organizing; providing an organization switch connected to the bus organization, the organization switch outputting data from the computing device to one or more ports; and using one or more routing header processors to exchange a particular transport stream So that the organization switch handles different transport streams.

According to still another embodiment of the present invention, a method for load balancing using an exchange organization is specifically proposed, the method comprising the steps of: providing a server node having one or more processors; connecting to the One of the one or more processors' busbar organization; one of the busbar organizations connected to the organization, the organization switch outputting data from the computing device to one or more ports; and connecting to the organization switch An IP virtual server; receiving an incoming request; routing the incoming request to the IP virtual server connected to the organization switch; generating the target for the organization using the IP virtual server connected to the organization switch One of a particular node routing a header; forwarding the incoming request to the particular node; and processing the incoming request using the particular node to provide load balancing.

According to still another embodiment of the present invention, a method for processing using an exchange organization is provided, the method comprising the steps of: providing a server node having one or more processors; connecting to the one One or more processors, a bus organization; one of the bus organizations connected to the organization, the organization switch outputs data from the computing device to one or more ports; and is connected to one of the organization switches a streaming device; receiving an incoming request; routing the incoming request to the open flow device connected to the organization switch; using the open flow device to generate a routing header for one of the specific nodes of the organization; The request is forwarded to the particular node; the incoming request is processed using the particular node to provide load balancing; and the processed incoming request is sent back to the open flow device.

According to another embodiment of the present invention, a computing device is provided, the computing device comprising: one or more processors; a busbar organization connected to one of the one or more processors; and connected to the busbar organization An organization switch that outputs data from the computing device to one or more ports; to a PCIe interface of the bus bar organization; and to the external processor of the computing device using the PCIe interface.

In accordance with yet another embodiment of the present invention, a computing device is provided, the computing device comprising: a tissue switch that outputs data from the computing device to one or more ports; and connects to the tissue switch One of the Ethernet ports; and an external processor connected to the computing device using an Ethernet interface.

Simple illustration

Figure 1 and Figure 2 illustrate typical data center network aggregation;

Figure 3 illustrates network aggregation using a server in accordance with one embodiment;

Figure 4 illustrates a data center in a stent in accordance with one embodiment;

Figure 5 illustrates a high-level topology of a network system with an exchange organization;

Figure 6 illustrates a server board that constitutes a plurality of server nodes interconnected with the point-to-point interconnect structure;

Figure 6a - Figure 6c illustrate another example of a tissue topology;

Figure 7 illustrates an example of a passive backplane connected to one or more node boards and two polymeric boards;

Figure 8 illustrates an example of an extended tissue crossing the shelf and the link shelf over the server bracket;

Figure 9a illustrates an exemplary server 700 having a disc form factor;

Figures 9b and 9c illustrate an exemplary array of disc-server combinations in accordance with one embodiment, the disc-server combination using a storage server 1-node SATA board;

Figure 9d illustrates a standard 3.5” drive;

Figure 9e illustrates the implementation of a plurality of server nodes in a standard 3.5" disc drive form factor;

Figure 10 illustrates the implementation of a server that is deeply integrated with the storage;

Figure 11 illustrates an implementation of the close packing of the storage and server of an existing 3.5" JBOD storage box;

Figure 12 illustrates the implementation of a server node exemplified in the same form factor of a 2.5" drive;

Figure 13 illustrates the implementation of the bracket chimney cooling;

Figure 13a illustrates an exemplary illustration of the heat convection used in the cooling of the chimney bracket shown in Figure 13;

Figure 14 illustrates server nodes that are placed diagonally relative to one another to minimize self-heating across the server node;

Figure 15 illustrates an exemplary 16-node system in accordance with one embodiment in which heat waves rise from a printed circuit board;

Figure 16 illustrates a higher density variant of a 16-node system having nodes similarly arranged to minimize self-heating across nodes;

Figure 17 illustrates the internal architecture of the server node organization switch;

Figure 18 illustrates a server node that includes a PCIe controller that is coupled to an internal CPU bus organization;

Figure 18a illustrates a system with multiple protocol bridges using a tissue switch;

Figure 19 illustrates the integration of server organization and network processor;

Figure 20 illustrates an organization switch and an FPGA that provides services such as the Internet Protocol Virtual Server (IPVS);

Figure 21 illustrates a method of constructing OpenFlow process processing as a Calxeda organization;

Figure 22 illustrates an example of a power optimized organization switch integrated into an existing processor via PCIe;

Figure 23 illustrates an example of a power optimized organization switch integrated into an existing processor via Ethernet.

Detailed description of the preferred embodiment

The present invention discloses an architecture and method for efficiently optimizing the performance and power optimization of a power-optimized tree organization interconnect structure. One embodiment uses a tile building block to build a low power server cluster that effectively utilizes the organization, while another embodiment implements a storage solution or cooling solution. Another embodiment uses an organization to exchange other things.

The architecture of the power optimization server communication organization is described in the patent application Serial No. 12/794,996, the power optimization server communication organization uses a tree topology or a graphics topology to support routing, the tree topology or graphics The topology supports multiple links per node within the topology, with each link designated as an uplink, downlink, or lateral link. The system uses a segmented MAC architecture that can have a MAC IP address repurposed for internal MAC and external MAC, and effectively utilizes mechanisms that will typically be used for MAC physical signal delivery to the switch. Methods. The Calxeda XAUI system interconnect structure reduces power, wire and bracket size. No high power, expensive Ethernet switches and high power Ethernet physical layer (Phy) are required on individual servers. This significantly reduces the cable (cable complexity, cost, and an important source of failure). This also enables heterogeneous server mixing in the rack to support any device using Ethernet or SATA or PCIe. In this architecture, power savings come mainly from two architectural aspects: 1) minimization of the physical layer of the Ethernet across the organization, replacing the Ethernet entity layers with nodes in a point-to-point XAUI interconnect structure, And 2) the ability to dynamically adjust the XAUI width and speed of the link based on the load.

Figure 3 illustrates network aggregation 200. This network supports 10-Gb/sec Ethernet communication 201 (thick line) between the aggregation router 202 and the three brackets 203a-c. In the bracket 203a, the Calxeda interconnect structure provides a plurality of high speed 10 Gb paths between the servers 206a-d on the shelves within the rack, the paths being indicated by thick lines. The embedded switch in servers 206a-d replaces the top-of-rack switch, thus saving a lot of power and cost while still providing 10 Gb Ethernet to the aggregation router. The Calxeda Exchange organization can integrate legacy Ethernet (1 Gb or 10 Gb) into the Calxeda XAUI organization, and the Calxeda server can act as a top-of-rack switch for third-party Ethernet connectivity servers.

The intermediate bracket 203b illustrates another situation in which the Calxeda servers 206e, 206f can be integrated into existing data center racks that contain overhead switches 208a. In this case, the IT group can continue to connect other servers of the IT group up to the existing top-of-rack switch via 1 Gb Ethernet. The Calxeda internal server can be connected via the Calxeda 10 Gb XAUI organization and the Calxeda internal servers can be integrated up to the existing top-of-rack switch using a 1 Gb or 10 Gb Ethernet interconnect structure. The bracket 203c on the right side is the current way of deploying the data center bracket in a conventional manner. The thin red line indicates 1 Gb Ethernet. Thus, traditionally, the data center rack is currently deployed with a 1 Gb Ethernet connection up to the top-of-rack switch 308b, and then 10 Gb (thick red line 201) is output from the top-of-rack switch to the aggregation router. It should be noted that all servers exist in unknown quantities, however, such servers are illustrated in limited numbers for purposes of clarity and conciseness. Also, by using the enhanced Calxeda server, no additional routers are needed, as these enhance the Calxeda server to operate its own XAUI exchange organization, as described below.

FIG. 4 illustrates an overview of an exemplary "in-bracket data center" 400 in accordance with one embodiment. The in-stand data center 400 has a 10-Gb Ethernet physical layer 401a-n and a 1-Gb dedicated Ethernet physical layer 402. Large computer (power server) 403a-n support search; data exploration; index; Hadoop, Java software framework; MapReduce, which is a software framework introduced by Google to support distributed computing on large data sets on a cluster of computers; Cloud applications, etc. Computer (server) 404a-n with regional flash memory and/or solid-state disk (SSD) supports search, MySQL, CDN, software-as-a-service (SaaS) , cloud applications, etc. A single large low speed fan 405 expands the convection cooling of a vertically mounted server above a single large low speed fan 405. The data center 400 has an array 406 of, for example, a hard disk in a Just a Bunch of Disks (JBOD) configuration, and optionally a Calxeda server (a green frame in arrays 406 and 407) of the disc form factor. These Calxeda servers optionally act as disc controllers. The hard disk server or Calxeda disc server can be used for web servers, user applications, and cloud applications. An array 407 of storage servers is also illustrated, as well as historical servers 408a, 408b (any size, any vendor) having a standard Ethernet interface for legacy applications.

Figure 5 illustrates a high-order topology 500 of the network system described in the co-pending patent application Serial No. 12/794,996, which is incorporated herein by reference. 10 Gb Ethernet 埠 Eth0 501a and Eth1 501b come from the top of the tree. The ovals 502a-n are Calxeda nodes, which include both computational processors and embedded switches. The node has five XAUI links connected to the internal switch. The switch layer uses all five XAUI links for switching. Hierarchy 0 leaf nodes 502d, 502e (ie, N0n nodes or Nxy, where x=hierarchy and y=item number) use only one XAUI link to attach to the interconnect structure, leaving left to be attached to I /O's XAUI, 10 Gb Ethernet, PCIe, SATA and other four high-speed ports. Most trees and thick trees only have valid nodes like leaf nodes, while other nodes are pure switching nodes. This approach makes routing more straightforward. Topology 500 has the flexibility to allow each node to be a combined computing and switching node, or just a switching node. Most tree type implementations have I/O on leaf nodes, but topology 500 allows I/O to be on any node. Typically, placing Ethernet on top of the tree minimizes the average number of hops to the Ethernet.

Building a power optimized server organization board using tiled building blocks

Figure 6 illustrates a server board that constitutes a plurality of server nodes that are interconnected with the point-to-point interconnect structure. The server board has:

• Each of the ovals in this graph is a standalone server node that includes a processor, memory, I/O, and organization switch.

• The organization switch has the ability to dynamically modify the width (number of paths) and speed of each path for each link independently.

The 14-node board example illustrates two self-organizing Ethernet outlets. These Ethernet egress ports will typically be routed to a standard Ethernet switch or router. These Ethernet outlets can be standard 1 Gb or 10 Gb Ethernet.

The 14-node instance topology is a butterfly-shaped thick tree that provides redundant paths to allow adaptive routing to routes around faults and to locate routes around hotspots.

The 3-node aggregator board allows large server organizations to consist of only two tile tiles.

■ Adding a second aggregator for redundancy

■Input / Output:

● PCIe connector for smooth-stone organization

●Optional Ethernet support (off, 1 Gb, 2 Gb, 5 Gb, 10 Gb or 20 Gb)

■Ethernet decision based on the bandwidth required by the application

The nodes on the aggregator board can be only switching nodes, or full computing nodes including switches.

● Board input/output can be PCIe connector and / or optional Ethernet support (off, 1 Gb, 2 Gb, 10 Gb or 20 Gb), the PCIe connector supports two x4 XAUI (2 talc organizations) link).

An exemplary organizational topology like a 14-node instance minimizes the number of links across the board to minimize connector (size and number) and associated costs while still maintaining Ethernet egress and multipath redundancy.

• Two aggregator boards can be used to achieve path redundancy when extending the tissue.

● Power savings can be achieved using static link configuration

○ The lower layer nodes (denoted as leaf nodes) in the figure can be executed at 1 Gb/sec.

o The first layer of switching nodes (denoted as layer 1 switches) in the figure will then have an input bandwidth of 3 Gb/sec from the leaf nodes. This allows a static link configuration of 2.5 Gb/sec or 5 Gb/sec between the Layer 1 switch and the Layer 2 switch.

o Then, the link extending away from the layer 2 switching layer can be executed at 10 Gb/sec.

○ In this topology, since most nodes are leaf nodes, most links are executed at the slowest rate (1 Gb/sec in this example), thus minimizing network connection power consumption.

○ Allows the Ethernet egress to be pulled out at any node in the organization, allowing the organization designer to compromise the required bandwidth of the Ethernet exit, the number of eaves used by the top-of-rack switch, and The cost and power associated with Ethernet.

• Power savings can be further optimized via the link utilizing the driven dynamic link configuration. In this example, each link and organization switch association has a bandwidth counter with configurable threshold events that allow reconfiguration of the uplink based on dynamic link utilization Road width and speed, and downlink width and speed.

● Since the Ethernet traffic is mainly from node to external Ethernet instead of node to node under many shared server usage conditions, the proposed tree organization (and especially the butterfly thick tree instance) is minimized. The number of hops that traverse the organization to the Ethernet network is minimized, thus minimizing latency. This allows the establishment of a large low-latency organization of the Ethernet network while utilizing a switch with a relatively small number of exchanges (in this example 5).

The integration of the server 209a in Figure 2 illustrates the use of another novel system of server organization defined. In this case, to exploit the performance and power management of the server organization, and to minimize the use of overhead on the top-of-rack switch, this figure illustrates the heterogeneous integration of existing servers onto the defined server organization so that The existing server's Ethernet traffic can enter the organization via the gateway, allowing communication with nodes within the organization and 209a Ethernet traffic to be carried over the organization to the uplink Ethernet port 201.

Figure 6a - Figure 6c illustrate another example of an organization topology that is a forty-eight node organization topology consisting of 12 cards connected to a system board, where each card contains 4 nodes. This topology provides some redundant links but no major redundancy. The topology has four Ethernet gateway escape ports and each of these Ethernet gateway escape ports can be 1 Gb or 10 Gb, but does not require the use or connection of all such Ethernet networks. Gateway. In the illustrated example, eight tissue links are taken from a four-node card, and in one example, the PCIe x16 connector uses four slave links from the card.

Overview/Overview of Building a Power Optimized Server Organization Board Using Tiled Building Blocks

1. The server tree organization allows any number of Ethernet egress exits across the server interconnect fabric to minimize the number of Ethernet entities used to save association with the Ethernet physical layer Power and cost, associated cables, and consumption on top-of-rack Ethernet switches/routers.

2. The switching node can be a pure switching node that conserves power by disconnecting the computing subsystem, or the switching nodes can be used as a full computing subsystem including organizational switching. Referring to Figure 17, in one implementation, multiple power domains are used to separate the computing subsystem (block 905) from the management processor (block 906) and the organization switch (remaining blocks). This allows the SOC to be configured as a power off calculation subsystem (block 905), maintaining the management process in block 906, and hardware packet exchange and routing by the organization switch.

3. The Butterfly-Shaped Tree Topology Server organization provides the minimum number of links in the board (saving power and cost), the minimum number of links across the board (saving power and cost), while allowing redundancy within and across boards. The remaining link path.

4. The proposed backplane and aggregator board allows the scalable failover server organization to consist of only two board building blocks.

5. Tree-directed server organization and variants of similar exemplary butterfly-shaped thick trees allow for static link width and speed specifications that can be determined by the aggregate bandwidth of the child nodes of the node, allowing for easy link configuration while minimizing mutual Connected structure power.

6. The power savings can be further optimized via the link utilizing the driven dynamic link configuration. In this example, each link and organization switch association has a bandwidth counter with configurable threshold events that allow reconfiguration of the uplink based on dynamic link utilization Road width and speed, and downlink width and speed.

7. Since the Ethernet traffic is mainly from node to external Ethernet instead of node to node under many shared server usage conditions, the proposed tree organization (and especially the butterfly thick tree instance) is the smallest. The number of hops that traverse the organization to the Ethernet network is minimized, thus minimizing latency. This allows the establishment of a large low-latency organization of the Ethernet network while utilizing a switch with a relatively small number of exchanges (in this example 5).

8. Allow heterogeneous servers to be integrated into the organization, allowing Ethernet traffic from existing servers to enter and pass through defined server communication organizations.

Use tiled building blocks to build power optimized server shelves and brackets

These board "tiles" can now be formed to construct the shelves and brackets that connect the server nodes. Figure 7 illustrates an example of how a passive backplane can connect eight 14-node boards and two aggregation boards to form a shelf of 236 server nodes. Each plate can be, for example, 8.7" high + mechanical height < 10.75" for 6U, interspersed hot trough for density and 16 plates for 19" wide brackets. The backplane can be simple/cheap, with PCIe connectors and routing, where the routing can be a very simple and wireless XAUI signal (blue and green) + power. The Ethernet connection diagram is at the 8-plate aggregation point.

Figure 8 illustrates an example in which the extended tissue passes over the shelf and the link shelf passes over the server bracket. The Ethernet egress can be pulled out at any node in the organization, in this example, the Ethernet exits are pulled out from the passive interconnect fabric backplane that connects the multi-node blades.

Overview/Overview of Building Power Optimized Server Shelves and Brackets Using Tiled Building Blocks

1. Use the PCIe connector to route the Ethernet out port and the XAUI link away from the board to connect the board to the point-to-point server organization, not using PCIe signaling, but using the physical connector for the power of the board and The XAUI signal maintains redundant communication paths for failover and hotspot reduction.

2. XAUI peer-to-peer server interconnect structure organized by a fully passive backplane.

3. Cross the organization's Ethernet outlet, which spans every level of the tree, not just the top of the tree.

4. Can be dynamically enabled and can be used to cross the organization's Ethernet outlet to match bandwidth and optimize power usage.

5. The node-to-node traffic, including system management traffic, stays on the traversal of the cradle and does not pass through the top-of-rack Ethernet switch.

Storage

Figure 9a illustrates an exemplary server 700 having a disc form factor, typically such as a standard 2.3" or 3.5" hard disk drive with a SCSI or SATA driver, according to one embodiment. ;HDD). The servo board 701 accommodates the same basic structure as the disc drive 702 in the current disc holder. Server 701 is a full server with DDR, server-on-a-chip SoC, optional flash memory, local power management, SATA connection to the disc (connected The size of the device is limited to 1-16......). The output of server 701 can be an Ethernet or Calxeda organization (XAUI) with two XAUI outputs for failover. Alternatively, server 701 can use PCIe instead of ATA (SSD or other things that require PCIe), with 1 to 4 nodes balancing computing and storage requirements. This server is available for RAID implementation and LAMP stacking server applications. Use Calxeda ServerNode ^TM on each disc to provide a full 4 GB of DDR3 LAMP stack of servers, and a plurality of SATA interface. Optionally, a second node for 8 GB of DDR can be added as needed.

Figures 9b and 9c illustrate exemplary arrays 710 and 720 of disc-server combinations 700a-n, respectively, using a storage server as discussed above, in accordance with one embodiment 1 node SATA board. Eliminate the need for large Ethernet switches by connecting high-speed networks or interconnects (standard or proprietary) to save power, cost, heat and area. Each plate 701 is smaller than the height and depth of the disc. The array can be arranged alternately with the disc and the board, as shown in Figure 7b, or one board can serve multiple discs, for example, in a disc-disc-plate-disc-disc arrangement, such as Shown in Figure 7c. Therefore, the calculated power can be matched to the disc ratio in a flexible manner. The connectivity of the boards 701a-n can be based on each node, where SATA is used to hook the disc and multiple SATAs are used to hook multiple discs. The connectivity of the boards 701a-n may also be based on node-to-node, where two of the XAUIs in the organization configuration in each node (as previously described in the application and in the 61/256,723 application) are used for redundancy. Nodes are connected via the XAUI organization. Such connections may have a tree or coarse tree topology, ie, node-node-node-nodes, where deterministic, irrelevant or adaptive routing moves data in the correct direction. Alternatively, you can use a fully proprietary interconnect structure to move to other processing units. Some can turn to Ethernet output or any other I/O pipeline. Each node can go directly to the Ethernet (within the "box"), or XAUI to the XAUI aggregator (switch) and then to the physical layer, or XAUI to the physical layer. Or any combination of the above can be used. In other cases, an SSD with a PCIe connection can be used to replace the SATA connection with a PCIe connection. Some SSDs use PCIe or SATA to enter the disc form factor. Or you can mix PCIe and SATA. Instead of XAUI, the Ethernet from the box can be used for system interconnection. In some cases, for example, a standard SATA connector can be used, but in other cases a higher density connector with dedicated wiring through the dedicated backplane can be fabricated.

In another case, the server function can be in the disc drive, thereby providing a full server plus disc in the single disc drive form factor. For example, ServerNode ^TM may be mounted on a board within the disc. This method can be implemented with XAUI or Ethernet connectivity. In this case, the server single chip method known to the inventors can be used as the disc controller plus the servo. Figure 9d illustrates this concept. The standard 3.5" drive (item 9d0) is illustrated in Figure 9d. The 3.5" drive has an integrated circuit card 9d1 for controlling the disc drive. A large amount of space in the drive unit (marked by 9d2) is not used, in which a Calxeda low power, small server node PCB can be formed to fit within this unused space within the disc drive.

Figure 9e illustrates the implementation of placing multiple server nodes in a standard 3.5" disc drive form factor. In this case, the connector from the server PCB to the backplane outputs an XAUI-based server organization interconnect structure to provide network and inter-server communication organization, and four SATA ports for connecting to adjacent SATA drivers.

Figure 10 illustrates an implementation for deep integration of servers and storage. The server node (101) presents a fully low power server that integrates the compute core, DRAM, integrated I/O, and organization switch. In this example, the server node 101 is illustrated with the same form factor as the standard 2.5 inch disc drive (102). (103) The illustration combines the server nodes and the disc drive in a pair-to-one manner, wherein each server node has its own local storage of the server node. (104) shows a server node that controls four disk drive machines. The system (105) illustrates that these storage servers are combined via a unified server organization, and then in this example, four 10-Gb/sec Ethernet outlets are pulled out of the organization to connect to the Ethernet. Switch or router.

Figure 11 illustrates a specific implementation of this close accumulation of memory and server by illustrating the efficient use of existing 3.5-inch cluster disk (JBOD) storage boxes. In this case, the JBOD mechanical object including the disc casing is not changed, but the storage node is shown as being paired with the disc drive in the unmodified JBOD box. This shows that the server node is a pluggable module, and the pluggable modules are inserted into the motherboard below the organization link. In this description, the standard JBOD box holds 23 3.5-inch discs (illustrated as rectangles in the logical view), and this figure shows 31 server nodes in the JBOD box that control 23 discs. The logical view is shown as oval/circular) and exposes two 10 Gb/sec Ethernet links (shown as dark wide lines in the logical view). This tightly integrated server/storage concept uses only the off-the-shelf JBOD box and then adds 31 server nodes in the same form factor via power optimized tissue communication. This is excellently mapped to applications that preferably have local storage.

Figure 12 illustrates the related concept of effectively utilizing the fact that server nodes can be instantiated in the same form factor of a 2.5" drive. In this case, the server node is integrated into a 2.5" JBOD with 46 discs. This concept illustrates 64 server nodes integrated into the same form factor of the JBOD storage. In this example, two 10 Gb Ethernet links are pulled out of the organization, and a 1 Gb/sec managed Ethernet link.

Overview / Overview of the storage

1. Use the PCIe connector to route the Ethernet out port and the XAUI link away from the board to connect the board to the point-to-point server organization, not using PCIe signaling, but using the physical connector for the power of the board and The XAUI signal maintains redundant communication paths for fault recovery and load balancing.

2. By using a small form factor low power organization to enable the server node to pair with the disc, using the defined server organization to convert the existing JBOD storage system, thereby providing a very high density computing server, the computing server Tightly paired with local storage and integrated by power and performance optimization server organization to create new high performance computing server and storage server solutions without affecting the physical and mechanical design of the JBOD storage system.

3. For high-density computing systems, the method of packaging a full server into the form factor of a hard disk drive is used to replace some drivers with additional servers.

4. As claimed in claim 3, wherein the server is connected to the network via an additional exchange organization.

5. In claim 3, wherein the base plate in the outer casing of the fixed drive is replaced with a base plate adapted to establish at least one internal exchange path.

6. For high-density storage systems, the integration of low-power servo PCBs into the blank space of a standard 3.5-inch disc drive provides integrated computing capabilities within the disc drive.

Bracket integration for cooling of low power servers

One aspect of driving to a low-power computer server solution is the management of heat, cooling, and air movement through the rack and across the board. The minimization of the fan is one aspect of reducing the total cost of ownership (TCO) of the low power server. Fans increase cost, complexity, reduce reliability due to moving parts, consume a lot of power, and generate a lot of noise. Fan reduction and removal can provide significant benefits in terms of reliability, TCO, and power consumption.

Figure 13 illustrates a novel implementation of stent chimney cooling that supports chimney cooling throughout all or only the stent sections. An important aspect is the single fan in the chimney bracket concept, which uses upward natural convection with the help of a fan. The large fan that cools all the brackets can be low speed. The large fan can be positioned at the bottom or within the bracket below the vertically mounted convection cooling subset of the bracket. As cold air enters the bottom, the fan pushes cold air through the chimney and pushes out the top. Since all the plates are vertical, there is no horizontal barrier. Although the fan is illustrated at the bottom of the bracket in this example, the fan can be anywhere in the system. That is, the system may have a horizontal blockage with "conventional" cooling under the vents and fans, leaving the top as a vertical chimney. This vertical bottom cooling method works on small systems. The fan can be variable speed and varies with temperature.

Figure 13a illustrates an exemplary illustration of the novel principles of heat convection 500 for use in the chimney bracket concept. Aligning the placement components at an angle causes the heat streams 501a-n to rise from the Double Data Rate (DDR) memory chips 503a-n on the printed circuit board 502, so that the heat sinks do not form a hot backup. Or get hot from each other. In this example, the DDR wafers are placed in a diagonal rather than a vertical stack with each other because the DDR wafers are easily heated to each other. Again, the DDR wafers are placed over large compute wafers 504a (such as ASICs, SOCs, or processors) rather than below because the DDR wafers tend to heat the SOC. The coldest wafer (flash chip 506) is placed under the SOC. Likewise, nodes are not stacked vertically, as described below. Figure 14 extends this concept to illustrate how server nodes are placed diagonally with respect to each other to minimize self-heating across server nodes.

Figure 15 illustrates an exemplary 16-node system in accordance with one embodiment in which heat waves rise from a printed circuit board. For a typical 16-node system, individual cells are arranged so that the heat rising from each cell does not heat the cells above. The entire outer casing will typically be longer, not too tall and less dense. Again, instead of mounting the PCB diagonally as shown, the PCB can be square aligned and rectangular, but the components can be placed diagonally to minimize mutual heating. PCBs in different columns can have complementary layouts or can be staggered, thus reducing mutual heating. Similarly, Figure 16 illustrates a higher density variant of a 16-node system in which nodes are arranged in a similar manner to minimize self-heating across nodes.

The additional cooling concept for brackets for low power servers is to use a pneumatic air pressure differential to establish an upward airflow without the need for a fan. The technique used to do this is to create a sealed stent with an extended vertical exhaust pipe for air. This exhaust pipe must be high enough (about 20-30 呎+) to establish a sufficient air pressure differential to create an upward flow. This provides a fully passive air motion and cooling system for the brackets of low power servers.

Overview/Summary of Cooling of Bracket Mounted Low Power Servers

1. A method for placing a heat dissipating component on a vertically placed mounting board for use in a high density computing system, wherein none of the heat dissipating components are placed directly above or below the other heat dissipating component,

2. As claimed in claim 1, wherein the components are arranged in a substantially diagonal arrangement across the mounting plate.

3. As claimed in claim 1, wherein the components are arranged across several mounting plates in a number of substantially intersecting diagonal arrangements.

4. As claimed in claims 1, 2 and 3, wherein the mounting board is a printed circuit board.

Server organization exchange for non-Ethernet road packets

As described in the patent application Serial No. 12/794,996, the FIG. 17 illustrates the internal architecture of the server node organization switch. Figure 17 illustrates a block diagram of an exemplary switch 900 in accordance with one aspect of the systems and methods disclosed herein. The switch 900 has four associated areas 910a-d. The area 910a corresponds to an Ethernet path packet between the CPU and the internal MAC. The area 910b corresponds to an Ethernet frame at the Ethernet physical interface at the internal MAC, and the area 910b includes a preamble signal, a frame start, and an inter-frame gap field. The area 910c corresponds to an Ethernet frame at the Ethernet physical interface at the external MAC, and the area 910c includes a preamble signal, a frame start, and an inter-frame gap field. Region 910d corresponds to an Ethernet path packet between the processor of routing header 901 and external MAC 904. This segmented MAC architecture is asymmetric. The internal MAC has an Ethernet physical signaling interface that enters the routing header processor, while the external MAC has an Ethernet trunking interface that enters the routing header processor. Therefore, the MAC IP is repurposed for internal MAC and external MAC, and the mechanism that will typically be the physical signaling for the MAC to feed into the switch is utilized. The MAC configuration causes the operating system device driver of the A9 core 905 to manage and control the internal Eth0 MAC 902 and the internal ETH1 MAC 903. The device driver of the management processor 906 manages and controls the internal Eth2 MAC 907. The external Eth MAC 904 is not controlled by the device driver. The MAC 904 is configured in a messy mode to pass all frames without any filtering for network monitoring. The initialization of this MAC is coordinated between the hardware representation of the MAC and any other necessary management processor initialization. The external Eth MAC 904 register is visible to both the A9 905 and the management processor 906 address map. The interrupt signal of the external Eth MAC 904 can be routed to the A9 or management processor.

It is important to note that when receiving a packet from the MAC going to the switch, the route header processor 910d adds the organization route header to the packet, and when receiving the packet from the switch to the MAC, the route header processor 910d Remove the organization route header. The organization switch itself routes only the node ID and other information contained in the organization route header, and the organization switch itself does not perform packet inspection of the original packet.

Decentralized PCIe organization

Figure 18 illustrates a server node that includes a PCIe controller that is connected to an internal CPU bus organization. This allows for the creation of a novel PCIe switching organization that effectively utilizes high-performance, power-optimized server organization to build a scalable, high-performance, power-optimized PCIe organization.

The technology is as follows:

The PCIe controller 902 is coupled to a multiplexer (Mux) 902a that allows the PCIe controller to connect directly to an external PCIe physical layer or to a PCIe routing header processor 910c. When multiplexer 902a is configured to direct PCIe traffic to the local PCIe physical layer, this is equivalent to a standard partial PCIe connection. This enables the novel PCIe decentralized tissue switch mechanism when multiplexer 902a is configured to direct PCIe traffic to PCIe routing header processor 910c.

The PCIe routing header processor 910c uses the embedded routing information (address, ID, or implied) in the packet to establish an organization routing header that maps the PCIe packet route to the destination organization node PCIe control. Device.

This provides similar advantages to a decentralized PCIe organization that the server organization provides to the network.

The PCIe transaction originating from the processor core (905) can be routed to the local PCIe physical layer (via multiplexer bypass or via switch), routed to any other node on the organization, and routed directly to the internal PCIe controller ( 902) or route to an external PCIe controller/entity layer (904).

Similarly, the incoming PCIe transaction enters the external PCIe controller (904), is tagged by the PCIe routing header processor (910) to the organization routing header, and then the organization transmits the PCIe packet to the final destination of the PCIe packet.

Decentralized bus agreement organization

Figure 18a illustrates an additional extension showing the fact that multiple contract bridges can utilize the organization switch to route on the routing header rather than directly on the underlying packet payload (eg, layer 2 Ethernet frame) . In this description, three protocol bridges are illustrated: Ethernet, PCIe, and bus protocol bridge.

The role of the bus protocol bridge is to obtain a processor or internal SOC organization agreement, to encapsulate the processor or internal SOC organization protocol, to add a Calxeda organization route header, and then to route the processor or internal SOC organization protocol via the Calxeda organization.

As a tangible example, consider a bus protocol such as AMBA AXI, HyperTransport, or Fast Path Interconnect (QPI) within the SOC.

Consider the following data flow:

• The processor on the internal SOC bus organization issues a memory load (or store) request.

• The physical address target for memory operations has been mapped to a remote node on the organization.

● Busbar traffic passes through the busbar protocol bridge:

○ Separate bus bar transaction.

○ Map the physical address used for memory transaction to the remote node, which is used when building the route header.

○ The routing frame is constructed by the bus protocol bridge. The bus protocol bridge is composed of a routing header with a remote node ID, and the payload is a sealed bus bar.

● The bus routing message frame passes through the organization switch, passes through the organization, and is received by the frame switch of the target node.

The target node bus bar protocol bridge unpacks the blocked bus bar transaction, sends the bus bar transaction to the target SOC organization, completes the memory load, and returns the result via the same step, and the result flows back to the originating node.

Network processor and server organization integration

Figure 19 illustrates an illustration of integrating the server organization with a network processor (911). There are several usage scenarios for server organization and network processor integration, including:

• The network processor acts as a network packet processing accelerator for the local processor (905) and any other processor on the organization.

• Designed for the Network Processor Center, where the input packets from the external Ethernet are scaled to the network processor and the network processor and control plane processing is offloaded to the larger processor core (905).

● The server organization acts as a communication organization between network processors.

To enable these novel usage conditions, a network address is assigned to the network processor. In the switch architecture shown in Figure 19, there is no routing header processor attached to 1-4. Therefore, agents directly connected to 埠 1-4 need to inject packets that have a tissue switch header that is placed before the payload packet. The network processor adds the organization switch integration to the design of the network processors by:

• Mark the output packet from the network processor to the organization switch header, which encodes the destination node ID from the destination MAC.

● The input packet from the self-organizing switch to the network processor removes the organization switch header before the Ethernet packet is processed.

External device and server organization integration

Figure 19 illustrates an illustration of the integration of the server organization with any foreign device (912). By means of an external device, I mean any processor, DSP, GPU, I/O or communication device or processing device that requires an inter-device communication organization. A typical use case would be a large processing system consisting of DSP or GPU processors that require interconnected fabric organization between DSP or GPU processors.

The organization switch routes the packet based on the organization routing header, and the organization switch does not perform the packet inspection of the packet payload. The packet payload does not have the assumption of being formatted as an Ethernet frame, and the packet payload is considered completely opaque payload.

This allows external devices (eg, DSP or GPU processors) to attach to the organization switch and effectively utilize scalable, high-performance, power-optimized communication organizations by:

• Add the routing frame header containing the destination node ID of the packet to any packet payload sent to the frame switch.

● Strip the routing frame header when the slave frame switch receives the packet.

Load balancing

When considering a tissue topology such as that shown in Figure 5, each of the nodes in the organization outputs at least one MAC address and IP address to provide an external via the gateway node shown in 501a and 501b. Ethernet connectivity.

Exposing such refinement of MAC and IP addresses is advantageous for large-scale network operations using hardware load balancers because the exposure provides a flat list of MAC/IP addresses for the load balancer to compare operations, where the organization The internal structure is not visible to the load balancer.

However, smaller data centers can potentially withstand the potentially large number of new MAC/IP addresses that high-density, low-power servers can provide. It is advantageous to be able to provide options for load balancing to protect the external data center infrastructure from having to process a large number of IP addresses for layers such as network services, respectively.

Consider Figure 20, where we have adopted an FPGA on the organization switch and added an FPGA that provides services such as IP Virtual Server (IPVS). This IP virtualization can be done at the network level including Layer 4 (Transport) and Layer 7 (Application). In many cases, it may be advantageous to load balance at layer 7 for a data center layer, such as a network service, such that the http communication period state can be maintained locally by a particular network server node. Only the IPVS FPGA is attached to the gateway node (nodes 501a and 501b in Figure 5).

In this example, the organization shown in Figure 5 can output a single IP address per gateway node when using IPVS FPGA expansion on the gateway node. The IPVS FPGA then loads the incoming request (eg, HTTP request) into nodes within the organization. In the case of layer 4 load balancing, the IPVS FPGA can proceed statelessly and use an algorithm that includes a loop that crosses the node or exemplifies the maximum number of requests per node before using the next node. In the case of Layer 7 load balancing, the IPVS FPGA will need to maintain state so that the application communication period can be scaled to a particular node.

The resulting process becomes:

• The entry request (eg, an HTTP request) enters the gateway node (埠0) in Figure 20.

The organization switch routing table has been configured to direct incoming traffic from 埠0 to the IPVS FPGA port on the organization switch.

• The IPVS FPGA rewrites the routing header to calibrate specific nodes within the organization, and the IPVS FPGA forwards the resulting packet to the destination node.

The target node processes the request and sends the result out of the gateway node normally.

Open flow/software defined network connection empowerment organization

The open flow is a communication protocol that provides access to the forwarding plane of the switch or router via the network. The path that the open flow allows the network packet to pass through the network of the switch is determined by the software executing on a separate server. This separation of control and forwarding allows for more complex traffic management than is possible with today's ACLs and routing protocols. Open flow is considered an implementation of the general approach to software-defined network connections.

Figure 21 illustrates a method of constructing an OpenFlow (or, more specifically, software defined networking (SDF)) process to be a Calxeda organization. Each of the gateway nodes will instantiate the FPGA on the top of the organization switch that exemplifies the gateway node. Open-flow FPGAs require an out-of-band path to the control plane processor, which can be done by a separate network interface on the OpenFlow FPGA, or can be talked to by another control plane processor that simply leaves the organization switch Come on.

The resulting process becomes:

● Enter the request to enter the gateway node (埠0) in Figure 20.

• The organization switch routing table has been configured to direct incoming traffic from 埠0 to the OpenFlow/SDF FPGA埠 on the organization switch.

• Open Stream/SDF FPGA implements standard open stream processing, including optionally contacting the control plane processor when necessary. The OpenFlow/SDF FPGA rewrites the routing headers to calibrate specific nodes within the organization (by MAC address), and the OpenFlow/SDF FPGA forwards the resulting packets to the destination node.

The target node processes the request and sends the result back to the OpenFlow FPGA where the target node performs any output process processing.

Power optimization organization integrated into standard processor via PCIe

The power optimization server organization illustrated in Figure 5 and previously described provides compelling advantages to existing standard processors, and the power optimization server organization can be used as an integrated wafer solution with existing processing Integration. Standard desktop and server processors typically support the PCIe interface either directly or via an integrated chipset. Figure 22 illustrates an example of a power optimized organization switch integrated into an existing processor via PCIe. Item 22a illustrates a standard processor that supports one or more PCIe interfaces either directly or via an integrated chipset. Item 22b illustrates the disclosed organization switch with an integrated Ethernet MAC controller that has been integrated into the integrated Ethernet MAC controller. Project 22b can typically be integrated using an FPGA or ASIC implementation of a PCIe integrated organization switch.

In the present disclosure, the node shown in FIG. 5 may be a heterogeneous combination of a power optimization server SOC and an integrated organization switch, and an integration of the PCIe connection standard processor to the PCIe interface module. The PCIe interface module includes an Ethernet MAC and an organization switch.

Power optimization organization integrated into standard processor via Ethernet

The power optimization server organization illustrated in Figure 5 and previously described provides compelling advantages to existing standard processors, and the power optimization server organization can be used as an integrated wafer solution with existing processing Integration. Standard desktop and server processors typically support the Ethernet interface via integrated chips or potentially provided within the SOC. Figure 23 illustrates an example of a power optimized organization switch integrated into an existing processor via Ethernet. Item 23a illustrates a standard processor that supports the Ethernet interface via the SOC or via an integrated chip. Item 23b illustrates the disclosed tissue switch without an integrated internal Ethernet MAC controller. Project 23b can typically be integrated together using an FPGA or ASIC implementation of an integrated organization switch.

In the present disclosure, the node shown in FIG. 5 may be a heterogeneous combination of a power optimization server SOC and an integrated organization switch, and an Ethernet connection standard processor to an integrated organization switch. The integration of this disclosure, the integrated organization switch is implemented in an FPGA or ASIC.

While the invention has been described with respect to the specific embodiments of the present invention, it will be understood by those skilled in the art A definition of the scope of the patent application is attached.

9d0, 22a-23b. . . project

9d1. . . Integrated circuit card

9d2. . . a lot of space inside the drive

100. . . Typical network data center architecture

101,104. . . Server node

101a-n. . . Top-level switch

102. . . Standard 2.5" disc drive

102a-n, 203a-c. . . support

103a-f. . . Local router

104e-k. . . Extra server

105. . . system

105a-b. . . Bracket unit

106a-g. . . router

107a-n. . . Blade server

108a-n. . . Additional bracket unit

110. . . Exemplary entity view/aggregation

111a-bn. . . Peripheral server

112a-h. . . Edge router system

113. . . Core switching system

200. . . Network aggregation

201. . . 10-Gb/sec Ethernet communication/thick red line/uplink Ethernet network埠

202. . . Aggregation router

206a-d, 209a. . . server

208a. . . Top-of-rack exchanger

400. . . information Center

401a-n. . . 10-Gb Ethernet physical layer

402. . . 1-Gb dedicated Ethernet physical layer

403a-n. . . Large computer (power server)

404a-n. . . Computer (server)

405. . . Single large low speed fan

406,407,710,720. . . Array

408a, b. . . Historical server

500. . . High-order topology/topology/thermal convection

501a-n. . . Heat flow

501a. . . Node/10 Gb Ethernet 埠Eth0

501b. . . Node/10 Gb Ethernet 埠Eth1

502. . . A printed circuit board

502a-n. . . Oval

502d, e. . . Oval/level 0 leaf node

503a-n. . . Thermal double data rate (DDR) memory chip

504a. . . Large computing chip

506. . . Flash chip

700. . . Exemplary server

701. . . Server board/server/board

701a-n. . . board

702. . . Disc drive

900. . . Exchanger

901. . . Routing header

902. . . Internal Eth0 MAC/PCIe controller/internal PCIe controller

902a. . . Multiplexer

903. . . Internal ETH1 MAC

904. . . External MAC/External Eth MAC/MAC/External PCIe Controller/Solid Layer

905. . . Block / A9 Core / A9 / Processor Core / Local Processor

906. . . Block/management processor

907. . . Internal Eth2 MAC

910a-d. . . Related area

911. . . Network processor

912. . . Foreign device

Figure 1 and Figure 2 illustrate typical data center network aggregation;

Figure 3 illustrates network aggregation using a server in accordance with one embodiment;

Figure 4 illustrates a data center in a stent in accordance with one embodiment;

Figure 5 illustrates a high-level topology of a network system with an exchange organization;

Figure 6 illustrates a server board that constitutes a plurality of server nodes interconnected with the point-to-point interconnect structure;

Figure 6a - Figure 6c illustrate another example of a tissue topology;

Figure 7 illustrates an example of a passive backplane connected to one or more node boards and two polymeric boards;

Figure 8 illustrates an example of an extended tissue crossing the shelf and the link shelf over the server bracket;

Figure 9a illustrates an exemplary server 700 having a disc form factor;

Figures 9b and 9c illustrate an exemplary array of disc-server combinations in accordance with one embodiment, the disc-server combination using a storage server 1-node SATA board;

Figure 9d illustrates a standard 3.5” drive;

Figure 9e illustrates the implementation of a plurality of server nodes in a standard 3.5" disc drive form factor;

Figure 10 illustrates the implementation of a server that is deeply integrated with the storage;

Figure 11 illustrates an implementation of the close packing of the storage and server of an existing 3.5" JBOD storage box;

Figure 12 illustrates the implementation of a server node exemplified in the same form factor of a 2.5" drive;

Figure 13 illustrates the implementation of the bracket chimney cooling;

Figure 13a illustrates an exemplary illustration of the heat convection used in the cooling of the chimney bracket shown in Figure 13;

Figure 14 illustrates server nodes that are placed diagonally relative to one another to minimize self-heating across the server node;

Figure 15 illustrates an exemplary 16-node system in accordance with one embodiment in which heat waves rise from a printed circuit board;

Figure 16 illustrates a higher density variant of a 16-node system having nodes similarly arranged to minimize self-heating across nodes;

Figure 17 illustrates the internal architecture of the server node organization switch;

Figure 18 illustrates a server node that includes a PCIe controller that is coupled to an internal CPU bus organization;

Figure 18a illustrates a system with multiple protocol bridges using a tissue switch;

Figure 19 illustrates the integration of server organization and network processor;

Figure 20 illustrates an organization switch and an FPGA that provides services such as the Internet Protocol Virtual Server (IPVS);

Figure 21 illustrates a method of constructing an OpenFlow process process as a Calxeda organization;

Figure 22 illustrates an example of a power optimized organization switch integrated into an existing processor via PCIe;

Figure 23 illustrates an example of a power optimized organization switch integrated into an existing processor via Ethernet.

200. . . Network aggregation

201. . . 10-Gb/sec Ethernet communication/thick red line/uplink Ethernet network埠

202. . . Aggregation router

203a-c. . . support

206a-d. . . server

208a. . . Top-of-rack exchanger

209a. . . server

Claims (46)

A computing device comprising: a plurality of server nodes interconnected by a plurality of organizational links to form a server organization; and one or more Ethernet escapes, the one or more An Ethernet egress is from the server organization, wherein the one or more Ethernet egress ports are configured to connect the server organization to one or more ports external to the server organization; each of each The server node includes: a processor; a memory; an input/output circuit; and an internal organization switch configured to connect the server node to the server organization and exchange in the server organization Information; wherein the plurality of server nodes are aligned at an angle to accelerate cooling. The computing device of claim 1, further comprising a server board, wherein the plurality of server nodes are portions of the server board. The computing device of claim 1, wherein the computing device further comprises an aggregation of one of a plurality of server boards, wherein each of the server boards includes one or more server nodes of the plurality of server nodes And wherein the set of server boards are interconnected to form a server. Such as the computing device of claim 1 of the patent scope, wherein the internal organizations The switch is configured to exchange routing headers that are attached to the Ethernet Layer 2 packet. The computing device of claim 1, wherein the speed of each of the plurality of organizational links is set to optimize power. The computing device of claim 1, wherein the speed of each of the plurality of organizational links is dynamically adjustable to optimize power. A computing device as in claim 6 wherein the speed is dynamically adjustable based on an instantaneous utilization of a particular tissue link and an average utilization of the one of the particular tissue links. The computing device of claim 3, wherein the one or more organization links of the plurality of organizational links and the one or more Ethernet outlets each comprise a connection to one of the set of server boards Component Interconnect Express (PCIe) connector. The computing device of claim 1, further comprising a passive backplane comprising a point-to-point server interconnect structure. The computing device of claim 1, wherein the server organization has a topology of one tree, and wherein the one or more Ethernet outlets are disposed at each level of the tree. The computing device of claim 1, wherein each of the one or more Ethernet outlets is configured to be configured to match the energized or deactivated One of the optimized power usage is consistent in bandwidth. The computing device of claim 1, wherein the plurality of servers The data between the nodes is configured to be routed in the server organization instead of the one or more Ethernet outlets. The computing device of claim 4, wherein each of the plurality of server nodes is configured to cause the computing component thereon to be disconnected in response to a power reduction. The computing device of claim 2, further comprising a plurality of server boards configured to form one of a bracket and a base plate. The computing device of claim 14, further comprising a plurality of shelves configured to form a stand. A computing device comprising: a storage device of a form factor; and a server node of the shape factor identical to the storage device, wherein the server node comprises: a processor; a memory An input/output circuit; an internal organization switch configured to connect the server node to a network and exchange information in the network; and configured to connect to the storage device One or more Serial Advanced Technology Attachment (SATA) interfaces; wherein the server node is configured to control the storage device, and wherein the server node is aligned at an angle to accelerate cooling. For example, the computing device of claim 16 of the patent scope further An array of storage devices and an array of server nodes are included, wherein the array of server nodes are interconnected. The computing device of claim 16, wherein the server node is disposed in the storage device. The computing device of claim 16, wherein the server node is coupled to the storage device, and wherein the storage device is a local storage for the server node. The computing device of claim 16 further comprising a plurality of storage devices, wherein each of the plurality of storage devices is coupled to one of the one or more SATA interfaces, and wherein The server node is further configured to control the plurality of storage devices. The computing device of claim 16 further comprising a plurality of server nodes and a plurality of storage devices, wherein the plurality of server nodes are interconnected to form a server organization, and wherein the plurality of servers The node is configured to control the plurality of storage devices. The computing device of claim 16, further comprising one or more Ethernet outlets and a link, wherein the one or more Ethernet outlets and the link each comprise a link Peripheral Component Interconnect Express (PCIe) connector. A method for generating a high density computing system, the method comprising the steps of: packaging a server node into a form factor of a disc drive and aligning the server node at an angle to accelerate cooling ,its The server node includes: a processor; a memory; an input/output circuit; an internal organization switch configured to connect the server node to a network and exchange in the network Information; and connecting to one or more Serial Advanced Technology Attachment (SATA) interfaces of the disc drive; and controlling the disc drive by the server node. The method of claim 23, the method further comprising establishing at least one internal switching path on a back plane of one of the disc drive machines. A method for generating a high density computing system, the method comprising the steps of: integrating a server node into a disc drive machine of a standard form factor and aligning the server node at an angle to accelerate cooling Wherein the server node comprises: a processor; a memory; an input/output circuit; an internal organization switch configured to connect the server node to a network and exchange in the network And connecting to one or more Serial Advanced Technology Attachment (SATA) interfaces of the disc drive; and controlling the disc drive by the server node. A computing device comprising: a circuit board; one or more dynamic memory chips mounted on the circuit board; one or more computing chips mounted to the circuit board; and one or more mounted to the circuit board More flash memory chips; and an internal tissue switch configured to connect the circuit board to a network and exchange information in the network; wherein the circuit board is vertically oriented, and wherein One or more flash memory wafers are vertically positioned below the one or more computing wafers, and the one or more dynamic memory wafers are vertically positioned above the one or more computing wafers; and wherein the circuit board, the One or more flash memory wafers and the one or more dynamic memory wafers are aligned at an angle to energize chimney cooling, and wherein the chimney cooling configuration is configured to cool the circuit board. The computing device of claim 26, further comprising a plurality of angled circuit boards, wherein the chimney cooling configuration is configured to cool the plurality of circuit boards having the angle. The computing device of claim 26, the computing device further comprising a fan disposed at a bottom of the circuit board. The computing device of claim 26, further comprising a pneumatic air source and an exhaust pipe. The computing device of claim 26, wherein the one or more dynamic memory wafers are configured to offset the one or more computing wafers in a horizontal direction. The computing device of claim 26, wherein the circuit board comprises a printed circuit board. The computing device of claim 26, wherein the one or more dynamic memory chips, one or more computing wafers, and one or more flash memory wafers are mounted diagonally on the circuit board. A computing device comprising: one or more processors; a busbar organization connected to one of the one or more processors; an internal organization switch, the organization switch being connected to the busbar organization, wherein the An internal organization switch configured to connect the computing device to a network and output data from the computing device to one or more ports; and one or more routing header processors, wherein the one or more routes Each routing header processor of the header processor is configured to route a particular transport stream via the internal organization switch. The computing device of claim 33, wherein the specific transport stream comprises a server transport stream, a memory transport stream, and a network connection transport stream. The computing device of claim 33, the computing device further comprising one or more Ethernet MAC controllers, the one or more Ethernet MAC controllers being connected to the bus organization, wherein the internal A tissue switch is coupled to the one or more Ethernet MAC controllers, and wherein the one or more routing header processors include a Peripheral Component Interconnect Express (PCIe) header processor configured to PCIe data is routed through the internal organization switch. The computing device of claim 33, the computing device further comprising: a PCIe controller connected to the busbar organization; and a PCIe routing header connected to the PCIe controller; wherein the PCIe controller and the The PCIe routing header is connected to a PCIe physical layer (PHY). The computing device of claim 33, the computing device further comprising a network processor coupled to the internal organization switch. The computing device of claim 33, the computing device further comprising an external device coupled to at least one of the one or more ports. A computing device comprising: one or more processors; a busbar organization coupled to one of the one or more processors; an internal organization switch, the internal organization switch being coupled to the busbar organization, wherein The internal organization switch is configured to connect the computing device to a network and output data from the computing device to one or more ports; a bus bar connected between the bus bar organization and the internal switching organization a protocol bridge; and one or more routing header processors, wherein each routing header processor of the one or more routing header processors is configured to route a particular transport stream via the internal organization switch . A method for exchanging different transport streams, the method comprising the steps of: providing a computing device, wherein the computing device comprises: One or more processors; connected to one of the one or more processors; and to an internal organization switch of the bus organization, wherein the internal organization switch is configured to Connecting to a network and outputting data from the computing device to one or more ports; and exchanging a particular transport stream via the internal organization switch by one or more routing header processors. The method of claim 40, wherein the different transport streams comprise a server transport stream, a memory transport stream, and a network connection transport stream. The method of claim 40, the method further comprising routing peripheral component interconnect shortcut (PCIe) data via the internal organization switch. A method of load balancing, the method comprising the steps of: receiving, by a server node, an entry request for load balancing, wherein the server node comprises: one or more processors; connecting to the one or more processes One of the bus organization; is connected to an internal organization switch of the bus organization, wherein the internal organization switch is configured to connect the server node to one of the plurality of server nodes and switch over the plurality of servos Information in the organization of the node; and an IP virtual server connected to one of the internal organization switches; routing the incoming request to the IP virtual server; addressing the address by the IP virtual server Servo One of a particular node in the organization routing a header; the incoming request is forwarded to the particular node by the internal organization switch; and the incoming request is processed by the particular node to provide load balancing. A method for processing using an exchange organization, the method comprising the steps of: receiving, by a server node, an entry request for load balancing, wherein the server node comprises: one or more processors; connecting to the one or One of the more processors, the bus organization; one of the internal organization switches connected to the bus organization, wherein the internal organization switch is configured to connect the server node to one of the plurality of server nodes for organization and switching Information in the organization of the plurality of server nodes; and an Open Flow device connected to the internal organization switch; routing the incoming request to the internal organization switch; generating address by the open flow device Routing a header to one of a particular node of the plurality of server nodes; forwarding the incoming request to the particular node by the internal organization switch; processing the incoming request by the particular node to load balance; and The processed incoming request is sent back to the open flow device by the particular node. A computing device comprising: one or more processors; a busbar organization connected to one of the one or more processors; and an internal organization switch connected to one of the busbar organizations, wherein the internal organization switch Configuring to connect the computing device to a network and output data from the computing device to one or more ports; to connect to a peripheral component interconnect fast (PCIe) interface of the internal tissue switch; The PCIe interface is coupled to an external processor of the computing device, wherein the external processor is configured to route information via the internal organization switch. A computing device comprising: one or more processors; a busbar organization connected to one of the one or more processors; and an internal organization switch connected to one of the busbar organizations, wherein the internal organization switch Configuring to connect the computing device to a network and output data from the computing device to one or more ports; to connect to one of the internal organization switches Ethernet; and via the Ethernet The interface is coupled to an external processor of the computing device, wherein the external processor is configured to route information via the internal organization switch.