TWI539729B - Ac-dc converter and power factor correction circuit thereof - Google Patents

Description

AC-DC converter and its power factor correction circuit

The present invention relates to a converter technology, and more particularly to an AC-DC converter and its power factor correction circuit.

AC-DC converters have been widely used in a variety of electronic products, and the technology continues to improve. In order to improve the efficiency of the AC-DC converter, power factor correction (PFC) is generally added to the AC-DC converter to improve the power factor.

However, the conventional AC-DC converter does not suppress the magnitude of its inductor current, so there is a problem that the peak value of the inductor current is excessive.

The present invention proposes a power factor correction circuit that helps the AC-DC converter to suppress the peak value of its inductor current.

The present invention further provides an AC-DC converter including the above-described power factor correction circuit.

The utility model provides a power factor correction circuit suitable for an AC-DC converter, and the power factor correction circuit comprises: a clock generator, a voltage controlled oscillator, a clock signal selector, a reset signal generating circuit, and a latch And comparator. The clock generator is used to generate the first clock. The voltage controlled oscillator is used to generate the second clock and triangular wave signals. The clock signal selector is configured to receive the first clock and the second time Pulse, and output the first clock and the second clock in the higher frequency. The reset signal generating circuit is configured to generate a reset signal according to a feedback voltage of an output voltage of the AC-DC converter, a first sampling signal of the inductor current of the AC-DC converter, and a triangular wave signal. The latch has a setting end, a reset end and an output end, the setting end is for receiving a clock signal output by the clock signal selector, the reset end is for receiving the reset signal, and the output end is for outputting the pulse width adjustment The variable signal to a control terminal of the switch of the AC-DC converter. The comparator is configured to compare the first sampling signal with the current upper limit signal, and the voltage of the current upper limit signal corresponds to the inductor current threshold, and each time the magnitude of the first sampling signal reaches the inductor current threshold corresponding to the current upper limit signal, the comparator The control voltage controlled oscillator increases the frequency of the second clock and the frequency of the triangular wave signal to be greater than the frequency of the first clock, and controls the voltage controlled oscillator to increase the second according to the number of times the first sampling signal reaches the critical value of the inductor current. The frequency of the clock and triangle wave signals.

The present invention also provides an AC-DC converter comprising: a bridge rectifier, an inductor, a diode, a switch, and a power factor correction circuit as described above. The bridge rectifier has a first AC input terminal, a second AC input terminal, a positive output terminal and a negative output terminal, and the first AC input terminal and the second AC input terminal are coupled to the AC power source. One end of the inductor is coupled to the positive output. The anode of the diode is coupled to the other end of the inductor and its cathode is used as the first voltage output of the AC-DC converter. The switch has a first end, a second end and a control end, the first end is coupled to the other end of the inductor, the second end is coupled to the negative output end, and the negative output end is used as the second voltage output end of the AC-DC converter .

The reset signal generating circuit in the above embodiment includes a voltage error amplifier, a multiplier, a current error amplifier, and a pulse width modulation comparator. The voltage error amplifier is configured to compare the feedback voltage with the reference voltage and generate a first error signal accordingly. The multiplier is configured to generate a reference current signal according to the second sampling signal obtained after the full-wave rectification according to the first error signal and the input voltage of the AC-DC converter. Current error amplifier for comparing reference current signal with first The signal is sampled and a second error signal is generated accordingly. The pulse width modulation comparator is configured to compare the second error signal with the triangular wave signal and generate a reset signal accordingly.

In the present invention, the comparator of the power factor correction circuit controls the frequency of the second clock and the triangular wave signal whenever the size of the first sampling signal reaches the critical value of the inductor current corresponding to the current upper limit signal. The frequency is increased to be greater than the frequency of the first clock, and the voltage controlled oscillator is controlled to increase the frequency of the second clock and the triangular wave signal according to the number of times the first sampling signal reaches the inductor current threshold. Therefore, each time the size of the first sampling signal reaches the critical value of the inductor current corresponding to the current upper limit signal, the frequency of the voltage controlled oscillator is increased to adjust the switching frequency of the switch in a timely manner, thereby reducing the amplitude of the inductor current. The peak value of the inductor current is changed so that the peak value of the inductor current is lower than the current upper limit value.

100‧‧‧AC-DC converter

10‧‧‧Bridge rectifier

11‧‧‧ positive output

12‧‧‧negative output

20‧‧‧Inductance

30‧‧‧ diode

40‧‧‧ switch

41‧‧‧ first end

42‧‧‧second end

43‧‧‧Control terminal

50‧‧‧Power factor correction circuit

51‧‧‧ Clock Generator

52‧‧‧Voltage-controlled oscillator

53‧‧‧clock signal selector

54‧‧‧Reset signal generation circuit

542‧‧‧Voltage error amplifier

544‧‧‧Multiplier

546‧‧‧ Current Error Amplifier

548‧‧‧ Pulse width modulation comparator

55‧‧‧Latch

551, SET‧‧‧Setting end

552, RESET‧‧‧ reset end

553, Q‧‧‧ output

56‧‧‧ comparator

60, 549‧‧‧ capacitor

70‧‧‧Inductor current value

71‧‧‧Average of the inductor current

72‧‧‧Inductance current threshold

80‧‧‧Voltage sampling circuit

90, 91, 92, 93‧‧‧ current sampling circuit

901, 911‧‧‧ current induction coil

902, 912‧‧ ‧ diode

903‧‧‧Rected Waveform Sampling Circuit

AC‧‧‧AC power supply

S ₁ ‧‧‧ current limit signal

S ₂ ‧‧‧first sampling signal

S ₃ ‧‧‧Second sampling signal

S ₅₄ ‧‧‧Reset signal

S ₅₂₂ ‧‧‧ triangle wave signal

S ₅₄₃ ‧‧‧First error signal

S ₅₄₅ ‧‧‧reference current signal

S ₅₄₇ ‧‧‧second error signal

S ₅₇ ‧‧‧ Pulse width modulation signal

CLK1‧‧‧ first clock

CLK2‧‧‧ second clock

V _OUT ‧‧‧ output voltage

V _FB ‧‧‧ feedback voltage

V _REF ‧‧‧reference voltage

R ₁ , R ₂ , R ₃ , R ₄ ‧‧‧ resistance

T1, T2, T3‧‧‧ time zone

GND‧‧‧ Ground potential

1 is a schematic diagram of an AC-DC converter according to an embodiment of the present invention.

2 is a schematic diagram showing changes in inductor current according to an embodiment of the present invention.

FIG. 3 illustrates another embodiment of a current sampling circuit.

Figure 4 illustrates yet another embodiment of a current sampling circuit.

Figure 5 illustrates yet another embodiment of a current sampling circuit.

1 is a schematic diagram of an AC-DC converter according to an embodiment of the present invention. Referring to FIG. 1 , the AC-DC converter 100 includes a bridge rectifier 10 , an inductor 20 , a diode 30 , a switch 40 , a power factor correction circuit 50 , a capacitor 60 , a voltage sampling circuit 80 , a current sampling circuit 90 , and a rectification waveform . Sampling circuit 903.

The bridge rectifier 10 has a first AC input terminal, a second AC input terminal, a positive output terminal 11 and a negative output terminal 12, and the first AC input terminal and the second AC input terminal are coupled to the AC power source AC. One end of the inductor 20 is coupled to the positive output terminal 11 through a current sampling circuit 90. The anode of the diode 30 is coupled to the other end of the inductor 20, and the cathode thereof is used as the first voltage output of the AC-DC converter 100. The switch 40 has a first end 41, a second end 42 and a control end 43, the first end 41 is coupled to the other end of the inductor 20, the second end 42 is coupled to the negative output end 12, and the negative output end 12 is used as an AC A second voltage output of the DC converter 100. In this example, the second voltage output terminal is coupled to the ground potential GND. The switch 40 can be implemented, for example, by an NMOS transistor, wherein the gate of the NMOS transistor is used as the aforementioned control terminal 43. However, the present invention is not limited thereto. Under the principle of circuit operation, the switch 40 can also be implemented in other types, such as a PMOS transistor. In addition, the capacitor 60 is coupled between the first voltage output end and the second voltage output end of the AC-DC converter 100.

The voltage sampling circuit 80 is coupled between the first voltage output terminal of the AC-DC converter 100 and the ground potential to obtain the feedback voltage V _FB . This voltage sampling circuit 80 is implemented with resistors R ₁ and R ₂ . The current sampling circuit 90 is implemented by a current sensing coil 901 and a diode 902. The current sampling circuit 90 is configured to sample the inductor current of the inductor 20 to obtain a first sampling signal S ₂ . The rectified waveform sampling circuit 903 is configured to sample the output signal of the bridge rectifier 10 (that is, the signal generated by the bridge rectifier 10 after full-wave rectification of the input voltage from the AC power source AC) to obtain the second sampling signal. S ₃ . This rectified waveform sampling circuit 903 is realized by resistors R ₃ and R ₄ .

The power factor correction circuit 50 includes a time pulse generator 51, a voltage controlled oscillator 52, a clock signal selector 53, a reset signal generating circuit 54, a latch 55, and a comparator 56. The clock generator 51 is configured to generate the first clock CLK1. The voltage controlled oscillator 52 is used to generate the second clock CLK2 and the triangular wave signal S ₅₂₂ . The clock signal selector 53 is configured to receive the first clock CLK1 and the second clock CLK2, and output the higher frequency of the first clock CLK1 and the second clock CLK2. The reset signal generating circuit 54 is configured to generate the reset signal S ₅₄ according to the feedback voltage V _FB of the output voltage V _OUT of the AC-DC converter 100, the first sampling signal S ₂ of the inductor current of the inductor 20, and the triangular wave signal S ₅₂₂ . . The latching device 55 has a setting end 551, a reset end 552 and an output end 553. The setting end 551 is configured to receive a clock signal output by the clock signal selector 53, and the reset end 552 is configured to receive the reset signal _S54 . The output terminal 553 is configured to output the pulse width modulation signal S ₅₇ to the control terminal 43 of the switch 40, thereby controlling the opening and closing state of the switch 40. The comparator 56 is configured to compare the first sampling signal S ₂ with the current upper limit signal S ₁ , and the comparator 56 controls each time the size of the first sampling signal S ₂ reaches the inductor current threshold corresponding to the current upper limit signal S ₁ . The voltage controlled oscillator 52 increases the frequency of the second clock CLK2 and the frequency of the triangular wave signal S ₅₂₂ to be greater than the frequency of the first clock CLK1, and controls the voltage controlled oscillator 52 to reach the inductor current threshold according to the first sampling signal S ₂ . The number of times increases the frequency of the second clock CLK2 and the triangular wave signal S ₅₂₂ .

In the present embodiment, the reset signal generating circuit 54 includes a voltage error amplifier 542, a multiplier 544, a current error amplifier 546, a pulse width modulation comparator 548, and a capacitor 549. The voltage error amplifier 542 is configured to compare the feedback voltage V _FB with the reference voltage V _REF and accordingly generate a first error signal S ₅₄₃ . The multiplier 544 is configured to generate the reference current signal S ₅₄₅ according to the first error signal S ₅₄₃ and the second sampling signal S ₃ . The current error amplifier 546 is configured to compare the reference current signal S ₅₄₅ with the first sample signal S ₂ and generate a second error signal S ₅₄₇ . The pulse width modulation comparator 548 is configured to compare the second error signal S ₅₄₇ with the triangular wave signal S ₅₂₂ and generate a reset signal S _{54 accordingly} .

In other embodiments, the triangular wave signal S ₅₂₂ generated by the voltage controlled oscillator 52 may be a sawtooth wave signal. Further, the aforementioned latch 55 can be implemented using an SR latch. However, the present invention is not limited thereto, and the latch 55 may be implemented by other types of latches or alternative circuits in accordance with the principle of circuit operation.

2 is a schematic diagram showing changes in inductor current according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2 together. As shown in the time segment T1, when the inductor current of the inductor 20 gradually rises with the change of the voltage, the comparator 56 determines the inductor current value 70 corresponding to the first sample signal S ₂ during this period. It has not yet reached _a peak inductor current threshold value corresponding to the current limit signal S 72, so that the comparator 56 does not control the VCO 52 to increase the frequency of the second clock CLK2 and the triangular wave signal S ₅₂₂ is greater than the first frequency The frequency of the clock CLK1, so the latch 55 generates a lower frequency pulse width modulation signal S _{57 according} to the first clock CLK1 and the reset signal S ₅₄ output by the clock signal selector 53 to utilize the pulse The wide adjustment signal S ₅₇ controls the opening and closing state of the switch 40.

As indicated by time period T2, as the average value of the inductor current (as indicated by reference numeral 71) gradually approaches the inductor current threshold 72, the comparator 56 determines the first sampled signal S ₂ during this period. corresponding to the peak value of the inductor current 70 has reached _a threshold value corresponding to the current inductor current limit signal S 72, so that the comparator 56 to control the voltage controlled oscillator 52 will be the second clock CLK2, the frequency of the triangular wave signal S ₅₂₂ The frequency is increased to be greater than the frequency of the first clock CLK1, so the latch 55 generates a higher frequency pulse width modulation signal according to the second clock CLK2 and the reset signal S ₅₄ output by the clock signal selector 53. S _57, to take advantage of the PWM signal S ₅₇ to increase the switching frequency of the switch 40, so as to reduce the amplitude of the inductor current, thereby suppressing the peak inductor current.

Next, as shown in the time segment T3, when the inductor current of the inductor 20 gradually decreases with the change of the voltage, the comparator 56 determines the inductance corresponding to the first sample signal S ₂ during this period. 70 the peak current value does not reach _a threshold value corresponding to the current inductor current limit signal S 72, so that the comparator 56 does not control the voltage controlled oscillator 52 to the second clock CLK2, the frequency of the triangular wave signal S ₅₂₂ increases the frequency Up to a frequency greater than the frequency of the first clock CLK1, the latch 55 generates a lower frequency pulse width modulation signal S ₅₇ according to the first clock CLK1 and the reset signal S ₅₄ output by the clock signal selector 53. The opening and closing state of the switch 40 is controlled by the pulse width modulation signal S ₅₇ .

Please refer to FIG. 3 to FIG. 5. 3 to 5 illustrate other embodiments of the current sampling circuit, respectively. As shown in FIG. 3, the current sampling circuit 91 is composed of a current sensing coil 911 and a diode 912, and the current sampling circuit 91 is coupled to the current sampling circuit 90 in a different manner. As shown in FIG. 4, the current sampling circuit 92 is implemented by a resistor. As for the current sampling circuit 93 shown in FIG. 5, it is also implemented by a resistor, and the current sampling circuit 93 is coupled to the current sampling circuit 92 in a different manner. Since the coupling manners of the current sampling circuits are clearly illustrated in FIG. 3 to FIG. 5, details are not described herein again.

In summary, in the present invention, whenever the size of the first sampling signal reaches the critical value of the inductor current corresponding to the current upper limit signal, the comparator of the power factor correcting circuit controls the voltage controlled oscillator to the second clock. The frequency and the frequency of the triangular wave signal are increased to be greater than the frequency of the first clock, and the voltage controlled oscillator is controlled to increase the frequency of the second clock and the triangular wave signal according to the number of times the first sampling signal reaches the critical value of the inductor current. Therefore, each time the size of the first sampling signal reaches the critical value of the inductor current corresponding to the current upper limit signal, the frequency of the voltage controlled oscillator is increased to adjust the switching frequency of the switch in a timely manner, thereby reducing the amplitude of the inductor current. The peak value of the inductor current is changed so that the peak value of the inductor current is lower than the current upper limit value. By limiting the inductor current, the inductor is not easily saturated, allowing the use of lower rated inductor components and power switches.

While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧AC-DC converter

10‧‧‧Bridge rectifier

11‧‧‧ positive output

12‧‧‧negative output

20‧‧‧Inductance

30‧‧‧ diode

40‧‧‧ switch

41‧‧‧ first end

42‧‧‧second end

43‧‧‧Control terminal

50‧‧‧Power factor correction circuit

51‧‧‧ Clock Generator

52‧‧‧Voltage-controlled oscillator

53‧‧‧clock signal selector

54‧‧‧Reset signal generation circuit

542‧‧‧Voltage error amplifier

544‧‧‧Multiplier

546‧‧‧ Current Error Amplifier

548‧‧‧ Pulse width modulation comparator

55‧‧‧Latch

551, SET‧‧‧Setting end

552, RESET‧‧‧ reset end

553, Q‧‧‧ output

56‧‧‧ comparator

60, 549‧‧‧ capacitor

80‧‧‧Voltage sampling circuit

90‧‧‧ Current sampling circuit

901‧‧‧current induction coil

902‧‧‧ diode

903‧‧‧Rected Waveform Sampling Circuit

AC‧‧‧AC power supply

S ₁ ‧‧‧ current limit signal

S ₂ ‧‧‧first sampling signal

S ₃ ‧‧‧Second sampling signal

S ₅₄ ‧‧‧Reset signal

S ₅₂₂ ‧‧‧ triangle wave signal

S ₅₄₃ ‧‧‧First error signal

S ₅₄₅ ‧‧‧reference current signal

S ₅₄₇ ‧‧‧second error signal

S ₅₇ ‧‧‧ Pulse width modulation signal

CLK1‧‧‧ first clock

CLK2‧‧‧ second clock

V _OUT ‧‧‧ output voltage

V _FB ‧‧‧ feedback voltage

V _REF ‧‧‧reference voltage

R ₁ , R ₂ , R ₃ , R ₄ ‧‧‧ resistance

GND‧‧‧ Ground potential

Claims (10)

A power factor correction circuit is applicable to an AC-DC converter, the power factor correction circuit includes: a clock generator for generating a first clock; and a voltage controlled oscillator for generating a second clock And a triangular wave signal; a clock signal selector for receiving the first clock and the second clock, and outputting a higher frequency of the first clock and the second clock; and a reset signal is generated a circuit for generating a reset signal according to a feedback voltage of an output voltage of the AC-DC converter, a first sampling signal of an inductor current of the AC-DC converter, and the triangular wave signal; The device has a setting end, a reset end and an output end, wherein the setting end is configured to receive a clock signal output by the clock signal selector, and the reset end is configured to receive the reset signal, and the output end is configured to receive the reset signal a terminal for outputting a pulse width modulation signal to a switch of the AC-DC converter; and a comparator for comparing the first sample signal with a current upper limit signal, the voltage of the current upper limit signal Size corresponds to an inductor a current threshold, and each time the size of the first sampling signal reaches a threshold value of the inductor current corresponding to the current upper limit signal, the comparator controls the frequency of the second clock and the triangular wave of the voltage controlled oscillator The frequency of the signal is increased to be greater than the frequency of the first clock, and the voltage controlled oscillator is controlled to increase the frequency of the second clock and the triangular wave signal according to the number of times the first sampling signal reaches the threshold value of the inductor current. The power factor correction circuit of claim 1, wherein the reset signal generating circuit comprises: a voltage error amplifier for comparing the feedback voltage with a reference voltage, and accordingly generating a first error signal; a multiplier for generating a reference current signal according to the second error signal obtained by the first error signal and an input voltage of the AC-DC converter after full-wave rectification; a current error amplifier for Comparing the reference current signal with the first sampling signal, and generating a second error signal; and a pulse width modulation comparator for comparing the second error signal with the triangular wave signal, and generating the weight accordingly Signal number. The power factor correction circuit of claim 1, wherein the triangular wave signal comprises a sawtooth wave signal. The power factor correction circuit of claim 1, wherein the switch comprises an NMOS transistor, and the control terminal is a gate of the NMOS transistor. The power factor correction circuit of claim 1, wherein the latch comprises an SR latch. An AC-DC converter includes: a bridge rectifier having a first AC input terminal, a second AC input terminal, a positive output terminal and a negative output terminal, the first AC input terminal and the second AC input terminal The input end is coupled to an AC power source; an inductor is coupled to the positive output end at one end thereof; a diode having an anode coupled to the other end of the inductor and a cathode serving as the AC-DC converter a first voltage output terminal; a switch having a first end, a second end, and a control end, the first end coupled to the other end of the inductor, the second end coupled to the negative output end, wherein The negative output is used as a second voltage output terminal of the AC-DC converter; And a power factor correction circuit, comprising: a clock generator for generating a first clock; a voltage controlled oscillator for generating a second clock and a triangular wave signal; and a clock signal selector for Receiving the first clock and the second clock, and outputting a higher frequency of the first clock and the second clock; and a reset signal generating circuit for using the AC-DC converter a feedback voltage of an output voltage, a first sampling signal of an inductor current of the inductor and the triangular wave signal to generate a reset signal; a latch having a setting end, a reset end and an output end, The setting end is configured to receive a clock signal output by the clock signal selector, the reset end is configured to receive the reset signal, and the output end is configured to output a pulse width modulation signal to the control of the switch And a comparator for comparing the first sampling signal with a current upper limit signal, the voltage of the current upper limit signal corresponding to an inductor current threshold, and each time the size of the first sampling signal reaches the current upper limit Corresponding to the signal When the inductor current threshold is used, the comparator controls the voltage controlled oscillator to increase the frequency of the second clock and the frequency of the triangular wave signal to be greater than the frequency of the first clock, and control the voltage controlled oscillator according to The number of times the first sampling signal reaches the threshold value of the inductor current increases the frequency of the second clock and the triangular wave signal. The AC-DC converter of claim 6, wherein the reset signal generating circuit comprises: a voltage error amplifier for comparing the feedback voltage with a reference voltage, and generating a first error signal accordingly a multiplier for determining the first error signal and the AC-DC conversion An input voltage of the device generates a reference current signal after a second sampling signal obtained by full-wave rectification; and a current error amplifier for comparing the reference current signal with the first sampling signal, and generating a first a second error signal; and a pulse width modulation comparator for comparing the second error signal with the triangular wave signal, and generating the reset signal accordingly. The AC-DC converter of claim 6, wherein the triangular wave signal comprises a sawtooth wave signal. The AC-DC converter of claim 6, wherein the switch comprises an NMOS transistor and the control terminal is a gate of the NMOS transistor. The AC-DC converter of claim 6, wherein the latch comprises an SR latch.