TWI538406B - Apparatus and method of pluse width modultion with feedback control - Google Patents

Description

Pulse width modulation device and method with feedback control

The present disclosure relates to a pulse width modulation driving apparatus and method with feedback control.

In the past, analog audio playback was often applied to radios, analog TVs, etc., and the speakers were directly driven by analog signals. With the advancement of technology, the evolution of personal computers and networks, and the development of digital audio signal processing, digital audio playback has been applied to various electronic systems such as cinemas, homes, automobiles, and other digital televisions, various types of computers, walkmans, Mobile phones, etc. Among them, the function of the audio signal processing driver must have low noise and high quality characteristics, which makes the sound effect more perfect and reduces the human-machine interface error rate of some applications.

Some existing audio signal driving techniques have used digital signal processing to improve distortion and noise interference of the front end input audio signal. One technique is as shown in the first figure. The digital interface sorts the digital audio data input by various interface specifications (such as the I2S/SPDIF interface) to output a Pulse Code Modulation (PCM) code, for example, a 24-bit pulse code. Modulation code; this technique then applies the pulse code modulation code to the Up-Sampling and Delta-Sigma Modulator to generate another A pulse code modulation code (PCM-10bit) is then used to drive an external load by converting the output pulse width modulation code to a power driver, such as a Class-D amplifier.

The above method of driving an external load via a power driver with a pulse width modulation code is often because the mode rise/fall time asymmetry of driving an external load, the upper and lower end drive transistor impedances in the power driver are different, and the upper and lower end voltage sources are asymmetric. , causing distortion of the drive audio signal. Therefore, in the architecture of designing an audio signal processing driver, how to design a technique for improving the distortion of the driving audio signal is needed. The present disclosure proposes a pulse width modulation driving technology with feedback control, which can further improve the distortion of the driving audio signal. .

The disclosed embodiments can provide a pulse width modulation apparatus and method with feedback control.

The disclosed embodiment relates to a pulse width modulation device with feedback control for driving an external load, the device comprising a pulse width modulator, a code modulator, a power actuator and a control The pulse width modulator converts the input pulse code modulation code into a pulse width modulation code, and the code converter converts the pulse width modulation code into an upper end signal and a lower end signal, and the power trend The actuator receives the upper end driving signal and the lower end driving signal to drive the external load, the controller measures the voltage of the external load, and generates a control signal according to the upper end driving signal and the lower end driving signal, and the controller transmits the control signal to A coder is used to adjust the upper end signal and the lower end signal.

Another embodiment disclosed is directed to a pulse width modulation method with feedback control for driving an external load, the method comprising: converting a pulse code modulation code of an input into a pulse width modulator a pulse width modulation code, using a coded transducer to convert the pulse width modulation code into an upper end signal and a lower end signal, and using a power actuator to receive the upper end signal and the lower end signal to drive the external a load, a controller measures the voltage of the external load, and generates a control signal according to the upper end signal and the lower end signal, and the controller transmits the control signal to the code adjuster to adjust the upper end signal and the lower end signal .

The above and other advantages of the present disclosure will be described in detail below with reference to the following drawings, detailed description of the embodiments, and claims.

200‧‧‧Pulse width modulation device with feedback control

210‧‧‧ pulse width modulator

211‧‧‧ pulse code modulation code

212‧‧‧ pulse width modulation code

220‧‧‧ Coded Transducer

221‧‧‧Upper moving signal

222‧‧‧ lower end signal

230‧‧‧Power actuator

231‧‧‧Load voltage

240‧‧‧ Controller

250‧‧‧External load

410‧‧‧ pulse width modulation period

420‧‧‧System clock

510‧‧‧Transistor drive circuit

520‧‧‧Upper transistor

530‧‧‧lower transistor

610‧‧ ‧ voltage divider

620‧‧‧potentiometer

621‧‧‧Upper amplitude signal

622‧‧‧lower amplitude signal

630‧‧‧critical comparator

631‧‧‧Upper delay signal

632‧‧‧lower delay signal

710‧‧‧Upper amplitude voltage

720‧‧‧lower amplitude voltage

760‧‧‧Upper rise delay time

770‧‧‧Upper down delay time

780‧‧‧Lower rise delay time

790‧‧‧ Lower end delay time

810‧‧‧ Converting an input pulse code modulation code into a pulse width modulation code using a pulse width modulator

820‧‧‧ Use a coded transducer to convert this pulse width modulation code into an upper end signal and a lower end signal

830‧‧‧Use a power actuator to receive the upper end signal and the lower end signal to drive the external load

840‧‧‧ A controller measures the voltage of the external load, and generates a control signal according to the upper end driving signal and the lower end driving signal

850‧‧‧The controller transmits this control signal to the code converter to adjust the upper end signal and the lower end signal

The first figure is a schematic diagram illustrating an audio signal driving technique using digital signal processing.

The second figure is a schematic view consistent with an embodiment of the disclosure, illustrating a pulse width modulation device with feedback control.

The third figure is a schematic view consistent with an embodiment of the disclosure, illustrating the pulse width modulator of the second figure.

The fourth figure is a schematic diagram consistent with an embodiment of the disclosure, illustrating the waveforms of the upper end signal and the lower end signal.

The fifth figure is a schematic diagram consistent with an embodiment of the disclosure, illustrating that the power actuator receives the upper and lower kinetic signals to drive the external load.

The sixth figure is a schematic diagram consistent with an embodiment of the disclosure, illustrating the controller measuring the voltage of an external load.

7A and 7B are schematic views consistent with an embodiment of the disclosure, illustrating the controller generating a control signal.

The eighth figure is a schematic view consistent with an embodiment of the disclosure, illustrating a pulse width modulation method with feedback control.

The present disclosure proposes a technique of pulse width modulation with feedback control to improve the distortion of the drive audio signal. The second figure is a schematic view consistent with an embodiment of the disclosure, illustrating a pulse width modulation device with feedback control.

The pulse width modulation device with feedback control in the second figure is applied to drive an external load. As shown in the second figure, the device 200 includes a pulse width modulator 210, a code converter 220, and a power. The encoder 230 and a controller 240, wherein the pulse width modulator 210 converts the input pulse code modulation code 211 into a pulse width modulation code 212, and the code converter 220 adjusts the pulse width modulation code 212. Converted into an upper end moving signal 221 and a lower end moving signal 222, the power actuator 230 receives the upper end moving signal 221 and the lower end moving signal 222 to drive the external load 250, and the controller 240 measures the voltage of the external load 250. 231, and a control signal 241 is generated according to the upper end driving signal 221 and the lower end driving signal 222, and the control signal 241 is transmitted to the encoding adjuster 220 to adjust the upper end moving signal 221 and the lower end moving signal 222.

According to an embodiment of the pulse width modulation device with feedback control in the second figure, the pulse width modulator converts the input pulse code modulation code 211 into a pulse width modulation code 212. The third figure is a schematic view consistent with an embodiment of the disclosure, illustrating the pulse width modulator of the second figure. As shown in the third figure, the pulse width modulator can be, for example, but not limited to, a counter, and the input pulse code modulation code 211 is counted according to a system clock to become a pulse width modulation in which the pulse width is proportional to the count. Change code 212.

According to the embodiment in the second figure, the code converter 220 converts the pulse width modulation code 212 into an upper end motion signal 221 and a lower end motion signal 222. The fourth figure is a schematic diagram consistent with an embodiment of the disclosure, illustrating the waveforms of the upper end signal and the lower end signal. As shown in the fourth figure, in a pulse width modulation period 410, the encoder adjuster converts the pulse width modulation code into an upper motion signal 221 and a lower motion signal 222 according to a system clock 420. In the fourth figure, the upper end moving signal 221 has a pulse width corresponding to the pulse width modulation code, and has a free time T between the upper end moving signal 221 and the lower end moving signal 222. The lower end drive signal 222 starts at a time after the vacant time T, and the lower end drive signal 222 ends at a time before the end of the pulse width modulation period 410.

In view of the above, the power actuator 230 receives the upper end actuation signal 221 and the lower end actuation signal 222 to drive the external load 250. The fifth diagram is a schematic diagram consistent with an embodiment of the disclosure, illustrating that the power actuator 230 receives the upper end actuation signal 221 and the lower end actuation signal 222 to drive the external load 250. As shown in the fifth figure, the power actuator 230 includes a transistor driving circuit 510 for driving the received upper end driving signal and the lower end driving signal to drive the external load 250 via an upper transistor 520 and a lower transistor 530. As shown in the fifth figure, an upper transistor 520 and a lower transistor 530 are connected in series with a positive power supply VDD and a negative power supply VEE, wherein the positive power supply VDD is, for example, +100 volts (Volt), and the negative power supply VEE is, for example, - 100 volts (Volt). The upper transistor 520 and the lower transistor 530 are realized, for example, as a Metal-Oxide-Semiconductor (MOS) device.

In view of the above, the controller 240 measures the voltage of the external load 250 to generate a control signal 241. The sixth figure is a schematic diagram consistent with an disclosed embodiment, illustrating control The controller 240 measures the voltage of the external load 250. Referring to the sixth figure, the controller 240 includes a voltage divider 610 and a potential shifter 620 for converting the voltage 231 of the external load 250 into an upper amplitude signal 621 and a lower amplitude signal. 622, as shown in the sixth figure. The controller 240 further includes a threshold comparator 630, and trims the upper end amplitude signal 621 and the lower end amplitude signal 622 into an upper end delay signal 631 and a lower end delay signal 632, respectively.

7A and 7B are schematic views consistent with an embodiment of the disclosure, illustrating controller 240 generating control signal 241. Referring to Figure 7A, the controller measures the amplitude of the upper end amplitude signal 621 and the lower end amplitude signal 622 described above. As shown in FIG. 7A, the controller performs measurement of the upper end amplitude signal 621 at timing T1 to obtain an upper end amplitude voltage 710. The controller also performs a measurement of the lower end amplitude signal 622 at timing T2 to obtain a lower end amplitude voltage 720, which is a negative voltage value. The controller can compare the upper amplitude voltage 710 and the lower amplitude voltage 720 to generate the control signal 241. For example, if the upper amplitude voltage 710 is greater than the absolute value of the lower amplitude voltage 720 by 3 millivolts (mV), the controller can transmit the control signal +3 millivolts (mV) to the coded transducer to adjust the upper end signal, ie, the coded actuator. Decrease the pulse width of the subsequent upper end signal by 3 microseconds (corresponding to +3 millivolts); or the code converter adjusts the lower end signal, ie the coded transducer increases the pulse width of the subsequent lower end signal by 3 micro Seconds (corresponds to +3 millivolts).

In the above, the controller 240 can also generate the control signal 241 according to the upper end driving signal 221 and the lower end driving signal 222. The seventh B diagram illustrates that the controller generates a control signal based on the upper end delay signal and the lower end delay signal. Referring to Figure 7B, the 710 controller compares the upper end delay signal 631 with the upper end motion signal 221 for timing comparison, and the lower end The delay signal 632 and the lower end signal 222 are compared for timing. As shown in FIG. 7B, the timing comparison result can respectively know the upper end delay time 760 and the upper end delay time 770, and the lower end delay time 780 and the lower end delay time 790. The receiver controller can compare the upper end delay time 760 and the upper end delay time 770, and compare the lower end delay time 780 and the lower end delay time 790 to generate the control signal 241. For example, if the upper end delay time is greater than the upper end delay time by 1 microsecond (μs), the controller can transmit the control signal +1 microsecond (μs) to the code converter to adjust the upper end signal, that is, the code converter will follow The pulse width of the upper end signal is increased by 1 microsecond. For example, if the lower end delay time is less than the lower end delay time of 2 microseconds (μs), the controller can transmit the control signal -2 microseconds (μs) to the code converter to adjust the lower end signal, that is, the code converter will follow The pulse width of the lower end of the signal is reduced by 2 microseconds.

According to an embodiment of the disclosure, the controller may further include a memory for storing the control signals in the seventh A picture and/or the seventh B picture, or over a period of time (ie, multiple pulse width modulation) A plurality of control signals obtained by the cycle). The controller may also statistically average the plurality of control signals, and then transmit the averaged control signal to the coded transducer to adjust the upper end signal and the lower end signal.

According to another embodiment, the eighth figure illustrates a pulse width modulation method with feedback control applied to drive an external load. The method includes: converting a pulse coded modulation code of the input into a pulse width modulation code using a pulse width modulator (step 810); converting the pulse width modulation code into an upper end signal using an encoding adjuster And a lower end driving signal (step 820); using a power actuator to receive the upper end moving signal and the lower end moving signal to drive the external load (step 830); And measuring a voltage of the external load, and generating a control signal according to the upper end signal and the lower end signal (step 840); and the controller transmitting the control signal to the code adjuster to adjust the upper end signal and the lower end signal ( Step 850).

As described above, in the eighth diagram, the upper end driving signal has a pulse width corresponding to the pulse width modulation code, and has a free time T between the upper end moving signal and the lower end moving signal. The start time of the lower end drive signal is after the above-described vacant time T, and the end of the lower end drive signal is before the end of the pulse width modulation period. The power actuator comprises a transistor driving circuit for driving the received upper end driving signal and the lower end driving signal to drive an external load via an upper transistor and a lower transistor, wherein the upper transistor and the lower transistor are connected in series with a positive power supply. VDD and a negative power supply VEE, wherein the positive power supply VDD is, for example, +100 volts (Volt), and the negative power supply VEE is, for example, -100 volts (Volt). The upper transistor and the lower transistor are realized, for example, as a Metal-Oxide-Semiconductor (MOS) device.

In the eighth figure, the controller can also convert the voltage of the external load into an upper end amplitude signal and a lower end amplitude signal, and compare the upper end amplitude signal and the lower end amplitude signal to generate a control signal. The controller can also trim the upper end amplitude signal and the lower end amplitude signal into an upper end delay signal and a lower end delay signal, and compare the upper end delay signal and the upper end moving signal, and the lower end delay signal and the lower end moving signal. Timing comparisons are used to obtain the upper end delay time and the upper end delay time, as well as the lower end delay time and the lower end delay time. The controller can also compare the upper end delay time and the upper end delay time, and compare the lower end delay time and the lower end delay time to generate a control signal.

According to an embodiment of the disclosure, the controller may further store the foregoing control signal, or store a plurality of control signals obtained for a period of time for statistical averaging, and then transmit the averaged control signal to the coded transducer to adjust the upper end. The sway signal and the lower end sway signal.

In summary, the present disclosure proposes a technique of pulse width modulation with feedback control to improve the distortion of the driving audio signal.

The above is only the embodiment of the disclosure, and the scope of the disclosure is not limited thereto. All changes and modifications made to the scope of the patent application of the present invention are intended to fall within the scope of the invention.

200‧‧‧Pulse width modulation device with feedback control

210‧‧‧ pulse width modulator

211‧‧‧ pulse code modulation code

212‧‧‧ pulse width modulation code

220‧‧‧ Coded Transducer

221‧‧‧Upper moving signal

222‧‧‧ lower end signal

230‧‧‧Power actuator

231‧‧‧Load voltage

240‧‧‧ Controller

250‧‧‧External load

Claims (14)

A pulse width modulation device with feedback control is applied to drive an external load, the device comprises: a pulse width modulator, converting an input pulse code modulation code into a pulse width modulation code; Converting the pulse width modulation code into an upper end stimulation signal and a lower end actuation signal; a power actuator receiving the upper end actuation signal and the lower end actuation signal to drive the external load; and a controller Measuring a voltage of the external load, and generating a control signal according to the upper end driving signal and the lower end driving signal, and transmitting the control signal to the encoding adjuster to adjust the upper end driving signal and the lower end driving signal Wherein the upper end driving signal has a pulse width corresponding to the pulse width modulation code, and the upper end driving signal and the lower end driving signal have a spare time, and the lower end driving signal starts at the time After the free time, the end drive signal ends at a time before the end of a pulse width modulation period. The device of claim 1, wherein the power actuator comprises a transistor driving circuit to drive the received upper end driving signal and the lower end driving signal via an upper transistor and a lower transistor. The external load. The device of claim 2, wherein the upper transistor and the lower transistor are connected in series with a positive power supply and a negative power supply to drive the external load. The device of claim 2, wherein the upper end transistor and the lower end transistor are metal oxide semiconductor elements. The device of claim 1, wherein the controller converts the voltage of the external load into an upper end amplitude signal and a lower end amplitude signal, and compares the upper end amplitude signal and the lower end amplitude signal to generate the control signal. . The device of claim 5, wherein the controller separately trims the upper end amplitude signal and the lower end amplitude signal into an upper end delay signal and a lower end delay signal to generate the control signal. The device of claim 6, wherein the controller compares the upper end delay signal and the upper end driving signal with a timing comparison, and compares the lower end delay signal with the lower end driving signal for timing comparison, respectively. An upper end delay time and an upper end delay time, and a lower end delay time and a lower end delay time, the controller compares the upper end delay time and the upper end delay time, and compare the lower end delay time and the The lower end delays the delay time to generate the control signal. A pulse width modulation method with feedback control is applied to drive an external load, the method comprising: converting a input pulse code modulation code into a pulse width modulation code by using a pulse width modulator; using an code The transducer converts the pulse width modulation code into an upper end stimulation signal and a lower end actuation signal; using a power actuator to receive the upper end actuation signal and the lower end actuation signal to drive the external load; a voltage of the external load, and generating a control signal according to the upper end driving signal and the lower end driving signal; and the controller transmitting the control signal to the encoding adjuster to adjust the upper end driving signal and the lower end driving signal; Wherein, the upper end of the signal has a pulse width corresponding to the pulse width modulation code, and the upper end driving signal and the lower end driving signal have a spare time, and the lower end driving signal starts at the time of the free time. Thereafter, the lower end drive signal ends at a time before the end of a pulse width modulation period. The method of claim 8, wherein the power actuator comprises a transistor driving circuit, and the received upper end driving signal and the lower end driving signal are passed through an upper transistor and a lower transistor. Drive the external load. The method of claim 9, wherein the upper transistor and the lower transistor are connected in series with a positive power supply and a negative power supply to drive the external load. The method of claim 9, wherein the upper end transistor and the lower end transistor are metal oxide semiconductor elements. The method of claim 8, wherein the controller converts the voltage of the external load into an upper end amplitude signal and a lower end amplitude signal, and compares the upper end amplitude signal and the lower end amplitude signal to generate the control signal. The method of claim 12, wherein the controller separately trims the upper end amplitude signal and the lower end amplitude signal into an upper end delay signal and a lower end delay signal to generate the control signal. The method of claim 13, wherein the controller compares the upper end delay signal and the upper end signal with a timing comparison, and compares the lower end delay signal and the lower end signal with a timing comparison to obtain respectively An upper end delay time and an upper end delay time, and a lower end delay time and a lower end delay time, the controller compares the upper end delay time and the upper end delay time, and compare the lower end delay time and the The lower end delays the delay time to generate the control signal.