TWI536752B - Pulse Compression Method of CHIRP Signal and Its Wireless Signal Transceiver - Google Patents

Description

Pulse compression method for CHIRP signal and wireless signal transceiver thereof

The present invention relates to a pulse compression method for a CHIRP signal (linear frequency modulation signal), and a wireless signal transceiver based on the pulse compression method.

The CHIRP signal is used as a chirp signal, and its instantaneous frequency is expressed by a mathematical formula: f(t)=f ₀ +st 0<t<T

Where f ₀ is the starting frequency of the CHIRP signal, and s is the slope of the frequency change. When s>0, it indicates that the frequency of the CHIRP signal is increasing continuously during the signal period, which is called UP CHIRP (ascending chirp signal); When s<0, it indicates that the frequency of the CHIRP signal is continuously decreasing during the signal period, which is called DOWN CHIRP (descending chirp signal). It can be seen from the above equation that the instantaneous frequency at any moment corresponds to the moment, which is also the inherent law of the CHIRP signal.

In CHIRP signal processing, DDL (Dispersion Delay Line) is widely used to generate CHIRP signals and achieve pulse compression. The conventional DDL (Dispersion Delay Line) is implemented using a SAW (Surface Acoustic Wave) device, and once completed, its parameter characteristics are determined and cannot be adjusted. If a CHIRP signal BT value (B refers to the bandwidth, T refers to the period) requires a higher level, especially when the T value is large, the device The production cost is very high and bulky, and should not be adopted in modern communication systems. The existing digital DDL implementation method usually adopts the digital filter design method, and utilizes two conversion algorithms of DFT and IDFT, which consumes a large amount of machine calculation cycle time resources, has high cost, and is not suitable when the T value is large.

The invention provides a pulse compression method for a CHIRP signal, which solves the technical problem that the calculation period is long when the CHIRP signal is pulse-compressed in the prior art, and the CHIRP signal needs to be synchronized, the system is complicated and the cost is high.

The present invention also proposes a wireless signal transceiver based on the pulse compression method of the above CHIRP signal.

The pulse compression method of the CHIRP signal of the present invention adopts the following technical solution: the pulse compression method of the CHIRP signal, and the CHIRP signals are: C ₁ , C ₂ , C ₃ , ... C _k ... C _K ,1 k K, where K is the number of CHIRP signal cycles that need to be sent to complete a communication; the pulse compression process for the period C _k includes the following steps: S1, analyzing all instantaneous frequency components in the instantaneous signal, and separating each instantaneous frequency component corresponding to the amplitude, to obtain the amplitude and phase of each instantaneous frequency components; S2, open the amplitude and phase of each of the instantaneous frequency component storage space M _n storage step S1 obtained; position order of the storage space M _n corresponding to the sequence of instantaneous frequency components; relative time S3, disposed relative time instantaneous frequency component f _n appearing in the corresponding CHIRP period of t _n, so that the instantaneous frequency component f _n appears t length of time the instantaneous frequency end of the component f cycle _n where _n distance τ _n, by τ _n =Tt _n calculates τ _n ; S4, opens up another storage space M _τ for rearranging the amplitudes of different instantaneous frequency components at each moment in C _k , the order of which is τ _n reference, each instantaneous frequency component f _n amplitude values stored in the space τ _{n M} τ corresponding to the storage space, and all overlapping points in the same space in the storage space _M τ instantaneous frequency Amplitude superimposed on a storage space in the space _M τ; wherein, T is the signal period CHIRP, 0 n N.

In the above-described step S3, the pre-calculation of the τ _n, τ _n and the calculated instantaneous frequency components f _n corresponding to the amplitude and phase arrays stored in the storage space in M _n.

The wireless signal transceiver based on the pulse compression method of the CHIRP signal adopts the following technical scheme: a wireless signal transceiver based on the pulse compression method of the above CHIRP signal, including an interface controller, a power saving controller, an IQ modulator, and an IQ demodulator , band pass filter and transceiver antenna; also includes a microprocessor and an FPGA; the microprocessor is respectively connected with an FPGA, an interface controller and a power saving controller; in the uplink, the FPGA is subjected to an IQ modulator, a band pass filter Connected to the transceiver antenna; in the downlink, the FPGA is connected to the transceiver antenna via an IQ demodulator, a bandpass filter; the microprocessor communicates with the FPGA to implement bidirectional data transmission and send control commands to the FPGA; The CHIRP signal is generated, the CHIRP signal is pulse-compressed, the MAC protocol is analyzed, and the MAC packet is synthesized.

In the above wireless signal transceiver, the FPGA comprises a CHIRP signal generator, a MAC protocol analyzer and a pulse compression processor; the microprocessor is respectively connected with a CHIRP signal generator, a MAC protocol analyzer and a pulse compression processor; In the road, the CHIRP signal generator is connected to the transmitting and receiving antenna via an IQ modulator and a band pass filter; in the downlink, the pulse compression processor is connected to the transmitting and receiving antenna via an IQ demodulator and a band pass filter.

In the above wireless signal transceiver, the wireless signal transceiver further includes a low noise amplifier in the downlink and an amplitude detecting circuit; the low noise amplifier is coupled to a band pass filter for amplifying an output signal of the band pass filter; the amplitude detecting circuit is configured to detect an output amplitude of the low noise amplifier, And implement feedback gain control for low noise amplifiers.

A CHIRP signal generating module that presets a plurality of different BT values in the CHIRP signal generator, correspondingly presets a plurality of pulse compression modules of different BT values in the pulse compression processor, and each of the BT values corresponds to a pulse compression module having an UP The CHIRP compression algorithm and the DOWN CHIRP compression algorithm; the microprocessor and the FPGA use a plurality of BT value combinations to simultaneously perform pulse compression processing on the input CHIRP signal, and generate a compression pulse by a pulse compression module of a BT value that matches the actual CHIRP signal.

The core of the present invention is that the principle of pulse compression processing for CHIRP signals is different from the prior art: first, all frequency components in the transient signal are analyzed, and the amplitude corresponding to each frequency component is separated. The storage space unit is pre-coded in chronological order, and the frequency components and amplitudes obtained by analyzing each time point are stored and superimposed to the corresponding time point according to the inherent frequency of the instantaneous frequency of the CHIRP signal at any time and the time-to-one correspondence. In the unit. When the complete CHIRP signal period is processed, the peak value is accumulated in the storage space, and the pulse compression processing is completed.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

1. The compression processing method of the CHIRP signal of the present invention occupies less machine calculation period, and does not need to synchronize the processed CHIRP signal, thereby reducing the time cost occupied by the CHIRP signal pulse compression process.

2. The compression processing method of the CHIRP signal of the present invention uses the storage space temporary data to process the intermediate result, and the T value of the CHIRP signal corresponds to the size of the storage space occupied; and with the advancement of current semiconductor technology, the large storage space cost is also very low. Therefore, the method of the present invention also reduces the hardware resource cost occupied by the CHIRP signal pulse compression process.

3. The wireless signal transceiver of the present invention is based on the compression processing method of the aforementioned CHIRP signal, and uses FPGA to implement pulse compression, MAC protocol analysis, and CHIRP signal generation; since the compression processing method of the CHIRP signal needs to consume time resources and hardware resources. Rarely, the performance requirements of FPGAs can be lowered, thus reducing the cost of wireless signal transceivers, especially in mass production, the cost advantage becomes more and more obvious.

4. Since the compression processing method of the CHIRP signal of the present invention does not need to achieve synchronization for the CHIRP signal, the complexity of the design of the wireless signal transceiver of the present invention is greatly reduced, and the response speed of the wireless signal transceiver to the CHIRP signal compression processing is also improved.

5. The wireless signal transceiver of the present invention can realize various functions such as a microprocessor, an interface controller and a power saving controller through the FPGA as a whole, and is integrated into a complete transceiver chip (the digital part and the analog part are fully integrated into one) The foundation. The wireless signal transceiver of the invention realizes the processing of the CHIRP signal with small bandwidth and large duration, and can be widely used in the occasions where the data bandwidth requirement is not high but the receiving sensitivity requirement is high, such as tens or even hundreds of kilometers of point-to-point or point. Data transceiving application for multi-point wireless sensors.

C‧‧‧CHIRP signal

K‧‧‧The number of CHIRP signal cycles that need to be sent to complete a communication

K‧‧‧1 number of CHIRP signal cycles between the number of CHIRP signal cycles and the number of K CHIRP signal cycles

T‧‧‧ signal cycle

B‧‧‧Bandwidth

N‧‧‧ total number

Any number between n‧‧‧0 to N

t‧‧‧Time

F‧‧‧ instantaneous frequency component

A‧‧‧Amplitude of instantaneous frequency components

Φ‧‧‧ Phase of instantaneous frequency components

△f‧‧‧frequency accuracy

f _a ‧‧‧A certain frequency

1 is a waveform diagram of UP CHIRP signals; FIG. 2 is a frequency change graph of UP CHIRP signals; FIG. 3 is a schematic diagram of superimposing amplitudes of instantaneous frequency components; and FIG. 4 is a structural block diagram of a wireless signal transceiver.

The present invention will be further described in detail below with reference to the embodiments and the accompanying drawings, but Embodiments of the invention are not limited thereto.

Example

In the CSS (CHIRP SPREAD SPECTRUM) communication system, the transmitter transmits a series of CHIRP signals to the air, which can be expressed as: C ₁ , C ₂ , C ₃ , ... C _k ... C _K , 1 k K, where K is the number of CHIRP signal cycles that need to be sent to complete a communication. Let the period of the CHIRP signal be T and the bandwidth be B.

Figure 1 shows a typical periodic UP CHIRP signal. The UP CHIRP signal has the following characteristics: the amplitude is constant; the frequency varies linearly with time, as shown in Fig. 2, and T is a period, defining t _N = t ₀ + T; the bandwidth of the signal B = f _N - f ₀ . Obviously, when a transceiver receives a specific CHIRP signal, its instantaneous frequency component f _n (0 n N) will appear in chronological order, ie f _n should only be at t _n (0 n N) always appears.

The pulse compression process of the CHIRP signal of the present invention performs different delay operations for different instantaneous frequency components, that is, superimposes the amplitudes of the instantaneous frequency components overlapping in the same storage space, so that different instantaneous frequency components appear in chronological order. An energy superposition is formed which appears as a pulse signal that can be detected.

The pulse compression process of the CHIRP signal of the present invention firstly analyzes and obtains all instantaneous frequency components in the instantaneous signal, and separates the amplitude corresponding to each instantaneous frequency component to obtain an amplitude and phase array of each instantaneous frequency component. The method of obtaining the instantaneous frequency component of the transient signal is not limited to a specific mode, but various general methods can be employed; for example, in the present embodiment, the FFT fast Fourier transform algorithm is used. The result of the FFT transformation is an array of the amplitude and phase of each instantaneous frequency component. Table 1 shows the amplitude and phase array of each instantaneous frequency component at a certain time.

M _n is then stored in the storage space in the above Table I the instantaneous amplitude and phase of each frequency component of the array. Positional order storage M _n corresponding to the order of individual instantaneous frequency components above, that is: f0 the amplitude and the phase stored in the M _0; amplitude and phase of f ₁ is stored in the M _1; amplitude and phase of f ₂ is stored in M ₂ ; ......, f _n stored in the amplitude and phase of M _n; the sequential storage positions corresponding relationship between the M _n of the respective components of the instantaneous frequency is represented as a table, compared to the two shown.

The accuracy of the instantaneous frequency components that can be obtained by discrete digital processing techniques is limited by the sampling frequency and the calculation speed. Assuming the frequency accuracy is Δf, there are: f ₀ = Δff ₁ = f ₀ + Δff ₂ = f ₁ + Δff ₃ = f ₂ + Δf ...... f _N = f _N-1 + △f

When a certain frequency is f _a and there is: f _n-1 When f _a <f _n , the amplitude and phase corresponding to n=1, 2, 3, ..., N+1, f _a will be stored in the Mn _-1 space corresponding to f _n-1 .

In CSS communication, the characteristics of the transmitted CHIRP signal are artificially set and agreed by the transmitting and receiving parties in advance. That is, in any one of the CHIRP periods _Ck , the relative timing at which a certain instantaneous frequency component appears is determinable. In other words, when the receiver analyzes the received signal and finds that there is a certain instantaneous frequency component f _n , the instantaneous frequency component can be determined at the relative time t _n corresponding to the CHIRP period. Let τ _n denote the _length of time at which the instant t _{n of} the instantaneous frequency component f _n appears from the end of the period in which the instantaneous frequency component f _n is located, and τ _n , 0 is calculated by τ _n = Tt _n n N,. M _n in the storage space, the τ _n frequency components f _n with instantaneous amplitude and phase of the corresponding storage array, shown in Table III as follows:

When the receiver starts processing the received signal at any time, it processes the signal at a certain time t _n of a certain period C _k of the CHIRP signals. After the receiver performs the instantaneous frequency analysis calculation, the instantaneous frequency component f _n and the amplitude A _{n of the} signal at the moment are obtained, and the τ _n corresponding to the instantaneous frequency component f _{n is} obtained through calculation. In the actual algorithm, τ _n by the equation pre τ _n = Tt _n considered good, in the presence of the three table array in accordance with the instantaneous frequency components f _n by three lookup table to find the corresponding τ _n.

Then, a storage space M _τ is additionally opened in the storage unit for rearranging the amplitudes of different instantaneous frequency components at each moment in C _k ; the arrangement order is referenced to τ _{n , that} is, the amplitude value of each instantaneous frequency component f _n is stored. In the space of the storage space M _τ corresponding to τ _n . If two or more instantaneous frequency components just overlap in the same space of the storage space M _τ , their amplitudes are superimposed as shown in FIG. 3 . In theory, the instantaneous frequency component f _{n in} C _k will appear successively in chronological order (ascending UP CHIRP or descending DOWN CHIRP), and the receiving end will overlap all in the same space of the storage space M _τ according to the above algorithm. The amplitudes of the instantaneous frequency components are all superimposed in an accumulation space of the storage space M _τ . If the value of M _τ is plotted in chronological order, it appears as a very high peak pulse.

The above process completes the pulse compression of the CHIRP signal. Repeating the above process in a repeated manner, the pulse compression of the CHIRP signal of the complete sequence of C _K can be completed, and then the numerical peak value is accumulated in the accumulation space of the storage space M _τ to complete the pulse compression processing. After the pulse peak identification, the modulated signal can be restored to complete the data communication.

The wireless signal transceiver based on the pulse compression method of CHIRP signal, the principle block diagram shown in Figure 4, mainly includes FPGA (field programmable gate array), microprocessor, interface controller, power saving controller, storage, IQ Modulator, IQ demodulator, bandpass filter and transceiver antenna. The FPGA includes a CHIRP signal generator, a MAC protocol analyzer, and a pulse compression processor. The microprocessor is connected to the CHIRP signal generator, the MAC protocol analyzer, the pulse compression processor, the interface controller, the power saving controller and the storage respectively; in the uplink (transmission link), the CHIRP signal generator is subjected to the IQ modulator The band pass filter is connected to the transceiver antenna; in the downlink (receiving link), the pulse compression processor is connected to the transceiver antenna via an IQ demodulator and a band pass filter. The storage unit or storage space in the pulse compression method of the CHIRP signal of the present invention may, but need not, be placed in the storage of the aforementioned wireless signal transceiver; in fact, it may be placed in a storage unit built into the FPGA.

Choosing a larger BT value in CHIRP communication can achieve a larger spread spectrum increase. beneficial. When the small signal processing unit in wireless communication has a large spread spectrum gain, the signal receiving sensitivity is greatly improved, so that the useful signal buried in the noise can be recognized. The CHIRP signal pulse compression method of the patent of the present invention is used in the design of the transceiver, and the ideal actual result is obtained. Performing pulse compression on the CHIRP signal will result in a spread spectrum gain. The magnitude of the gain is closely related to the frequency variation range B of the CHIRP signal and the duration T of a single period of the CHIRP signal. The present invention focuses on adapting the need for spread spectrum gain by changing T, while controlling B to a small level and supplementing the appropriate filter to suppress external noise from entering the receiver. Specifically, it can be designed as follows:

The B value (ie, the frequency bandwidth of the CHIRP signal) is fixed in advance, and only the duration T of the CHIRP signal (ie, the period of the CHIRP signal) needs to be changed, and the BT value can be changed; that is, by changing the duration T to obtain different BT. The value, ie the preset several different BT values, has substantially the same B value. In the FPGA, several CHIRP signal generation modules with different BT values are preset in the CHIRP signal generator, and correspondingly, several pulse compression modules with different BT values are preset in the pulse compression processor, and each BT value corresponds to The pulse compression module has UP CHIRP compression algorithm and DOWN CHIRP compression algorithm. According to the compression principle of the pulse compression method of the present invention, the UP CHIRP compression algorithm only compresses the UP CHIRP signal into a pulse, and the DOWN CHIRP signal is processed into a low noise, distributed throughout the signal period, without generating a pulse; and vice versa . Also, according to the compression principle of the pulse compression method of the present invention, the UP CHIRP compression algorithm and the DOWN CHIRP compression algorithm of the specific BT value are only sensitive to the CHIRP signal of the specific BT value, that is, only the CHIRP signal that matches the pulse compression BT value is compressed. A pulse can be generated during the process.

In the actual application system, in the process of the first communication, the devices at both ends of the communication try to transmit data with different BT value CHIRP signals, and then determine the BT value by measuring the signal to noise ratio. The design principle of the invention is to obtain the highest band under the premise of ensuring reliable communication. Width, that is, the minimum BT value is chosen; in order to avoid excessive BT value, the transmission data bandwidth is sacrificed while obtaining better receiving sensitivity.

In Figure 4, the working tasks of the FPGA are mainly the generation of CHIRP signals, pulse compression processing, MAC protocol analysis, and MAC packet synthesis. The microprocessor communicates with the FPGA to realize bidirectional data transmission and send control instructions to the FPGA to complete selection control of the aforementioned FPGA work tasks. The operating state of the FPGA informs the microprocessor through the change of the pin level of the device. When the device is powered on, the microprocessor sends a transceiving enable command to the FPGA according to the task: when the task needs to send data, the microprocessor goes to the FPGA. Send the "send" control command, and then send it to the FPGA to send the data; after receiving the command and data, the FPGA packs the data into the MAC data frame that needs to be sent, and then converts the data into one through the CHIRP signal generator inside the FPGA. The string CHIRP pulse is output and sent out to the antenna for transmission through various conversion circuit units. When the task needs to receive data, the microprocessor sends a “receive” control command to the FPGA, and the FPGA then starts the pulse compression processing flow, and the slave receiving circuit Extracting the data signal, the FPGA performs MAC protocol analysis on the received data signal (usually a string of data consisting of “0” and “1”), unpacks the protocol frame into useful data, and then transmits it to the microprocessor for subsequent processing. deal with. The microprocessor simultaneously controls the interface controller so that the transceiver communicates with peripheral related sensors or actuators, including digital I/O channels, analog input channels (A/D conversion), USB interfaces, and the like. The power-saving controller accepts the control of the microprocessor, allowing the device to work in several different power supply state modes to achieve the overall low-power characteristics of the transceiver, such as: full-featured transceiver (normal mode), only receiving part of the power supply (detection) Listening mode), only the interface controller works (hold mode), only the microprocessor works (standby mode), only the memory is powered (hibernate save mode), and so on.

The frequency variation range (i.e., bandwidth) B and duration (i.e., period) T of the CHIRP signal generated by the CHIRP generator are selected and varied by the FPGA based on control signals from the microprocessor to obtain different spreading gains. Its digital modulation code also occurs by CHIRRP The device is completed. The CHIRP signal generated by the CHIRP generator is a series of digital quantities, which are parallel outputs and are divided into I channel and Q channel. The IQ channel data is digital-to-analog converted to analog and sent to the IQ modulator to form a high-frequency signal. Then, the bandpass filter and the mixer are converted into radio frequency signals, and then sent to the air through the power amplifier, the radio frequency switch, and the like.

In the receiving part, the received airborne RF signal is first processed by a bandpass filter to remove out-of-band clutter. It is then amplified by a low noise amplifier LNA. The protection measure for the LNA is also designed, that is, the amplitude detection circuit is used to detect the output amplitude of the LNA, and realize the feedback gain control of the LNA to ensure that the LNA is always in a linear working state to reduce the signal-to-noise ratio degradation. The RF signal is then sent to the mixer, and the IF signal is output, which is amplified and filtered and sent to the IQ demodulator to separate the analog signal of the IQ channel. Here, a variable gain amplifier and low-pass filtering are arranged to process the analog signal, filter out the out-of-band clutter, and improve the dynamic range.

The analog-to-digital converted IQ channel signal is sent to the FPGA for pulse compression processing. The innovative software technology algorithms of this patent will be used here. The microprocessor and FPGA in the wireless signal transceiver will use a combination of multiple BT values to simultaneously perform pulse compression processing on the input CHIRP signal. Only the pulse compression algorithm of the BT value that matches the actual CHIRP signal will have a compression pulse generated, that is, A compression pulse is generated by a pulse compression module of the BT value that coincides with the actual CHIRP signal. The obtained pulse corresponds to the bit, and the data string is continuously processed, and then the actual valid data is obtained through MAC protocol analysis. The microprocessor fully controls the various processing processes of the FPGA, obtains the correct data, and completes the transceiving task.

The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and combinations thereof may be made without departing from the spirit and scope of the invention. Simplifications should all be equivalent replacements and are included in the scope of the present invention.

Claims (10)

A pulse compression method for CHIRP signals, wherein the CHIRP signals are: C ₁ , C ₂ , C ₃ , ... C _k ... C _K , 1 k K, where K is the number of cycles of the CHIRP signal to be transmitted to complete a communication, and k is the number of cycles of any CHIRP signal from one CHIRP signal cycle to K CHIRP signal cycles; characterized by a period C _k The pulse compression processing comprises the following steps: S1, analyzing all instantaneous frequency components in the instantaneous signal, and separating the amplitude corresponding to each instantaneous frequency component to obtain the amplitude and phase of each instantaneous frequency component; S2, opening up the storage space M _n the storage step S1 to obtain the amplitude and phase of each of the instantaneous frequency components; position order of the storage space M _n corresponding to the sequence of instantaneous frequency components; S3, provided the instantaneous frequency component f _n corresponding relative time CHIRP period appears to t _n, so that the instantaneous frequency component f _n occurring at time tn relative length from the end of the instantaneous frequency component f _n where cycle time τ _n, obtained by _n [tau] _n [tau] is calculated _n = Tt; S4, open for other storage space _M τ rearranging the instantaneous amplitude of different frequency components in the respective time C _k, τ _n is the order to reference the instantaneous amplitude value of each frequency component f _n stored in the corresponding τ _n Storage space _M τ, the magnitude of all of the overlapping and in the same space in the storage space _M τ instantaneous frequency components superimposed on a storage space in the space _M τ; wherein, T is the signal period CHIRP, 0 n N; where N represents the total number and n represents any number between 0 and N. The pulse compression method of the CHIRP signal according to claim 1, wherein in step S3, the τ _n is pre-calculated, and the calculated τ _{n is} stored in correspondence with the amplitude and phase array of the instantaneous frequency component f _n M _n of the storage space. The CHIRP pulse request signal compression method of Item 2, wherein the τ _n frequency components f _n with instantaneous amplitude and phase of the corresponding array of M _n stored in the storage space and forming the following form: Find the corresponding τ _n based on the instantaneous frequency component f _n ; Φ represents the phase and A represents the amplitude. The pulse compression method of the CHIRP signal according to claim 1, wherein in step S1, the amplitude and phase of each instantaneous frequency component are obtained by using an FFT fast Fourier transform algorithm. A wireless signal transceiver for a pulse compression method of a CHIRP signal according to any one of claims 1 to 4, comprising an interface controller, a power saving controller, an IQ modulator, an IQ demodulator, a band pass filter, and a transceiver The antenna is characterized in that it further comprises a microprocessor and an FPGA; the microprocessor is respectively connected with an FPGA, an interface controller and a power saving controller; in the uplink, the FPGA is subjected to an IQ modulator, a band pass filter and a transmitting and receiving antenna. In the downlink, the FPGA is connected to the transceiver antenna via an IQ demodulator, a bandpass filter, and the microprocessor communicates with the FPGA to implement bidirectional data transmission and send control instructions to the FPGA; the FPGA is used to generate CHIRP signal, pulse compression processing, MAC protocol analysis and MAC packet synthesis for CHIRP signals. The wireless signal transceiver of claim 5, wherein the FPGA comprises a CHIRP signal generator, a MAC protocol analyzer, and a pulse compression processor; the microprocessor and the CHIRP signal generator, the MAC protocol analyzer, and the pulse compression processing, respectively. Connection; in the uplink, CHIRP The signal generator is connected to the transceiver antenna via an IQ modulator and a band pass filter; in the downlink, the pulse compression processor is connected to the transceiver antenna via an IQ demodulator and a band pass filter. The wireless signal transceiver of claim 5, wherein the wireless signal transceiver further comprises a low noise amplifier disposed in the downlink and an amplitude detecting circuit; the low noise amplifier being coupled to the band pass filter for amplifying The output signal of the band pass filter; the amplitude detecting circuit is used for detecting the output amplitude of the low noise amplifier, and implementing feedback gain control of the low noise amplifier, so that the low noise amplifier is always in a linear working state. The wireless signal transceiver according to claim 6, wherein a CHIRP signal generating module that presets a plurality of different BT values in the CHIRP signal generator, correspondingly presets a plurality of pulse compression modules of different BT values in the pulse compression processor The pulse compression module corresponding to each BT value is provided with a UP CHIRP compression algorithm and a DOWN CHIRP compression algorithm; the microprocessor and the FPGA use a plurality of BT value combinations to simultaneously perform pulse compression processing on the input CHIRP signal, and the actual CHIRP The pulse compression module of the BT value of the signal coincidence produces a compression pulse. The wireless signal transceiver of claim 8, wherein in the pulse compression module of the plurality of different BT values, a UP CHIRP compression algorithm and a DOWN CHIRP compression algorithm are provided in the pulse compression module corresponding to each BT value. The wireless signal transceiver of claim 8, wherein the plurality of different BT values have the same B value; wherein B represents a bandwidth.