TWI536501B - Method for fabricating memory device - Google Patents

Description

Memory element manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a memory device.

Memory can be divided into two types: volatile memory (Volatile memory) and non-volatile memory (Non-volatile memory). Volatile memory will disappear after the power supply is interrupted. The non-volatile memory will not disappear after the power supply is interrupted. After re-powering, it will be able to Read the data in the memory. Therefore, non-volatile memory can be widely used in electronic products, especially portable products.

As the integration of the memory elements increases and the size is reduced, in order to ensure that the plurality of memory cells are electrically isolated from each other, a plurality of isolation structures and dielectric layers must be formed, and the plurality of isolation structures and dielectric layers It must be formed through multiple complex lithography processes, which may cause mis-alignment between the isolation structure and the dielectric layer and increase process variation. Therefore, there is a great need for a manufacturing method that simplifies the process to fabricate memory components and mitigate alignment errors.

The invention provides a method for manufacturing a memory element, which can simplify the process to reduce the variation of the process and reduce the cost of the process.

The present invention provides a method of fabricating a memory device, the steps of which include providing a substrate having a first region and a second region. A stacked layer is formed on the substrates of the first region and the second region, and the stacked layer includes a storage layer, a first conductor layer, and a first mask layer. Then, the stacked layers are patterned to form a plurality of first patterned stacked layers, the first patterned stacked layers extending along the first direction, extending from the first region to the second region, each first patterned The stacked layers each have an opening on each side. Next, a filling layer is formed on the substrate, and the filling layer is filled in the opening. A second mask layer is formed on the first region of the substrate, and the second mask layer does not cover the fill layer of the second region. Thereafter, the first patterned stacked layer and the partial substrate in the second region are removed by using the filling layer as a mask to form a plurality of trenches in the substrate of the second region.

In an embodiment of the invention, after the trench is formed, the method further includes removing the filling layer to expose the surface of the first patterned stacked layer of the first region. Then, a plurality of buried dielectric layers are formed in the openings between the first patterned stacked layers of the first region, and a plurality of isolation structures are formed in the trenches of the second region. Next, the first mask layer is removed to expose the surface of the first conductor layer. Thereafter, a second conductor layer extending in the second direction is formed on the substrate, and each of the first patterned stacked layers of the first region is patterned into a plurality of second patterned stacked layers.

In an embodiment of the invention, the method of removing the above-described filling layer includes a dry etching method or a wet etching method.

In an embodiment of the invention, the buried dielectric layer and the isolation structure are formed simultaneously.

In an embodiment of the invention, the method for forming the buried dielectric layer and the isolation structure includes forming a dielectric material layer on the substrate, and the dielectric material layer is filled in the first patterned stacked layer of the first region. Among the openings between the openings, and filled in the trenches of the second zone, and covering the first mask layer. Then, the first mask layer is used as a stop layer to remove the dielectric material layer on the first mask layer.

In an embodiment of the invention, the material of the filling layer is different from the material of the first mask layer.

In an embodiment of the invention, the material of the filling layer comprises a fluid material.

In an embodiment of the invention, the fluid material comprises a photoresist or an organic dielectric material.

In an embodiment of the invention, the method for forming the filling layer comprises a spin coating method, a high density plasma chemical vapor deposition (HDPCVD) method or an enhanced high aspect ratio process (eHARP). .

In an embodiment of the invention, before forming the filling layer, further comprising forming a buried doping region in each of the substrates on both sides of each of the first patterned stacked layers, the buried doping region along The first direction extends.

Based on the above, the present invention can be used as a mask for etching trenches by using a filling layer, after which a buried dielectric layer and an isolation structure can be simultaneously formed. In this way, the manufacturing method of the memory element of the present invention can simplify the process, thereby reducing the process variation and reducing the cost of the process.

The above described features and advantages of the invention will be apparent from the following description.

1A-1K are top views of a manufacturing process of a memory device according to an embodiment of the invention. 2A to 2K are schematic cross-sectional views taken along line II-II' of Figs. 1A to 1K, respectively. 3A to 3K are schematic cross-sectional views taken along line III-III' of Figs. 1A to 1K, respectively. Figure 4 is a schematic cross-sectional view taken along line IV-IV' of Figure 1K.

Referring to FIG. 1A, FIG. 2A and FIG. 3A, first, a stacked layer 11 is formed in the substrate 10. The substrate 10 has a first region R1 and a second region R2 (as shown in FIG. 1A). In an embodiment, the first zone R1 may be, for example, an active zone; and the second zone R2 may be, for example, a perimeter zone. The substrate 10 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide.

Next, a stacked layer 11 is formed on the substrate 10 of the first region R1 and the second region R2. The stacked layer 11 includes a storage layer 12 (eg, a high dielectric constant material), a first conductor layer 14 (eg, as a control gate), and a first mask layer 16. In an embodiment, the storage layer 12 can be, for example, a composite layer composed of a tunneling dielectric layer, a charge storage layer, and a barrier layer. For example, the composite layer may be composed of an oxide layer/nitride layer/oxide layer (Oxide-Nitride-Oxide, ONO), which may be three or more layers, and the invention is not limited thereto, and the formation method thereof may be It is a chemical vapor deposition method, a thermal oxidation method, or the like.

The material of the first conductor layer 14 is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof can be formed by chemical vapor deposition. The material of the first mask layer 16 is, for example, a tantalum material or a metal material. The material of the first mask layer 16 of the present invention is not limited thereto as long as the material of the first mask layer 16 has a high etching selectivity ratio with the material of the substrate 10, the storage layer 12, and the first conductor layer 14.

Referring to FIGS. 1B, 2B, and 3B, the stacked layers 11 are patterned to form a plurality of patterned stacked layers 11a. The patterned stacked layer 11a extends along the first direction D1, extending from the first region R1 to the second region R2. Each of the patterned stacked layers 11a has an opening 18 on each side. In one embodiment, the patterning method may utilize a lithography and etching process to remove portions of the first mask layer 16, a portion of the first conductor layer 14, and a portion of the storage layer 12, such that each patterned layer 11a The side is formed with an opening 18 exposing the surface of the substrate 10 (as shown in Figure 1B). The patterned stacked layer 11a includes a first mask layer 16a, a first conductor layer 14a, and a storage layer 12a. The etching process may be a dry etching method such as a sputtering etching method or a reactive ion etching method.

Thereafter, a buried doping region 100 is formed in each of the substrates 10 on both sides of each of the patterned stacked layers 11a. Specifically, an ion implantation process is performed to form the buried doped region 100 in the exposed substrate 10 of the opening 18. In other words, the buried doped region 100 is located in the substrate 10 exposed by the openings 18 on either side of each patterned stacked layer 11a. The buried doped region 100 extends along the first direction D1 and extends from the first region R1 to the second region R2. In an embodiment, the substrate 10 has a first conductivity type; the buried doped region 100 has a second conductivity type. The first conductivity type is, for example, a P type; the second conductivity type is, for example, an N type, and vice versa. In an embodiment, the doping implanted in the buried doping region 100 is, for example, phosphorus or arsenic, and the doping dose is, for example, 1.0 ^{́10 15} /cm ² to 3.0 ^{́10 15} /cm ² , implanted. The energy is, for example, 10 keV to 20 keV.

Referring to FIG. 1C , FIG. 2C and FIG. 3C , a filling layer 110 is formed on the substrate 10 , and the filling layer 110 is filled in the opening 18 . The fill layer 110 of the present invention is different in material from the first mask layer 16 and has a high etch selectivity ratio with the first mask layer 16. The material of the fill layer 110 includes a fluid material. The fluid material can be a photoresist or an organic dielectric material. The material of the filling layer 110 of the present invention is not limited thereto as long as it has a high filling property and can be filled with a structure having a high aspect ratio. The formation method of the filling layer 110 is, for example, a spin coating method, a high-density plasma method, or an enhanced high aspect ratio groove filling process. In an embodiment, the thickness T1 of the filling layer 110 above the first mask layer 16 is, for example, 100 nm to 500 nm.

Next, a second mask layer 20 is formed on the first region R1 of the substrate 10. The second mask layer 20 does not cover the fill layer 110 of the second region R2. The material of the second mask layer 20 is, for example, a carbon or photoresist type material or the like. The method of forming the second mask layer 20 is, for example, a spin coating method. In an embodiment, the anti-reflective layer 19 may be further included. The anti-reflection layer 19 is located on the filling layer 110 of the first region R1 and the second region R2. The anti-reflective layer 19 of the first region R1 is located between the second mask layer 20 and the filling layer 110. The anti-reflection layer 19 of the second region R2 is exposed. The material of the anti-reflection layer 19 is, for example, an organic polymer, carbon or bismuth oxynitride or the like. The material of the anti-reflection layer 19 is different from the material of the second mask layer 20, and is formed by, for example, a spin coating method or a chemical vapor deposition (CVD) method.

1D, 2D, and 3D, with the second mask layer 20 of FIGS. 1C, 2C, and 3C as a mask, the anti-reflective layer 19 and the partially filled layer 110 of the second region R2 are removed. To expose the top surface of the first mask layer 16 of the second region R2. In detail, in order to ensure that the filling layer 110 of the top surface of the first mask layer 16 of the second region R2 can be completely removed, during the etching process, an over etching method is performed, so that the second The top surface of the fill layer 110 in the opening 18 of the region R2 will be slightly lower than the top surface of the first mask layer 16 of the second region R2. The removal method may be a dry etching method such as a sputtering etching method or a reactive ion etching method. Next, the second mask layer 20 is removed. In one embodiment, the second mask layer 20 may be removed by first patterning the second mask layer 20 with high density plasma ashing, followed by a wet cleaning process.

Referring to FIG. 1E, FIG. 2E and FIG. 3E, the anti-reflective layer 19 and the filling layer 110 of FIGS. 1C, 2C and 3C are used as a mask to remove the patterned stacked layer 11a of the second region R2 and a portion of the substrate below it. 10, a plurality of trenches 22 are formed in the substrate 10 of the second region R2 (FIGS. 1D, 2D, and 3D). Referring to FIG. 3D , the filling layer 110 is located above the buried doping region 100. Therefore, when the filling layer 110 is used as an etching mask layer, the trench 22 can be formed by self-aligning the region not covering the filling layer 110 without The problem of misalignment occurs due to the multi-pass lithography process. Therefore, the trench 22 can be referred to as a Self-Aligned Contact Region. The filling layer 110 on the first mask layer 16a has a sufficient thickness T1, and thus, even in the process of removing the patterned stacked layer 11a of the second region R2 and a portion of the substrate 10, although resistant to the first region R1 The reflective layer 19 and the partially filled layer 110 are also removed at the same time, however, a portion of the filled layer 110 may remain, covering the top surface of the first mask layer 16a of the first region R1 (FIG. 1E and FIG. 2E). Therefore, the first mask layer 16a of the first region R1 is not subjected to etching damage.

Referring to FIG. 1F, FIG. 2F and FIG. 3F, the filling layer 110 is removed, the surface of the patterned stacked layer 11a of the first region R1 is exposed, and the buried blend of the first region R1 and the second region R2 is exposed. Miscellaneous area 100. The method of removing the filling layer 110 includes a dry stripping method or a wet stripping method. The dry stripping method is, for example, a sputtering etching method or a reactive ion etching method. The wet stripping method is performed by, for example, etching using a mixed solution of hydrofluoric acid, nitric acid, and hydrofluoric acid or hot phosphoric acid (150 ° C to 200 ° C).

Referring to FIGS. 1G, 2G, and 3G, a dielectric material layer 24 is formed on the substrate 10. The dielectric material layer 24 is filled in the opening 18 of the first region R1 and filled in the trench 22 of the second region R2 and covers the first mask layer 16a. The material of the dielectric material layer 24 is, for example, ruthenium oxide. The cerium oxide is, for example, a spin-on dielectric (SOD), a high-density plasma oxide (HDP Oxide), or an oxide layer formed by an enhanced high aspect ratio trench filling process.

Referring to FIG. 1H, FIG. 2H and FIG. 3H, the first mask layer 16a is used as a stop layer, and the dielectric material layer 24 on the first mask layer 16a is removed to simultaneously form a patterned stack in the first region R1. A plurality of buried dielectric layers 24a are formed in the openings 18 between the layers 11a, and a plurality of isolation structures 24b are formed in the trenches 22 of the second region R2. The method of removing the dielectric material layer 24 on the first mask layer 16a is, for example, a chemical mechanical polishing process. The top surface of the buried dielectric layer 24a and the top surface of the first mask layer 16a may be coplanar, or the top of the buried dielectric layer 24a due to over-polishing relationship. The face is slightly lower than the top surface of the first mask layer 16a.

Referring to FIGS. 1I, 2I, and 3I, the first mask layer 16a is removed to expose the surfaces of the first conductor layer 14a, the buried dielectric layer 24a, and the isolation structure 24b. The method of removing the first mask layer 16a includes a wet etching method. The wet etching method is performed, for example, using hot phosphoric acid.

Referring to FIGS. 1J, 2J, and 3J, the second conductor layer 28 and the mask layer 30 are sequentially formed on the substrate 10. In an embodiment, the material of the second conductor layer 28 is, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof may utilize a chemical vapor deposition method. The thickness of the second conductor layer 28 is, for example, 500 angstroms to 1000 angstroms.

Referring to FIG. 1K, FIG. 2K, FIG. 3K and FIG. 4, the mask layer 30 and the second conductor layer 28 are patterned by lithography and etching to form a plurality of masks extending in the second direction D2 on the substrate 10. The curtain layer 30a and the plurality of second conductor layers 28a (for example, as word lines) continue to etch the first conductor layer 14a of the first region R1 to form the first conductor layer 14b. The etching method can be performed by a dry etching method such as a sputtering etching method or a reactive ion etching method. The storage layer 12a includes a storage layer 12b covered by the first conductor layer 14b and a storage layer 12c not covered by the first conductor layer 14a. The first conductor layer 14b and the storage layer 12b constitute a plurality of patterned stacked layers 11b. A plurality of patterned stacked layers 11b are located on the substrate 10 of the first region R1. A buried dielectric layer 24a is disposed between each patterned stacked layer 11b such that a plurality of patterned stacked layers 11b are electrically isolated from each other. In an embodiment, it may form an N x N matrix.

Since the filling layer 110 is highly filled and has characteristics of easy coating and removal, the present invention can fill the filling layer 110 between the second patterned stacked layers 11a (FIG. 3C). Moreover, since the filling layer 110 and the first mask layer 16a have a high etching selectivity ratio, they can be used as a mask layer to form the trench 22 in the substrate 10 (Fig. 3E). After the filling layer 110 is removed, a dielectric material layer 24 is formed on the substrate 10, and after chemical mechanical polishing or etch back, the isolation structure 24b can be formed in the trenches 22, and simultaneously in the patterned stacked layer 11b. A buried dielectric layer 24a is formed (Figs. 2G, 3G, 2H, 3H).

Referring to FIG. 1K, FIG. 2K, FIG. 3K and FIG. 4, the memory element of the embodiment of the present invention includes a plurality of second conductor layers 28a (for example, as word lines), a plurality of patterned stacked layers 11b, A plurality of buried dielectric layers 24a, a plurality of buried doped regions 100, and a plurality of isolation structures 24b. A plurality of buried doped regions (eg, as bit lines) 100 are located on the first region R1 and the second region R2 of the substrate 10, which extend along the first direction D1. The second conductor layer 28a is located on the first region R1 and extends along the second direction D2 across the buried doping region 100. Below each of the second conductor layers 28a is a plurality of patterned stacked layers 11b. Each of the patterned stacked layers 11b includes a storage layer 12b and a first conductor layer 14b. The buried dielectric layer 24a extends along the first direction D1 and is located on the first region R1 and the second region R2 and above the buried doping region 100. Each of the buried dielectric layers 24a on the first region R1 separates the adjacent two patterned stacked layers 11b. The buried dielectric layer 24a on the second region R2 is connected to the isolation structure 24b on both sides of the buried doping region 100 in the substrate 10 to form a unitary structure.

In summary, the filling layer formed on the buried doped region (for example, as a bit line) can be used as a mask for etching the trench, so that the trench can be self-aligned and formed in the buried type. Both sides of the doped region. Moreover, the process method can simultaneously form a buried dielectric layer and an isolation structure by using a simple lithography process, a deposition process, and a planarization process without requiring multiple lithography processes. Therefore, the manufacturing method of the memory element of the present invention has a simplified process to achieve the effects of reducing process variation and reducing process cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base
11‧‧‧Stacking
11a, 11b‧‧‧ patterned stacking layers
12, 12a, 12b, 12c‧‧‧ storage layer
14, 14a‧‧‧ first conductor layer
16, 16a‧‧‧ first cover layer
18‧‧‧ openings
19‧‧‧Anti-reflective layer
20‧‧‧Second cover layer
22‧‧‧ Ditch
24‧‧‧ dielectric material layer
24a‧‧‧ Buried dielectric layer
24b‧‧‧Isolation structure
28, 28a‧‧‧Second conductor layer
30, 30a‧‧ ‧ cover layer
100‧‧‧Buried doped area
110‧‧‧ fill layer
R1, R2‧‧‧
D1, D2‧‧‧ direction
T1‧‧‧ thickness

1A-1K are top views of a manufacturing process of a memory device according to an embodiment of the invention. 2A to 2K are schematic cross-sectional views taken along line II-II' of Figs. 1A to 1K, respectively. 3A to 3K are schematic cross-sectional views taken along line III-III' of Figs. 1A to 1K, respectively. Figure 4 is a schematic cross-sectional view taken along line IV-IV' of Figure 1K.

10‧‧‧Base

11b‧‧‧Second patterned stack

12b‧‧‧ storage layer

14b‧‧‧First conductor layer

24a‧‧‧ Buried dielectric layer

28a‧‧‧Second conductor layer

30a‧‧‧ Cover layer

100‧‧‧Buried doped area

Claims (10)

A method of manufacturing a memory device, comprising: providing a substrate having a first region and a second region; forming a stacked layer on the substrate of the first region and the second region, the stacked layer including a a storage layer, a first conductor layer and a first mask layer; patterning the stacked layer to form a plurality of first patterned stacked layers, the first patterned stacked layers extending along a first direction Extending from the first region to the second region, each of the first patterned stacked layers has an opening on each side thereof; forming a filling layer on the substrate, the filling layer filling the openings; Forming a second mask layer on the first region of the substrate, the second mask layer not covering the filling layer of the second region; and removing the layer in the second region by using the filling layer as a mask The first patterned stacked layer and a portion of the substrate form a plurality of trenches in the substrate of the second region. The method of manufacturing the memory device of claim 1, wherein after the trenches are formed, the method further comprises: removing the filling layer to expose surfaces of the first patterned stacked layers of the first region Forming a plurality of buried dielectric layers in the openings between the first patterned stacked layers of the first region, and forming a plurality of isolation structures in the trenches of the second region; Removing the first mask layer to expose a surface of the first conductor layer; and forming a second conductor layer extending in a second direction on the substrate, and forming each first pattern of the first region The stacked layers are patterned into a plurality of second patterned stacked layers. The method of manufacturing a memory element according to claim 2, wherein the method of removing the filling layer comprises a dry etching method or a wet etching method. The method of fabricating a memory device according to claim 2, wherein the buried dielectric layers and the isolation structures are formed simultaneously. The method of manufacturing the memory device of claim 2, wherein the step of forming the buried dielectric layer and the isolation structures comprises: forming a dielectric material layer on the substrate, the dielectric material a layer is filled in the openings between the first patterned stacked layers of the first region, and filled in the trenches of the second region, and covers the first mask layer And removing the layer of dielectric material on the first mask layer with the first mask layer as a stop layer. The method of manufacturing a memory device according to claim 1, wherein the material of the filling layer is different from the material of the first mask layer. The method of manufacturing a memory element according to claim 6, wherein the material of the filling layer comprises a fluid material. The method of manufacturing a memory device according to claim 7, wherein the fluid material comprises a photoresist or an organic dielectric material. The method of manufacturing a memory device according to claim 7, wherein the method for forming the filling layer comprises a spin coating method including a spin coating method, a high-density plasma method, or an enhanced high aspect ratio trench filling process. The method for manufacturing a memory device according to claim 1, further comprising: forming a buried doping in the substrate on each side of each of the first patterned stacked layers before forming the filling layer a region, the buried doped region extends along the first direction.