TWI536177B - Selecting and setting system for peripheral component interconnect express and microserver - Google Patents

Selecting and setting system for peripheral component interconnect express and microserver Download PDF

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TWI536177B
TWI536177B TW102146701A TW102146701A TWI536177B TW I536177 B TWI536177 B TW I536177B TW 102146701 A TW102146701 A TW 102146701A TW 102146701 A TW102146701 A TW 102146701A TW I536177 B TWI536177 B TW I536177B
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peripheral interconnection
interconnection standard
selection signal
standard
shortcut
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TW102146701A
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TW201525721A (en
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方蘭蘭
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英業達股份有限公司
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Description

快捷外設互聯標準的選擇設定系統及微伺服器 Fast peripheral interconnection standard selection setting system and micro server

一種選擇設定系統及微伺服器,尤其是指一種快捷外設互聯標準的選擇設定系統及微伺服器。 A selection setting system and a micro server, in particular, a selection setting system and a micro server for a fast peripheral interconnection standard.

快捷外設互聯標準(PCI-E)的傳輸控制是透過快捷外設互聯標準控制晶片進行設置,一般是透過strapping signals進行設置,但是在實際使用上,由於快捷外設互聯標準控制晶片一次只能設置一個快捷外設互聯標準埠作為上游快捷外設互聯標準埠,並沒有辦法同時配置多個上游快捷外設互聯標準埠,而由於上游快捷外設互聯標準埠不會同時進行連接,故無法同時將上游快捷外設互聯標準埠進行使能(enable)或是禁能(disable)。 The Fast Peripheral Interconnect Standard (PCI-E) transmission control is set by the fast peripheral interconnect standard control chip, which is usually set by strapping signals, but in actual use, the standard peripheral control chip can only be controlled once. Setting up a fast peripheral interconnection standard as an upstream fast peripheral interconnection standard, there is no way to configure multiple upstream fast peripheral interconnection standards at the same time, and since the upstream fast peripheral interconnection standard is not connected at the same time, it cannot simultaneously The upstream fast peripheral interconnection standard is enabled or disabled.

當需要同時進行上游快捷外設互聯標準埠的使能(enable)或是禁能(disable)設置時,則必須要使用多個快捷外設互聯標準控制晶片才能達到同時對上游快捷外設互聯標準埠的使能(enable)或是禁能(disable)設置,但這會使得製造成本的增加,故需要對此進一步加以改善。 When it is necessary to simultaneously enable the enable or disable setting of the upstream fast peripheral interconnection standard, it is necessary to use multiple fast peripheral interconnection standard control chips to achieve the simultaneous upstream and external peripheral interconnection standards.埠Enable or disable settings, but this will increase the manufacturing cost, so it needs to be further improved.

綜上所述,可知先前技術中長期以來一直存在以單一快捷外設互聯標準控制晶片無法同時配置上游快捷外設互聯標準埠的問題,因此有必要提出改進的技術手段,來解決此一問題。 In summary, it can be seen that in the prior art, there has been a long-standing problem that the control chip cannot be configured with the upstream fast peripheral interconnection standard by a single fast peripheral interconnection standard. Therefore, it is necessary to propose an improved technical means to solve this problem.

有鑒於先前技術存在以單一快捷外設互聯標準控制晶片無法同時配置上游快捷外設互聯標準埠的問題,本發明遂揭露一種快捷外設互聯標準的選擇設定系統及微伺服器,其中: In view of the prior art, there is a problem that the control chip can not simultaneously configure the upstream fast peripheral interconnection standard by a single fast peripheral interconnection standard. The present invention discloses a selection and setting system and a micro server for a fast peripheral interconnection standard, wherein:

本發明所揭露的快捷外設互聯標準的選擇設定系統,其包含:快捷外設互聯標準控制晶片、至少一儲存器以及選擇控制器。 The invention relates to a selection and setting system of a shortcut peripheral interconnection standard, which comprises: a shortcut peripheral interconnection standard control chip, at least one storage device and a selection controller.

快捷外設互聯標準控制晶片是用以產生第一選擇訊號;每一個儲存器與快捷外設互聯標準控制晶片電性連接,且每一個儲存器中儲存有一個配置設定;及選擇控制器是用以接收第一選擇訊號以生成多個第二選擇訊號,每一個第二選擇訊號分別對應連接儲存器其中之一,以控制儲存器中配置設定對快捷外設互聯標準控制晶片進行配置。 The fast peripheral interconnection standard control chip is used to generate the first selection signal; each of the storage and the shortcut peripheral interconnection standard control chip is electrically connected, and each storage device stores a configuration setting; and the selection controller is used The first selection signal is received to generate a plurality of second selection signals, and each of the second selection signals respectively corresponds to one of the connection storages to control the configuration settings in the storage to configure the shortcut peripheral interconnection standard control chip.

本發明所揭露的徹伺服器(microserver),其包含:至少一系統單晶片(System On Chip,SOC)、快捷外設互聯標準控制晶片、至少一儲存器以及選擇控制器。 The microserver disclosed in the present invention comprises: at least one system on chip (SOC), a shortcut peripheral interconnect standard control chip, at least one memory, and a selection controller.

每一個系統單晶片具有第一快捷外設互聯標準(PCI-E)埠;快捷外設互聯標準控制晶片具有多個第二快捷外設互聯標準埠,第二快捷外設互聯標準埠與第一快捷外設互聯標準埠分別對應進行電性連接,且快捷外設互聯標準控制晶片產生第一選擇訊號;每一個儲存器與快捷外設互聯標準控制晶片電性連接,且每一個儲存器中儲存有一個配置設定;及選擇控制器是用以接收第一選擇訊號以生成多個第二選擇訊號。 Each system single chip has a first fast peripheral interconnection standard (PCI-E) 埠; a fast peripheral interconnection standard control chip has a plurality of second shortcut peripheral interconnection standards 埠, a second shortcut peripheral interconnection standard 埠 and the first The fast peripheral interconnection standard is respectively connected to the electrical connection, and the fast peripheral interconnection standard control chip generates the first selection signal; each of the storage and the shortcut peripheral interconnection standard control chip is electrically connected, and each storage is stored in the storage device. There is a configuration setting; and the selection controller is configured to receive the first selection signal to generate a plurality of second selection signals.

其中,每一個第二選擇訊號分別對應連接儲存器其中之一,以控制儲存器中配置設定對快捷外設互聯標準控制晶片進行配置,配置設定用以選擇第二快捷外設互聯標準埠其中之一設置為上游(upstream)快捷外設互聯標準埠,其於的第二快捷外設互聯標準埠不進行上游快捷外設互聯標準埠設置,被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠與第一快捷外設互聯標準埠電性連接以進行數據傳輸。 Each of the second selection signals respectively corresponds to one of the connection storages, and controls the configuration settings in the storage to configure the standard peripheral control chip of the shortcut peripheral interconnection, and the configuration setting is used to select the second shortcut peripheral interconnection standard. Once set as the upstream (upstream) fast peripheral interconnection standard, its second fast peripheral interconnection standard does not set the upstream fast peripheral interconnection standard setting, and is set as the second shortcut of the upstream fast peripheral interconnection standard. The Peripheral Interconnect Standard is electrically connected to the first Fast Peripheral Interconnect standard for data transmission.

本發明所揭露的微伺服器(microserver),其包含:至少一系統單晶片(System On Chip,SOC)、快捷外設互聯標準控制晶片、至少一儲存器以及選擇控制器。 The microserver disclosed in the present invention comprises: at least one system on chip (SOC), a shortcut peripheral interconnect standard control chip, at least one memory, and a selection controller.

每一個系統單晶片具有第一快捷外設互聯標準(PCI-E)埠;快捷外設互聯標準控制晶片具有多個第二快捷外設互聯標準埠,第二快捷外設互聯標準埠與第一快捷外設互聯標準埠分別對應進行電性連接,且快捷外設互聯標準控制晶片產生第一選擇訊號;每一個儲存器與快捷外設互聯標準控制晶片電性連接,且每一個儲存器中儲存有一個配置設定;及選擇控制器與每一個系統單晶片分別電性連接,以接收第一選擇訊號與每一個系統單晶片產生的控制訊號以生成第二選擇訊號,且每一個第二選擇訊號與每一個系統單晶片相互對應。 Each system single chip has a first fast peripheral interconnection standard (PCI-E) 埠; a fast peripheral interconnection standard control chip has a plurality of second shortcut peripheral interconnection standards 埠, a second shortcut peripheral interconnection standard 埠 and the first The fast peripheral interconnection standard is respectively connected to the electrical connection, and the fast peripheral interconnection standard control chip generates the first selection signal; each of the storage and the shortcut peripheral interconnection standard control chip is electrically connected, and each storage is stored in the storage device. There is a configuration setting; and the selection controller is electrically connected to each system single chip to receive the first selection signal and the control signal generated by each system single chip to generate a second selection signal, and each second selection signal Corresponding to each system single chip.

其中,每一個第二選擇訊號分別對應連接儲存器其中之一,以控制儲存器中配置設定對快捷外設互聯標準控制晶片進行配置,配置設定用以選擇第二快捷外設互聯標準埠其中之一設置為上游(upstream)快捷外設互聯標準埠,其於的第二快捷外設互聯標準埠不進行上游快捷外設互聯標準埠設置,被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠與第一快捷外設互聯標準埠電性連接以進行數據傳輸。 Each of the second selection signals respectively corresponds to one of the connection storages, and controls the configuration settings in the storage to configure the standard peripheral control chip of the shortcut peripheral interconnection, and the configuration setting is used to select the second shortcut peripheral interconnection standard. Once set as the upstream (upstream) fast peripheral interconnection standard, its second fast peripheral interconnection standard does not set the upstream fast peripheral interconnection standard setting, and is set as the second shortcut of the upstream fast peripheral interconnection standard. The Peripheral Interconnect Standard is electrically connected to the first Fast Peripheral Interconnect standard for data transmission.

本發明所揭露的系統與微伺服器如上,與先前技術之間的差異在於本發明是透過選擇控制器接收第一選擇訊號以生成多個第二選擇訊號,每一個第二選擇訊號分別對應連接儲存器其中之一,以控制儲存器中配置設定對快捷外設互聯標準控制晶片進行配置,配置設定用以選擇第二快捷外設互聯標準埠其中之一設置為上游快捷外設互聯標準埠,其於的第二快捷外設互聯標準埠不進行上游快捷外設互聯標準埠設置,被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠與第一快捷外設互聯標準埠電性連接以進行數據傳輸。 The system and the micro-server disclosed in the present invention are different from the prior art in that the present invention receives the first selection signal through the selection controller to generate a plurality of second selection signals, and each of the second selection signals is respectively connected. One of the storages is configured to control the configuration of the storage device to configure the standard peripheral control chip for the fast peripheral interconnection, and the configuration setting is used to select the second shortcut peripheral interconnection standard, one of which is set as the upstream fast peripheral interconnection standard, The second fast peripheral interconnection standard is not set up by the upstream fast peripheral interconnection standard, and is set as the second fast peripheral interconnection standard of the upstream fast peripheral interconnection standard 埠 and the first fast peripheral interconnection standard 埠Electrically connected for data transmission.

誘過上述的技術手段,本發明可以達成以單一快捷外設互聯標準控制晶片配置多個快捷外設互聯標準埠其中之一為上游快捷外設互聯標準埠,以對與快捷外設互聯標準控制晶片電性互連的多個系統單晶片其中之一進行數據傳輸的技術功效。 By inducing the above technical means, the present invention can achieve a single fast peripheral interconnection standard control chip configuration of multiple fast peripheral interconnection standards, one of which is the upstream fast peripheral interconnection standard 埠, to standardize the interconnection with the fast peripherals The technical effect of data transmission in one of a plurality of system single wafers electrically interconnected by the wafer.

10‧‧‧快捷外設互聯標準控制晶片 10‧‧‧Fast Peripheral Interconnect Standard Control Wafer

11‧‧‧第二快捷外設互聯標準埠 11‧‧‧Second Fast Peripheral Interconnect Standard埠

12‧‧‧第二快捷外設互聯標準埠 12‧‧‧Second Fast Peripheral Interconnect Standard埠

13‧‧‧第二快捷外設互聯標準埠 13‧‧‧Second Fast Peripheral Interconnect Standard埠

14‧‧‧第二快捷外設互聯標準埠 14‧‧‧Second Fast Peripheral Interconnect Standard埠

21‧‧‧第一儲存器 21‧‧‧First storage

22‧‧‧第二儲存器 22‧‧‧Second storage

23‧‧‧第三儲存器 23‧‧‧ third storage

24‧‧‧第四儲存器 24‧‧‧ fourth storage

30‧‧‧選擇控制器 30‧‧‧Select controller

31‧‧‧第一跳針 31‧‧‧First jumper

311‧‧‧第一接腳 311‧‧‧First pin

312‧‧‧第二接腳 312‧‧‧second pin

32‧‧‧第二跳針 32‧‧‧Second jumper

321‧‧‧第一接腳 321‧‧‧First pin

322‧‧‧第二接腳 322‧‧‧second pin

33‧‧‧第三跳針 33‧‧‧ Third jump stitch

331‧‧‧第一接腳 331‧‧‧First pin

332‧‧‧第二接腳 332‧‧‧second pin

34‧‧‧第四跳針 34‧‧‧fourth jumper

341‧‧‧第一接腳 341‧‧‧First pin

342‧‧‧第二接腳 342‧‧‧second pin

41‧‧‧第一邏輯閘 41‧‧‧First Logic Gate

42‧‧‧第二邏輯閘 42‧‧‧Second logic gate

43‧‧‧第三邏輯閘 43‧‧‧ Third Logic Gate

44‧‧‧第四邏輯閘 44‧‧‧fourth logic gate

51‧‧‧第一選擇訊號 51‧‧‧First choice signal

521‧‧‧第二選擇訊號 521‧‧‧second choice signal

522‧‧‧第二選擇訊號 522‧‧‧second choice signal

523‧‧‧第二選擇訊號 523‧‧‧second choice signal

524‧‧‧第二選擇訊號 524‧‧‧second choice signal

53‧‧‧第三選擇訊號 53‧‧‧ Third choice signal

61‧‧‧電源 61‧‧‧Power supply

62‧‧‧接地 62‧‧‧ Grounding

71‧‧‧第一系統單晶片 71‧‧‧First system single chip

711‧‧‧第一快捷外設互聯標準埠 711‧‧‧The first fast peripheral interconnection standard埠

72‧‧‧第二系統單晶片 72‧‧‧Second system single chip

721‧‧‧第一快捷外設互聯標準埠 721‧‧‧The first fast peripheral interconnection standard埠

73‧‧‧第三系統單晶片 73‧‧‧ Third system single chip

731‧‧‧第一快捷外設互聯標準埠 731‧‧‧The first fast peripheral interconnection standard埠

74‧‧‧第四系統單晶片 74‧‧‧fourth system single chip

741‧‧‧第一快捷外設互聯標準埠 741‧‧‧The first fast peripheral interconnection standard埠

第1圖繪示為本發明快捷外設互聯標準的選擇設定系統的系統架構圖。 FIG. 1 is a system architecture diagram of a selection setting system for a fast peripheral interconnection standard according to the present invention.

第2圖繪示為本發明快捷外設互聯標準的選擇設定系統的選擇控制器架構示意圖。 FIG. 2 is a schematic diagram showing the structure of a selection controller of the selection and setting system of the shortcut peripheral interconnection standard of the present invention.

第3圖繪示為本發明微伺服器的第一實施態樣系統架構圖。 FIG. 3 is a block diagram showing the system configuration of the first embodiment of the microserver according to the present invention.

第4圖繪示為本發明微伺服器的第二實施態樣系統架構圖。 FIG. 4 is a structural diagram of a second embodiment of the microserver according to the present invention.

以下將配合圖式及實施例來詳細說明本發明的實施方式,藉此對本發明如何應用技術手段來解決技術問題並達成技術功效的實現過程能充分理解並據以實施。 The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, so that the application of the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

以下首先要說明本發明所揭露的快捷外設互聯標準的選擇設定系統,並請同時參考「第1圖」以及「第2圖」所示,「第1圖」繪示為本發明快捷外設互聯標準的選擇設定系統的系統架構圖;「第2圖」繪示為本發明快捷外設互聯標準的選擇設定系統的選擇控制器架構示意圖。 The following is a description of the selection and setting system of the shortcut peripheral interconnection standard disclosed in the present invention, and please refer to "1" and "2", and "1" is shown as a shortcut peripheral of the present invention. The selection of the interconnection standard sets the system architecture diagram of the system; "Fig. 2" shows the architecture of the selection controller architecture of the selection and setting system of the shortcut peripheral interconnection standard of the present invention.

本發明所揭露的快捷外設互聯標準的選擇設定系統,其包含:快捷外設互聯標準控制晶片10、第一儲存器21、第二儲存器22、第三儲存器23、第四儲存器24以及選擇控制器30,其中選擇控制器30更包含:第一跳針31、第二跳針32、第三跳針33、第四跳針34、第一邏輯閘41、第二邏輯閘42、第三邏輯閘43以及第四邏輯閘44,儲存器、跳針以及邏輯閘的數量僅為舉例說明之,並不以此局限本發明的應用範疇。 The selection and setting system of the shortcut peripheral interconnection standard disclosed by the present invention comprises: a shortcut peripheral interconnection standard control chip 10, a first storage 21, a second storage 22, a third storage 23, and a fourth storage 24. And the selection controller 30, wherein the selection controller 30 further comprises: a first jumper 31, a second jumper 32, a third jumper 33, a fourth jumper 34, a first logic gate 41, a second logic gate 42, The number of the third logic gate 43 and the fourth logic gate 44, the memory, the jumper, and the logic gate are merely illustrative and are not intended to limit the scope of application of the present invention.

快捷外設互聯標準控制晶片10(例如是PEX8713晶片,在此僅為舉例說明之,並不以此侷限本發明的應用範疇)是用以產生第一選擇訊號51,第一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24分別與快捷外設互聯標準控制晶片10電性連接,且第一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24中分別儲存有一個配置設定,第一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24可為電子抹除式可複寫唯讀記憶體(Electrically-Erasable Programmable Read-Only Memory,EEPROM),在此僅為舉例說明之,並不以此侷限本發明的應用範疇。 The fast peripheral interconnect standard control chip 10 (for example, the PEX8713 chip, which is merely exemplified herein, and is not limited to the scope of application of the present invention) is used to generate the first selection signal 51, the first memory 21, The second storage unit 22, the third storage unit 23, and the fourth storage unit 24 are electrically connected to the shortcut peripheral interconnection standard control chip 10, respectively, and the first storage unit 21, the second storage unit 22, the third storage unit 23, and the The four storages 24 respectively store a configuration setting, and the first storage 21, the second storage 22, the third storage 23, and the fourth storage 24 can be electronically erasable rewritable read-only memory (Electrically- Erasable Programmable Read-Only Memory (EEPROM) is merely illustrative and is not intended to limit the scope of application of the present invention.

選擇控制器30中第一跳針31的第一接腳311與第一邏輯閘41連接,且第一跳針31的第一接腳311與電源61連接並生成第三選擇訊號53,第一跳針31的第二接腳312與接地62連接,且快捷外設互聯標準控制晶片10與第一邏輯閘41連接以提供第一選擇訊號51。 The first pin 311 of the first jumper 31 of the controller 30 is connected to the first logic gate 41, and the first pin 311 of the first jumper 31 is connected to the power source 61 to generate a third selection signal 53, first The second pin 312 of the jumper pin 31 is connected to the ground 62, and the shortcut peripheral interconnect standard control chip 10 is connected to the first logic gate 41 to provide the first selection signal 51.

選擇控制器30中第二跳針32的第一接腳321與第二邏輯閘42連接,且第二跳針32的第一接腳321與電源61連接並生成第三選擇訊號53,第二跳針32的第二接腳322與接地62連接,且快捷外設互聯標準控制晶片10與第二邏輯閘42連接以提供第一選擇訊號51。 The first pin 321 of the second jumper 32 of the controller 30 is connected to the second logic gate 42 , and the first pin 321 of the second jumper 32 is connected to the power source 61 to generate a third selection signal 53 . The second pin 322 of the jump pin 32 is connected to the ground 62, and the shortcut peripheral interconnect standard control chip 10 is connected to the second logic gate 42 to provide the first selection signal 51.

選擇控制器30中第三跳針33的第一接腳331與第三邏輯閘43連接,且第三跳針33的第一接腳331與電源61連接並生成第三選擇訊號53,第三跳針33的第二接腳332與接地62連接,且快捷蛉設互聯標準控制晶片10與第三邏輯閘43連接以提供第一選擇訊號51。 The first pin 331 of the third jumper 33 of the controller 30 is connected to the third logic gate 43, and the first pin 331 of the third jumper 33 is connected to the power source 61 to generate a third selection signal 53. The second pin 332 of the jumper pin 33 is connected to the ground 62, and the interconnect standard control wafer 10 is connected to the third logic gate 43 to provide the first selection signal 51.

選擇控制器30中第四跳針34的第一接腳341與第四邏輯閘44連接,且第四跳針34的第一接腳341與電源61連接並生成第三選擇訊號53,第四跳針34的第二接腳342與接地62連接,且快捷外設互聯標準控制晶片10與第四邏輯閘44連接以提供第一選擇訊號51。 The first pin 341 of the fourth jumper 34 of the controller 30 is connected to the fourth logic gate 44, and the first pin 341 of the fourth jumper 34 is connected to the power source 61 to generate a third selection signal 53. The second pin 342 of the jumper pin 34 is connected to the ground 62, and the shortcut peripheral interconnect standard control chip 10 is connected to the fourth logic gate 44 to provide the first selection signal 51.

當在快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為有效狀態的情況下,有效狀態即邏輯低電壓狀態為“0”,且第一跳針31透過跳帽將第一跳針31的第一接腳311與第一跳針31的第二接腳312連接使被選擇,第一跳針31的第一接腳311所生成的第三選擇訊號53即為有效狀態“0”,第二跳針32、第三跳針33以及第四跳針34並未被選擇,即第二跳針32的第一接腳321、第三跳針33的第一接腳331以及第四跳針34的第一接腳341所生成的第三選擇訊號53皆為無效狀態“1”。 When the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is in an active state, the active state, that is, the logic low voltage state is “0”, and the first jumper 31 transmits the first jump through the jump cap. The first pin 311 of the pin 31 is connected to the second pin 312 of the first jumper 31 to be selected, and the third selection signal 53 generated by the first pin 311 of the first jumper 31 is in an active state of “0”. The second jumper 32, the third jumper 33, and the fourth jumper 34 are not selected, that is, the first pin 321 of the second jumper 32, the first pin 331 of the third jumper 33, and the first The third selection signal 53 generated by the first pin 341 of the four-jump pin 34 is in an inactive state "1".

第一邏輯閘41即可對第一跳針31的第一接腳311所生成的第三選擇訊號53為“0”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號521為“0”。 The first logic gate 41 is "0" for the third selection signal 53 generated by the first pin 311 of the first jumper 31 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is " 0" performs or logical operation to generate second selection signal 521 to "0".

第二邏輯閘42即可對第二跳針32的第一接腳321所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號522為“1”。 The second logic gate 42 can be “1” for the third selection signal 53 generated by the first pin 321 of the second jumper 32 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" performs or logical operations to generate a second selection signal 522 of "1."

第三邏輯閘43即可對第三跳針33的第一接腳331所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號523為“1”。 The third logic gate 43 can be “1” for the third selection signal 53 generated by the first pin 331 of the third jumper 33 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" is performed or logically operated to generate a second selection signal 523 of "1".

第四邏輯閘42即可對第四跳針34的第一接腳341所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號524為“1”。 The fourth logic gate 42 can be “1” for the third selection signal 53 generated by the first pin 341 of the fourth jumper 34 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" is performed or logically operated to generate a second selection signal 524 of "1".

由於第二選擇訊號521為“0”屬於有效狀態,故與第二選擇訊號521連接的第一儲存器21中配置設定會被選擇,由於第二選擇訊號522為“1”屬於無效狀態,故與第二選擇訊號522連接的第二儲存器22中配置設定不會被選擇,由於第二選擇訊號523為“1”屬於無效狀態,故與第二選擇訊號523連接的第三儲存器23中配置設定不會被選擇,由於第二選擇訊號524為“1”屬於無效狀態,故與第二選擇訊號524連接的第四儲存器24中配置設定不會被選擇。 Since the second selection signal 521 is "0", the configuration setting in the first storage 21 connected to the second selection signal 521 is selected, and since the second selection signal 522 is "1", it is in an invalid state. The configuration setting in the second storage 22 connected to the second selection signal 522 is not selected. Since the second selection signal 523 is "1", it is in an invalid state, so the third storage 23 is connected to the second selection signal 523. The configuration setting is not selected. Since the second selection signal 524 is "1", it is in an invalid state, so the configuration setting in the fourth storage 24 connected to the second selection signal 524 is not selected.

透過上述第一儲存器21中被選擇的配置設定,即可進行快捷外設互聯標準控制晶片10進行配置。 The configuration of the shortcut peripheral interconnection standard control wafer 10 can be performed through the selected configuration settings in the first memory 21 described above.

接著,請同時參考「第2圖」以及「第3圖」所示,「第3圖」繪示為本發明微伺服器的第一實施態樣系統架構圖。 Next, please refer to "Fig. 2" and "3rd figure" at the same time, and "Fig. 3" is a system architecture diagram of the first embodiment of the microserver according to the present invention.

本發明所揭露第一實施態樣的微伺服器(microserver),其包含:第一系統單晶片(System On Chip,SOC)71、第二系統單晶片72、第三系統單晶片73以及第四系統單晶片74、快捷外設互聯標準控制晶片10、第一儲存器21、第二儲存器22、第三儲存器23、第四儲存器24以及選擇控制器30,其中選擇控制器30更包含:第一跳針31、第二跳針32、第三跳針33、第四跳針34、第一邏輯閘41、第二邏輯閘42、第三邏輯閘43以及第四邏輯閘44,系統單晶片、儲存器、跳針以及邏輯閘的數量僅為舉例說明之,並不以此侷限本發明的應用範疇。 A microserver according to a first embodiment of the present invention includes: a first system single chip (SOC) 71, a second system single chip 72, a third system single chip 73, and a fourth a system single chip 74, a shortcut peripheral interconnection standard control chip 10, a first storage 21, a second storage 22, a third storage 23, a fourth storage 24, and a selection controller 30, wherein the selection controller 30 further includes a first jumper 31, a second jumper 32, a third jumper 33, a fourth jumper 34, a first logic gate 41, a second logic gate 42, a third logic gate 43, and a fourth logic gate 44, the system The number of single wafers, reservoirs, jumpers, and logic gates is for illustrative purposes only and is not intended to limit the scope of application of the present invention.

第一系統單晶片71具有第一快捷外設互聯標準埠711,第二系統單晶片72具有第一快捷外設互聯標準埠721,第三系統單晶片73具有第一快捷外設互聯標準埠731以及第四系統單晶片74具有第一快捷外設互聯標準埠741。 The first system single chip 71 has a first fast peripheral interconnection standard 埠 711, the second system single chip 72 has a first fast peripheral interconnection standard 埠 721, and the third system single chip 73 has a first fast peripheral interconnection standard 埠 731 And the fourth system single chip 74 has a first fast peripheral interconnection standard 埠741.

快捷外設互聯標準控制晶片10(例如是PEX8713晶片,在此僅為舉例說明之,並不以此侷限本發明的應用範疇)具有第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14,第二快捷外設互聯標準埠11與第一快捷外設互聯標準埠711對應電性連接,第二快捷外設互聯標準埠12與第一快捷外設互聯標準埠721對應電性連接,第二快捷外設互聯標準埠13與第一快捷外設互聯標準埠731對應電性連接,第二快捷外設互聯標準埠14與第一快捷外設互聯標準埠741對應電性連接,且快捷外設互聯標準控制晶片10產生第一選擇訊號51。 The fast peripheral interconnect standard control chip 10 (for example, the PEX8713 chip, which is merely exemplified herein, is not limited to the application scope of the present invention) has the second shortcut peripheral interconnection standard 埠11, and the second shortcut peripheral interconnection The standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14, the second shortcut peripheral interconnection standard 埠11 is electrically connected to the first shortcut peripheral interconnection standard 埠711, and the second The fast peripheral interconnection standard 埠12 is electrically connected with the first fast peripheral interconnection standard 埠721, and the second fast peripheral interconnection standard 埠13 is electrically connected with the first shortcut peripheral interconnection standard 埠731, the second shortcut The interconnection standard 埠14 is electrically connected to the first fast peripheral interconnection standard 埠741, and the fast peripheral interconnection standard control chip 10 generates the first selection signal 51.

第一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24分別與快捷外設互聯標準控制晶片10電性連接,且第一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24中分別儲存有一個配置設定,第一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24可為電子抹除式可複寫唯讀記憶體(Electrically-Erasable Programmable Read-Only Memory,EEPROM),在此僅為舉例說明之,並不以此侷限本發明的應用範疇。 The first storage unit 21, the second storage unit 23, the third storage unit 23, and the fourth storage unit 24 are electrically connected to the shortcut peripheral interconnection standard control chip 10, respectively, and the first storage unit 21 and the second storage unit 22 are respectively The third storage 23 and the fourth storage 24 respectively store a configuration setting, and the first storage 21, the second storage 22, the third storage 23, and the fourth storage 24 can be electronically erasable and rewritable. The Electrically-Erasable Programmable Read-Only Memory (EEPROM) is merely illustrative and is not intended to limit the scope of application of the present invention.

選擇控制器30中第一跳針31的第一接腳311與第一邏輯閘41連接,且第一跳針31的第一接腳311與電源61連接並生成第三選擇訊號53,第一跳針31的第二接腳312與接地62連接,且快捷外設互聯標準控制晶片10與第一邏輯閘41連接以提供第一選擇訊號51。 The first pin 311 of the first jumper 31 of the controller 30 is connected to the first logic gate 41, and the first pin 311 of the first jumper 31 is connected to the power source 61 to generate a third selection signal 53, first The second pin 312 of the jumper pin 31 is connected to the ground 62, and the shortcut peripheral interconnect standard control chip 10 is connected to the first logic gate 41 to provide the first selection signal 51.

選擇控制器30中第二跳針32的第一接腳321與第二邏輯閘42連接,且第二跳針32的第一接腳321與電源61連接並生成第三選擇訊號53,第二跳針32的第二接腳322與接地62連接,且快捷外設互聯標準控制晶片10與第二邏輯閘42連接以提供第一選擇訊號51。 The first pin 321 of the second jumper 32 of the controller 30 is connected to the second logic gate 42 , and the first pin 321 of the second jumper 32 is connected to the power source 61 to generate a third selection signal 53 . The second pin 322 of the jump pin 32 is connected to the ground 62, and the shortcut peripheral interconnect standard control chip 10 is connected to the second logic gate 42 to provide the first selection signal 51.

選擇控制器30中第三跳針33的第一接腳331與第三邏輯閘43連接,且第三跳針33的第一接腳331與電源61連接並生成第三選擇訊號53,第三跳針33的第二接腳332與接地62連接,且快捷外設互聯標準控制晶片10與第三邏輯閘43連接以提供第一選擇訊號51。 The first pin 331 of the third jumper 33 of the controller 30 is connected to the third logic gate 43, and the first pin 331 of the third jumper 33 is connected to the power source 61 to generate a third selection signal 53. The second pin 332 of the jumper pin 33 is connected to the ground 62, and the shortcut peripheral interconnect standard control chip 10 is connected to the third logic gate 43 to provide the first selection signal 51.

選擇控制器30中第四跳針34的第一接腳341與第四邏輯閘44連接,且第四跳針34的第一接腳341與電源61連接並生成第三選擇訊號53,第四跳針34的第二接腳342與接地62連接,且快捷外設互聯標準控制晶片10與第四邏輯閘44連接以提供第一選擇訊號51。 The first pin 341 of the fourth jumper 34 of the controller 30 is connected to the fourth logic gate 44, and the first pin 341 of the fourth jumper 34 is connected to the power source 61 to generate a third selection signal 53. The second pin 342 of the jumper pin 34 is connected to the ground 62, and the shortcut peripheral interconnect standard control chip 10 is connected to the fourth logic gate 44 to provide the first selection signal 51.

當在快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為有效狀態的情況下,有效狀態即邏輯低電壓狀態為“0”,且第一跳針31透過跳帽將第一跳針31的第一接腳311與第一跳針31的第二接腳312連接使被選擇,第一跳針31的第一接腳311所生成的第三選擇訊號53即為有效狀態“0”,第二跳針32、第三跳針33以及第四跳針34並未被選擇,即第二跳針32的第一接腳321、第三跳針33的第一接腳331以及第四跳針34的第一接腳341所生成的第三選擇訊號53皆為無效狀態“1”。 When the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is in an active state, the active state, that is, the logic low voltage state is “0”, and the first jumper 31 transmits the first jump through the jump cap. The first pin 311 of the pin 31 is connected to the second pin 312 of the first jumper 31 to be selected, and the third selection signal 53 generated by the first pin 311 of the first jumper 31 is in an active state of “0”. The second jumper 32, the third jumper 33, and the fourth jumper 34 are not selected, that is, the first pin 321 of the second jumper 32, the first pin 331 of the third jumper 33, and the first The third selection signal 53 generated by the first pin 341 of the four-jump pin 34 is in an inactive state "1".

第一邏輯閘41即可對第一跳針31的第一接腳311所生成的第三選擇訊號53為“0”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號521為“0”。 The first logic gate 41 is "0" for the third selection signal 53 generated by the first pin 311 of the first jumper 31 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is " 0" performs or logical operation to generate second selection signal 521 to "0".

第二邏輯閘42即可對第二跳針32的第一接腳321所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號522為“1”。 The second logic gate 42 can be “1” for the third selection signal 53 generated by the first pin 321 of the second jumper 32 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" performs or logical operations to generate a second selection signal 522 of "1."

第三邏輯閘43即可對第三跳針33的第一接腳331所生成的第 三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號523為“1”。 The third logic gate 43 can generate the first pin 331 of the third jumper 33 The third selection signal 53 is "1" and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is "0" or logically operated to generate the second selection signal 523 to "1".

第四邏輯閘42即可對第四跳針34的第一接腳341所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號524為“1”。 The fourth logic gate 42 can be “1” for the third selection signal 53 generated by the first pin 341 of the fourth jumper 34 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" is performed or logically operated to generate a second selection signal 524 of "1".

由於第二選擇訊號521為“0”屬於有效狀態,故與第二選擇訊號521連接的第一儲存器21中配置設定為“將第二快捷外設互聯標準埠11設置為上游(upstream)快捷外設互聯標準埠,第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”會被選擇。 Since the second selection signal 521 is “0”, it is in an active state, so the configuration in the first storage 21 connected to the second selection signal 521 is set to “set the second shortcut peripheral interconnection standard 埠11 to upstream (upstream). The peripheral interconnection standard 埠, the second fast peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are not set as the upstream shortcut peripheral interconnection standard 埠” will be selected.

透過上述第一儲存器21中被選擇的配置設定為“將第二快捷外設互聯標準埠11設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”,藉以進行快捷外設互聯標準控制晶片10中第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14的設置。 The selected configuration in the first storage 21 is set to “set the second fast peripheral interconnection standard 埠11 as the upstream fast peripheral interconnection standard 埠, the second shortcut peripheral interconnection standard 埠12, the second shortcut peripheral The interconnection standard 埠13 and the second shortcut peripheral interconnection standard 埠14 are not set as the upstream fast peripheral interconnection standard 埠", thereby implementing the second peripheral peripheral interconnection standard 晶片11, the second shortcut in the fast peripheral interconnection standard control chip 10. The peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are set.

被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠11與第一系統單晶片71的第一快捷外設互聯標準埠711電性連接並進行數據傳輸。 The second fast peripheral interconnection standard 11 set as the upstream fast peripheral interconnection standard is electrically connected to the first fast peripheral interconnection standard 埠 711 of the first system single chip 71 and performs data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠12與第二系統單晶片72的第一快捷外設互聯標準埠721電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠12, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠721 of the second system single chip 72 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠13與第三系統單晶片73的第一快捷外設互聯標準埠731電性連接但不進行數據傳輸。 The second shortcut peripheral interconnection standard 埠13, which is not set as the upstream shortcut peripheral interconnection standard, is electrically connected to the first shortcut peripheral interconnection standard 埠731 of the third system single chip 73 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠14與第四系統單晶片74的第一快捷外設互聯標準埠741電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠14, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠741 of the fourth system single chip 74 but does not perform data transmission.

當在快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為有效狀態的情況下,有效狀態即邏輯低電壓狀態為“0”,且第二跳針32透過 跳帽將第二跳針32的第一接腳321與第二跳針32的第二接腳322連接使被選擇,第二跳針32的第一接腳321所生成的第三選擇訊號53即為有效狀態“0”,第一跳針31、第三跳針33以及第四跳針34並未被選擇,即第一跳針31的第一接腳311、第三跳針33的第一接腳331以及第四跳針34的第一接腳341所生成的第三選擇訊號53皆為無效狀態“1”。 When the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is in an active state, the active state, that is, the logic low voltage state is "0", and the second jump pin 32 is transmitted. The jumper cap connects the first pin 321 of the second jumper pin 32 with the second pin 322 of the second jumper pin 32 to be selected, and the third select signal 53 generated by the first pin 321 of the second jumper pin 32 is selected. That is, the active state "0", the first jumper 31, the third jumper 33, and the fourth jumper 34 are not selected, that is, the first pin 311 and the third jumper 33 of the first jumper 31 The third selection signal 53 generated by the first pin 341 of the one pin 331 and the fourth jump pin 34 is in an invalid state "1".

第一邏輯閘41即可對第一跳針31的第一接腳311所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號521為“1”。 The first logic gate 41 can be “1” for the third selection signal 53 generated by the first pin 311 of the first jumper 31 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" is performed or logically operated to generate the second selection signal 521 to be "1".

第二邏輯閘42即可對第二跳針32的第一接腳321所生成的第三選擇訊號53為“0”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號522為“0”。 The second logic gate 42 is "0" for the third selection signal 53 generated by the first pin 321 of the second jumper 32 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is " 0" performs or logical operation to generate second selection signal 522 to "0".

第三邏輯閘43即可對第三跳針33的第一接腳331所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號523為“1”。 The third logic gate 43 can be “1” for the third selection signal 53 generated by the first pin 331 of the third jumper 33 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" is performed or logically operated to generate a second selection signal 523 of "1".

第四邏輯閘42即可對第四跳針34的第一接腳341所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號524為“1”。 The fourth logic gate 42 can be “1” for the third selection signal 53 generated by the first pin 341 of the fourth jumper 34 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" is performed or logically operated to generate a second selection signal 524 of "1".

由於第二選擇訊號522為“0”屬於有效狀態,故與第二選擇訊號522連接的第二儲存器22中配置設定為“將第二快捷外設互聯標準埠12設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”會被選擇。 Since the second selection signal 522 is “0”, the second storage 22 connected to the second selection signal 522 is configured to “set the second shortcut peripheral interconnection standard 埠12 as the upstream shortcut peripheral interconnection. The standard 埠, the second fast peripheral interconnection standard 埠11, the second fast peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are not set as the upstream fast peripheral interconnection standard 埠” will be selected.

透過上述第一儲存器21中被選擇的配置設定為“將第二快捷外設互聯標準埠12設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”,藉以進行快捷外設互聯標準控制晶片10中第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14的設置。 The selected configuration in the first storage 21 is set to “set the second fast peripheral interconnection standard 埠12 as the upstream fast peripheral interconnection standard 埠, the second shortcut peripheral interconnection standard 埠11, the second shortcut peripheral The interconnection standard 埠13 and the second shortcut peripheral interconnection standard 埠14 are not set as the upstream fast peripheral interconnection standard 埠", thereby implementing the second peripheral peripheral interconnection standard 晶片11, the second shortcut in the fast peripheral interconnection standard control chip 10. The peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are set.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠11與第一系統單晶片71的第一快捷外設互聯標準埠711電性連接但不進行數 據傳輸。 The second fast peripheral interconnection standard 未被11, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠711 of the first system single chip 71, but is not counted. According to transmission.

被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠12與第二系統單晶片72的第一快捷外設互聯標準埠721電性連接並進行數據傳輸。 The second fast peripheral interconnection standard 埠12, which is set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠721 of the second system single chip 72 and performs data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠13與第三系統單晶片73的第一快捷外設互聯標準埠731電性連接但不進行數據傳輸。 The second shortcut peripheral interconnection standard 埠13, which is not set as the upstream shortcut peripheral interconnection standard, is electrically connected to the first shortcut peripheral interconnection standard 埠731 of the third system single chip 73 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠14與第四系統單晶片74的第一快捷外設互聯標準埠741電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠14, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠741 of the fourth system single chip 74 but does not perform data transmission.

當在快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為有效狀態的情況下,有效狀態即邏輯低電壓狀態為“0”,且第三跳針33透過跳帽將第三跳針33的第一接腳331與第三跳針33的第二接腳332連接使被選擇,第三跳針33的第一接腳331所生成的第三選擇訊號53即為有效狀態“0”,第一跳針31、第二跳針32以及第四跳針34並未被選擇,即第一跳針31的第一接腳311、第二跳針32的第一接腳321以及第四跳針34的第一接腳341所生成的第三選擇訊號53皆為無效狀態“1”。 When the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is in an active state, the active state, that is, the logic low voltage state is “0”, and the third jump pin 33 transmits the third jump through the jump cap. The first pin 331 of the pin 33 is connected to the second pin 332 of the third jumper 33 to be selected, and the third selection signal 53 generated by the first pin 331 of the third jumper 33 is in an active state of “0”. The first jumper 31, the second jumper 32, and the fourth jumper 34 are not selected, that is, the first pin 311 of the first jumper 31, the first pin 321 of the second jumper 32, and the first The third selection signal 53 generated by the first pin 341 of the four-jump pin 34 is in an inactive state "1".

第一邏輯閘41即可對第一跳針31的第一接腳311所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號521為“1”。 The first logic gate 41 can be “1” for the third selection signal 53 generated by the first pin 311 of the first jumper 31 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" is performed or logically operated to generate the second selection signal 521 to be "1".

第二邏輯閘42即可對第二跳針32的第一接腳321所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號522為“1”。 The second logic gate 42 can be “1” for the third selection signal 53 generated by the first pin 321 of the second jumper 32 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" performs or logical operations to generate a second selection signal 522 of "1."

第三邏輯閘43即可對第三跳針33的第一接腳331所生成的第三選擇訊號53為“0”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號523為“0”。 The third logic gate 43 is "0" for the third selection signal 53 generated by the first pin 331 of the third jumper 33 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is " 0" performs or logical operation to generate second selection signal 523 to "0".

第四邏輯閘42即可對第四跳針34的第一接腳341所生成的第三選擇訊號53為“1”與快捷外設互聯標薄控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號524為“1”。 The fourth logic gate 42 can be a "1" for the third selection signal 53 generated by the first pin 341 of the fourth jumper 34, and the first selection signal 51 generated by the shortcut peripheral interconnection standard control wafer 10 is A "0" is performed or a logical operation to generate a second selection signal 524 of "1".

由於第二選擇訊號523為“0”屬於有效狀態,故與第二選擇訊 號523連接的第三儲存器23中配置設定為“將第二快捷外設互聯標準埠13設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”會被選擇。 Since the second selection signal 523 is "0", it is in an active state, and the second selection signal The configuration of the third storage 23 connected to the number 523 is set to "set the second shortcut peripheral interconnection standard 埠13 as the upstream fast peripheral interconnection standard 埠, the second shortcut peripheral interconnection standard 埠11, the second shortcut peripheral interconnection The standard 埠12 and the second shortcut peripheral interconnection standard 埠14 are not set to the upstream fast peripheral interconnection standard 埠" will be selected.

透過上述第一儲存器21中被選擇的配置設定為“將第二快捷外設互聯標準埠13設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”,藉以進行快捷外設互聯標準控制晶片10中第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14的設置。 The selected configuration in the first storage 21 is set to “set the second fast peripheral interconnection standard 埠13 as the upstream fast peripheral interconnection standard 埠, the second shortcut peripheral interconnection standard 埠11, the second shortcut peripheral The interconnection standard 埠12 and the second fast peripheral interconnection standard 埠14 are not set as the upstream fast peripheral interconnection standard 埠", thereby implementing the second peripheral peripheral interconnection standard 晶片11, the second shortcut in the fast peripheral interconnection standard control chip 10. The peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are set.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠11與第一系統單晶片71的第一快捷外設互聯標準埠711電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 未被11, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠 711 of the first system single chip 71 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠12與第二系統單晶片72的第一快捷外設互聯標準埠721電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠12, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠721 of the second system single chip 72 but does not perform data transmission.

被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠13與第三系統單晶片73的第一快捷外設互聯標準埠731電性連接並進行數據傳輸。 The second fast peripheral interconnection standard 埠13, which is set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠731 of the third system single chip 73 and performs data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠14與第四系統單晶片74的第一快捷外設互聯標準埠741電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠14, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠741 of the fourth system single chip 74 but does not perform data transmission.

當在快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為有效狀態的情況下,有效狀態即邏輯低電壓狀態為“0”,且第四跳針34透過跳帽將第四跳針34的第一接腳341與第四跳針34的第二接腳342連接使被選擇,第四跳針34的第一接腳341所生成的第三選擇訊號53即為有效狀態“0”,第一跳針31、第二跳針32以及第三跳針33並未被選擇,即第一跳針31的第一接腳311、第二跳針32的第一接腳321以及第三跳針33的第一接腳331所生成的第三選擇訊號53皆為無效狀態“1”。 When the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is in an active state, the active state, that is, the logic low voltage state is “0”, and the fourth jumper 34 transmits the fourth jump through the jump cap. The first pin 341 of the pin 34 is connected to the second pin 342 of the fourth jumper 34 to be selected, and the third selection signal 53 generated by the first pin 341 of the fourth jumper 34 is in an active state of “0”. The first jumper 31, the second jumper 32, and the third jumper 33 are not selected, that is, the first pin 311 of the first jumper 31, the first pin 321 of the second jumper 32, and the first The third selection signal 53 generated by the first pin 331 of the three-jump pin 33 is in an inactive state "1".

第一邏輯閘41即可對第一跳針31的第一接腳311所生成的第 三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號521為“1”。 The first logic gate 41 can generate the first pin 311 of the first jumper 31 The third selection signal 53 is "1" and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is "0" or logically operated to generate the second selection signal 521 to be "1".

第二邏輯閘42即可對第二跳針32的第一接腳321所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號522為“1”。 The second logic gate 42 can be “1” for the third selection signal 53 generated by the first pin 321 of the second jumper 32 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" performs or logical operations to generate a second selection signal 522 of "1."

第三邏輯閘43即可對第三跳針33的第一接腳331所生成的第三選擇訊號53為“1”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號523為“1”。 The third logic gate 43 can be “1” for the third selection signal 53 generated by the first pin 331 of the third jumper 33 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is “ 0" is performed or logically operated to generate a second selection signal 523 of "1".

第四邏輯閘42即可對第四跳針34的第一接腳341所生成的第三選擇訊號53為“0”與快捷外設互聯標準控制晶片10所生成的第一選擇訊號51為“0”進行或邏輯運算以生成第二選擇訊號524為“0”。 The fourth logic gate 42 is "0" for the third selection signal 53 generated by the first pin 341 of the fourth jumper 34 and the first selection signal 51 generated by the shortcut peripheral interconnection standard control chip 10 is " 0" performs or logical operation to generate second selection signal 524 to "0".

由於第二選擇訊號524為“0”屬於有效狀態,故與第二選擇訊號524連接的第四儲存器24中配置設定為“將第二快捷外設互聯標準埠14設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12以及第二快捷外設互聯標準埠13不設置為上游快捷外設互聯標準埠”會被選擇。 Since the second selection signal 524 is "0", the configuration is set to "set the second shortcut peripheral interconnection standard 埠 14 as the upstream shortcut peripheral interconnection" in the fourth storage 24 connected to the second selection signal 524. The standard 埠, the second fast peripheral interconnection standard 埠 11, the second fast peripheral interconnection standard 埠 12 and the second fast peripheral interconnection standard 埠 13 are not set as the upstream fast peripheral interconnection standard 埠” will be selected.

透過上述第一儲存器21中被選擇的配置設定為“將第二快捷外設互聯標準埠14設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12以及第二快捷外設互聯標準埠13不設置為上游快捷外設互聯標準埠”,藉以進行快捷外設互聯標準控制晶片10中第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14的設置。 The selected configuration in the first storage 21 is set to "set the second fast peripheral interconnection standard 埠 14 as the upstream fast peripheral interconnection standard 埠, the second shortcut peripheral interconnection standard 埠 11, the second shortcut peripheral The interconnection standard 埠12 and the second fast peripheral interconnection standard 埠13 are not set as the upstream fast peripheral interconnection standard 埠", thereby implementing the second peripheral peripheral interconnection standard 晶片11, the second shortcut in the fast peripheral interconnection standard control chip 10. The peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are set.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠11與第一系統單晶片71的第一快捷外設互聯標準埠711電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 未被11, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠 711 of the first system single chip 71 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠12與第二系統單晶片72的第一快捷外設互聯標準埠721電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠12, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠721 of the second system single chip 72 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠13與第三系統單晶片73的第一快捷外設互聯標準埠731電性連接但不進行數 據傳輸。 The second fast peripheral interconnection standard 埠13, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠731 of the third system single chip 73, but is not counted. According to transmission.

被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠14與第四系統單晶片74的第一快捷外設互聯標準埠741電性連接並進行數據傳輸。 The second fast peripheral interconnection standard 埠14, which is set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠741 of the fourth system single chip 74 and performs data transmission.

上述的快捷外設互聯標準控制晶片10更包含支援通用序列匯流排(Universal Serial Bus,USB)151、序列ATA(Serial Advanced Technology Attachment,SATA)152以及加速影像處理埠(AcceleratedGraphiesPort,AGP)153,以及包含處於常開狀態(always on)的管理埠154。 The above-mentioned shortcut peripheral interconnection standard control chip 10 further includes a Universal Serial Bus (USB) 151, a Serial Advanced Technology Attachment (SATA) 152, and an Accelerated Image Port (AGP) 153, and Contains a management port 154 that is always on.

接著,請參考「第4圖」,所示,「第4圖」繪示為本發明微伺服器的第二實施態樣系統架橫圖。 Next, please refer to FIG. 4, and FIG. 4 is a cross-sectional view of the second embodiment of the microserver according to the present invention.

本發明所揭露第二實施態樣的微伺服器(microserver),其包含:第一系統單晶片(System On Chip,SOC)71、第二系統單晶片72、第三系統單晶片73以及第四系統單晶片74、快捷外設互聯標準控制晶片10、第一儲存器21、第二儲存器22、第三儲存器23、第四儲存器24以及選擇控制器30,系統單晶片以及儲存器的數量僅為舉例說明之,並不以此侷限本發明的應用範疇。 A microserver according to a second embodiment of the present invention includes: a first system single chip (SOC) 71, a second system single chip 72, a third system single chip 73, and a fourth System single chip 74, shortcut peripheral interconnect standard control chip 10, first storage 21, second storage 22, third storage 23, fourth storage 24 and selection controller 30, system single chip and storage The number is for illustrative purposes only and is not intended to limit the scope of application of the invention.

第一系統單晶片71具有第一快捷外設互聯標準埠711,第二系統單晶片72具有第一快捷外設互聯標準埠721,第三系統單晶片73具有第一快捷外設互聯標準埠731以及第四系統單晶片74具有第一快捷外設互聯標準埠741。 The first system single chip 71 has a first fast peripheral interconnection standard 埠 711, the second system single chip 72 has a first fast peripheral interconnection standard 埠 721, and the third system single chip 73 has a first fast peripheral interconnection standard 埠 731 And the fourth system single chip 74 has a first fast peripheral interconnection standard 埠741.

快捷外設互聯標準控制晶片10(例如是PEX8713晶片,在此僅為舉例說明之,並不以此侷限本發明的應用範疇)具有第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14,第二快捷外設互聯標準埠11與第一快捷外設互聯標準埠711對應電性連接,第二快捷外設互聯標準埠12與第一快捷外設互聯標準埠721對應電性連接,第二快捷外設互聯標準埠13與第一快捷外設互聯標準埠731對應電性連接,第二快捷外設互聯標準埠14與第一快捷外設互聯標準埠741對應電性連接,且快捷外設互聯標準控制晶片10產生第一選擇訊號51。 The fast peripheral interconnect standard control chip 10 (for example, the PEX8713 chip, which is merely exemplified herein, is not limited to the application scope of the present invention) has the second shortcut peripheral interconnection standard 埠11, and the second shortcut peripheral interconnection The standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14, the second shortcut peripheral interconnection standard 埠11 is electrically connected to the first shortcut peripheral interconnection standard 埠711, and the second The fast peripheral interconnection standard 埠12 is electrically connected with the first fast peripheral interconnection standard 埠721, and the second fast peripheral interconnection standard 埠13 is electrically connected with the first shortcut peripheral interconnection standard 埠731, the second shortcut The interconnection standard 埠14 is electrically connected to the first fast peripheral interconnection standard 埠741, and the fast peripheral interconnection standard control chip 10 generates the first selection signal 51.

第一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24分別與快捷外設互聯標準控制晶片10電性連接,且第一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24中分別儲存有一個配置設定,第 一儲存器21、第二儲存器22、第三儲存器23以及第四儲存器24可為電子抹除式可複寫唯讀記憶體(Electrically-Erasable Programmable Read-Only Memory,EEPROM),在此僅為舉例說明之,並不以此侷限本發明的應用範疇。 The first storage unit 21, the second storage unit 23, the third storage unit 23, and the fourth storage unit 24 are electrically connected to the shortcut peripheral interconnection standard control chip 10, respectively, and the first storage unit 21 and the second storage unit 22 are respectively A configuration setting is stored in each of the third storage 23 and the fourth storage 24, A storage 21, a second storage 22, a third storage 23, and a fourth storage 24 may be an electrically-erasable EEPROM (Electrically-Erasable Programmable Read-Only Memory (EEPROM), only To illustrate, this is not intended to limit the scope of application of the invention.

選擇控制器30是由複雜可程式邏輯裝置(Complex Programmable Logic Device,CPLD)或是現場可程式化閘陣列(Field-Programmable Gate Array,FPGA)加以實現。 The selection controller 30 is implemented by a Complex Programmable Logic Device (CPLD) or a Field-Programmable Gate Array (FPGA).

即選擇控制器30與第一系統單晶片71、第二系統單晶片72、第三系統單晶片73以及第四系統單晶片74分別電性連接,選擇控制器30即可自快捷外設互聯標準控制晶片10接收第一選擇訊號,以及選擇控制器30自第一系統單晶片71、第二系統單晶片72、第三系統單晶片73以及第四系統單晶片74分別產生的控制訊號以生成第二選擇訊號,且每一個第二選擇訊號分別與第一系統單晶片71、第二系統單晶片72、第三系統單晶片73以及第四系統單晶片74相互對應。 That is, the selection controller 30 is electrically connected to the first system single chip 71, the second system single chip 72, the third system single chip 73, and the fourth system single chip 74, respectively, and the controller 30 can be selected from the fast peripheral interconnection standard. The control chip 10 receives the first selection signal, and selects control signals generated by the controller 30 from the first system single chip 71, the second system single chip 72, the third system single chip 73, and the fourth system single chip 74 to generate a first The second selection signal, and each of the second selection signals respectively correspond to the first system single chip 71, the second system single wafer 72, the third system single wafer 73, and the fourth system single wafer 74.

當經過選擇控制器30運算後生成的第二選擇訊號選擇第一儲存器21中配置設定為“將第二快捷外設互聯標準埠11設置為上游(upstream)快捷外設互聯標準埠,第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”,藉以進行快捷外設互聯標準控制晶片10中第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14的設置。 When the second selection signal generated by the operation of the selection controller 30 is selected, the configuration in the first storage 21 is set to "set the second shortcut peripheral interconnection standard 埠 11 to the upstream (upstream) fast peripheral interconnection standard 埠, the second The fast peripheral interconnection standard 埠12, the second fast peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are not set as the upstream fast peripheral interconnection standard 埠”, thereby performing the shortcut peripheral interconnection standard control chip 10 The second shortcut peripheral interconnection standard 埠11, the second shortcut peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are set.

被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠11與第一系統單晶片71的第一快捷外設互聯標準埠711電性連接並進行數據傳輸。 The second fast peripheral interconnection standard 11 set as the upstream fast peripheral interconnection standard is electrically connected to the first fast peripheral interconnection standard 埠 711 of the first system single chip 71 and performs data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠12與第二系統單晶片72的第一快捷外設互聯標準埠721電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠12, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠721 of the second system single chip 72 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠13與第三系統單晶片73的第一快捷外設互聯標準埠731電性連接但不進行數據傳輸。 The second shortcut peripheral interconnection standard 埠13, which is not set as the upstream shortcut peripheral interconnection standard, is electrically connected to the first shortcut peripheral interconnection standard 埠731 of the third system single chip 73 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準 埠14與第四系統單晶片74的第一快捷外設互聯標準埠741電性連接但不進行數據傳輸。 Second Fast Peripheral Interconnect Standard not set as the upstream fast peripheral interconnect standard The first 14 is connected to the first fast peripheral interconnection standard 741 of the fourth system single chip 74 without data transmission.

當經過選擇控制器30運算後生成的第二選擇訊號選擇第二儲存器22中配置設定為“將第二快捷外設互聯標準埠12設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”,藉以進行快捷外設互聯標準控制晶片10中第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14的設置。 When the second selection signal generated by the selection controller 30 is selected, the configuration in the second storage 22 is set to "set the second shortcut peripheral interconnection standard 埠12 as the upstream shortcut peripheral interconnection standard", the second shortcut peripheral The interconnection standard 埠11, the second fast peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are not set as the upstream fast peripheral interconnection standard 埠”, thereby performing the second shortcut of the fast peripheral interconnection standard control wafer 10 The peripheral interconnection standard 埠11, the second shortcut peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are set.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠11與第一系統單晶片71的第一快捷外設互聯標準埠711電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 未被11, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠 711 of the first system single chip 71 but does not perform data transmission.

被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠12與第二系統單晶片72的第一快捷外設互聯標準埠721電性連接並進行數據傳輸。 The second fast peripheral interconnection standard 埠12, which is set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠721 of the second system single chip 72 and performs data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠13與第三系統單晶片73的第一快捷外設互聯標準埠731電性連接但不進行數據傳輸。 The second shortcut peripheral interconnection standard 埠13, which is not set as the upstream shortcut peripheral interconnection standard, is electrically connected to the first shortcut peripheral interconnection standard 埠731 of the third system single chip 73 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠14與第四系統單晶片74的第一快捷外設互聯標準埠741電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠14, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠741 of the fourth system single chip 74 but does not perform data transmission.

當經過選擇控制器30運算後生成的第二選擇訊號選擇第二儲存器22中配置設定為“將第二快捷外設互聯標準埠13設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12以及第二快捷外設互聯標準埠14不設置為上游快捷外設互聯標準埠”,藉以進行快捷外設互聯標準控制晶片10中第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14的設置。 When the second selection signal generated by the selection controller 30 is selected, the configuration in the second storage 22 is set to "set the second shortcut peripheral interconnection standard 埠13 as the upstream shortcut peripheral interconnection standard", and the second shortcut peripheral The interconnection standard 埠11, the second shortcut peripheral interconnection standard 埠12, and the second shortcut peripheral interconnection standard 埠14 are not set as the upstream fast peripheral interconnection standard 埠”, thereby performing the second shortcut of the fast peripheral interconnection standard control wafer 10. The peripheral interconnection standard 埠11, the second shortcut peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are set.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠11與第一系統單晶片71的第一快捷外設互聯標準埠711電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 未被11, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠 711 of the first system single chip 71 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準 埠12與第二系統單晶片72的第一快捷外設互聯標準埠721電性連接但不進行數據傳輸。 Second Fast Peripheral Interconnect Standard not set as the upstream fast peripheral interconnect standard The first 12 is connected to the first fast peripheral interconnection standard 埠 721 of the second system single chip 72 but does not perform data transmission.

被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠13與第三系統單晶片73的第一快捷外設互聯標準埠731電性連接並進行數據傳輸。 The second fast peripheral interconnection standard 埠13, which is set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠731 of the third system single chip 73 and performs data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠14與第四系統單晶片74的第一快捷外設互聯標準埠741電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠14, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠741 of the fourth system single chip 74 but does not perform data transmission.

當經過選擇控制器30運算後生成的第二選擇訊號選擇第二儲存器22中配置設定為“將第二快捷外設互聯標準埠14設置為上游快捷外設互聯標準埠,第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12以及第二快捷外設互聯標準埠13不設置為上游快捷外設互聯標準埠”,藉以進行快捷外設互聯標準控制晶片10中第二快捷外設互聯標準埠11、第二快捷外設互聯標準埠12、第二快捷外設互聯標準埠13以及第二快捷外設互聯標準埠14的設置。 When the second selection signal generated by the selection controller 30 is selected, the configuration in the second storage 22 is set to "set the second shortcut peripheral interconnection standard 埠 14 as the upstream shortcut peripheral interconnection standard", the second shortcut peripheral The interconnection standard 埠11, the second shortcut peripheral interconnection standard 埠12, and the second shortcut peripheral interconnection standard 埠13 are not set as the upstream fast peripheral interconnection standard 埠”, thereby performing the second shortcut of the fast peripheral interconnection standard control wafer 10 The peripheral interconnection standard 埠11, the second shortcut peripheral interconnection standard 埠12, the second shortcut peripheral interconnection standard 埠13, and the second shortcut peripheral interconnection standard 埠14 are set.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠11與第一系統單晶片71的第一快捷外設互聯標準埠711電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 未被11, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠 711 of the first system single chip 71 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠12與第二系統單晶片72的第一快捷外設互聯標準埠721電性連接但不進行數據傳輸。 The second fast peripheral interconnection standard 埠12, which is not set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠721 of the second system single chip 72 but does not perform data transmission.

未被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠13與第三系統單晶片73的第一快捷外設互聯標準埠731電性連接但不進行數據傳輸。 The second shortcut peripheral interconnection standard 埠13, which is not set as the upstream shortcut peripheral interconnection standard, is electrically connected to the first shortcut peripheral interconnection standard 埠731 of the third system single chip 73 but does not perform data transmission.

被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠14與第四系統單晶片74的第一快捷外設互聯標準埠741電性連接並進行數據傳輸。 The second fast peripheral interconnection standard 埠14, which is set as the upstream fast peripheral interconnection standard, is electrically connected to the first fast peripheral interconnection standard 埠741 of the fourth system single chip 74 and performs data transmission.

綜上所述,可知本發明與先前技術之間的差異在於本發明是透過選擇控制器接收第一選擇訊號以生成多個第二選擇訊號,每一個第二選擇訊號分別對應連接儲存器其中之一,以控制儲存器中配置設定對快捷外設互聯標準控制晶片進行配置,配置設定用以選擇第二快捷外設互聯標準埠其中之一設置為上 游快捷外設互聯標準埠,其於的第二快捷外設互聯標準埠不進行上游快捷外設互聯標準埠設置,被設置為上游快捷外設互聯標準埠的第二快捷外設互聯標準埠與第一快捷外設互聯標準埠電性連接以進行數據傳輸。 In summary, it can be seen that the difference between the present invention and the prior art is that the present invention receives the first selection signal through the selection controller to generate a plurality of second selection signals, and each of the second selection signals respectively corresponds to the connection storage. First, configure the shortcut peripheral interconnect standard control chip by controlling the configuration settings in the memory, and configure settings to select the second shortcut peripheral interconnection standard, one of which is set to The standard of the fast peripherals interconnection, the second fast peripheral interconnection standard is not set up by the upstream fast peripheral interconnection standard, and is set as the second fast peripheral interconnection standard of the upstream fast peripheral interconnection standard. The first fast peripheral interconnect standard is electrically connected for data transmission.

藉由此一技術手段可以來解決先前技術所存在以單一快捷外設互聯標準控制晶片無法同時配置上游快捷外設互聯標準埠的問題,進而達成以單一快捷外設互聯標準控制晶片配置多個快捷外設互聯標準埠其中之一為上游快捷外設互聯標準埠,以對與快捷外設互聯標準控制晶片電性互連的多個系統單晶片其中之一進行數據傳輸的技術功效。 By means of this technical means, it is possible to solve the problem that the prior art has a single fast peripheral interconnection standard to control the wafer cannot simultaneously configure the upstream fast peripheral interconnection standard, thereby achieving a plurality of shortcuts for controlling the wafer configuration by a single fast peripheral interconnection standard. One of the peripheral interconnection standards, the upstream fast peripheral interconnection standard, is the technical effect of data transmission for one of a plurality of system single chips electrically interconnected with the standard peripheral control chip.

雖然本發明所揭露的實施方式如上,惟所述的內容並非用以直接限定本發明的專利保護範圍。任何本發明所屬技術領域中具有通常知識者,在不脫離本發明所揭露的精神和範圍的前提下,可以在實施的形式上及細節上作些許的更動。本發明的專利保護範圍,仍須以所附的申請專利範圍所界定者為準。 While the embodiments of the present invention have been described above, the above description is not intended to limit the scope of the invention. Any changes in the form and details of the embodiments may be made without departing from the spirit and scope of the invention. The scope of the invention is to be determined by the scope of the appended claims.

10‧‧‧快捷外設互聯標準控制晶片 10‧‧‧Fast Peripheral Interconnect Standard Control Wafer

21‧‧‧第一儲存器 21‧‧‧First storage

22‧‧‧第二儲存器 22‧‧‧Second storage

23‧‧‧第三儲存器 23‧‧‧ third storage

24‧‧‧第四儲存器 24‧‧‧ fourth storage

30‧‧‧選擇控制器 30‧‧‧Select controller

Claims (15)

一種微伺服器(microserver),其包含:至少一系統單晶片(System On Chip,SOC),每一個系統單晶片具有一第一快捷外設互聯標準(PCI-E)埠;一快捷外設互聯標準控制晶片,所述快捷外設互聯標準控制晶片具有多個第二快捷外設互聯標準埠,所述第二快捷外設互聯標準埠與所述第一快捷外設互聯標準埠分別對應進行電性連接,且所述快捷外設互聯標準控制晶片產生一第一選擇訊號;至少一儲存器,每一個儲存器與所述快捷外設互聯標準控制晶片電性連接,且每一個儲存器中儲存有一配置設定;及一選擇控制器,用以接收所述第一選擇訊號以生成多個第二選擇訊號;其中,每一個第二選擇訊號分別對應連接所述儲存器其中之一,以控制所述儲存器中所述配置設定對所述快捷外設互聯標準控制晶片進行配置,所述配置設定用以選擇所述第二快捷外設互聯標準埠其中之一設置為上游(upstream)快捷外設互聯標準埠,其於的所述第二快捷外設互聯標準埠不進行上游快捷外設互聯標準埠設置,被設置為上游快捷外設互聯標準埠的所述第二快捷外設互聯標準埠與所述第一快捷外設互聯標準埠電性連接以進行數據傳輸。 A microserver includes: at least one system on chip (SOC), each system single chip has a first fast peripheral interconnect standard (PCI-E); a fast peripheral interconnection a standard control chip, the fast peripheral interconnection standard control chip has a plurality of second shortcut peripheral interconnection standards, and the second shortcut peripheral interconnection standard is respectively corresponding to the first shortcut peripheral interconnection standard a connection, and the shortcut peripheral interconnection standard control chip generates a first selection signal; at least one memory, each of the storages is electrically connected to the shortcut peripheral interconnection standard control chip, and is stored in each storage a configuration setting; and a selection controller, configured to receive the first selection signal to generate a plurality of second selection signals; wherein each of the second selection signals is respectively connected to one of the storages to control the The configuration setting in the storage device configures the shortcut peripheral interconnection standard control chip, and the configuration setting is used to select the second shortcut peripheral interconnection standard One is set to the upstream (faststream) peripheral interconnect standard, and the second fast peripheral interconnection standard is not set by the upstream fast peripheral interconnection standard, and is set as the upstream fast peripheral interconnection standard. The second fast peripheral interconnection standard is electrically connected to the first fast peripheral interconnection standard for data transmission. 如申請專利範圍第1項所述的微伺服器,其中所述儲存器是透過晶片選擇訊號(Chip Select,CS)以及對應的第二選擇訊號進行儲存器中所述配置設定的選擇,且所述儲存器與所述快捷外設互聯標準控制晶片電性連接以傳輸被選擇的配置設定至所述快捷外設互聯標準控制晶片以進行配置。 The micro-server according to claim 1, wherein the storage device selects the configuration setting in the storage device through a chip selection signal (Chip Select, CS) and a corresponding second selection signal, and The memory and the shortcut peripheral interconnect standard control chip are electrically connected to transmit the selected configuration settings to the shortcut peripheral interconnect standard control chip for configuration. 如申請專利範圍第1項所述的微伺服器,其中所述多個第二選擇訊號中僅有一個第二選擇訊號為有效狀態。 The microserver according to claim 1, wherein only one of the plurality of second selection signals is in an active state. 如申請專利範圍第1項所述的微伺服器,其中所述選擇控制器更包含多個跳針(Jumper)以及分別與所述跳針對應的多個邏輯閘。 The microserver according to claim 1, wherein the selection controller further comprises a plurality of jumpers and a plurality of logic gates respectively corresponding to the jumps. 如申請專利範圍第4項所述的微伺服器,其中每一個跳針由一第一接腳與一第二接腳所組成,所述第一接腳與電源連接並生成一第三選擇訊號,所述第二接腳與接地連接,每一個邏輯閘分別接收所述第一選擇訊號與對應的所述第三選擇訊號進行或邏輯運算以對應生成所述第二選擇訊號。 The micro-server according to claim 4, wherein each of the jump pins is composed of a first pin and a second pin, the first pin is connected to the power source and generates a third selection signal. The second pin is connected to the ground, and each of the logic gates respectively receives the first selection signal and the corresponding third selection signal or logically operates to generate the second selection signal. 如申請專利範圍第5項所述的微伺服器,其中當跳針其中之一透過跳帽將所述第一接腳與所述第二接腳連接使被選擇,所述第一接腳所生成的所述第三選擇訊號為有效狀態,並當所述第一選擇訊號為有效狀態時,與被選擇跳針對應的邏輯閘進行或邏輯運算以對應生成有效狀態的所述第二選擇訊號,且有效狀態為邏輯低電壓狀態。 The microserver of claim 5, wherein one of the jump pins is selected by connecting the first pin to the second pin through a jump cap, the first pin The generated third selection signal is in an active state, and when the first selection signal is in an active state, performing or logical operation with the logic gate corresponding to the selected hop to correspondingly generate the second selection signal of the valid state And the active state is a logic low voltage state. 如申請專利範圍第1項所述的微伺服器,所述快捷外設互聯標準控制晶片更包含支援通用序列匯流排(Universal Serial Bus,USB)、序列ATA(Serial Advanced Technology Attachment,SATA)以及加速影像處理埠(AcceleratedGraphicsPort,AGP),以及包含處於常開狀態(always on)的一管理埠。 The micro-server of the first aspect of the patent application, the fast peripheral interconnection standard control chip further comprises a universal serial bus (USB), a serial ATA (Serial Advanced Technology Attachment, SATA), and an acceleration. Image Processing (AGP), and contains a management al in the always on state. 一種微伺服器(microserver),其包含:至少一系統單晶片(System On Chip,SOC),每一個系統單晶片具有一第一快捷外設互聯標準(PCI-E)埠;一快捷外設互聯標準控制晶片,所述快捷外設互聯標準控制晶片具有多個第二快捷外設互聯標準埠,所述第二快捷外設互聯標準埠與所述第一快捷外設互聯標準埠分別對應進行電性連接,且所述快捷外設互聯標準控制晶片產生一第一選擇訊號;至少一儲存器,每一個儲存器與所述快捷外設互聯標準控制晶片電性連 接,且每一個儲存器中儲存有一配置設定;及一選擇控制器,所述選擇控制器與每一個系統單晶片分別電性連接,以接收所述第一選擇訊號與每一個系統單晶片產生的控制訊號以生成所述第二選擇訊號,且每一個第二選擇訊號與每一個系統單晶片相互對應;其中,每一個第二選擇訊號分別對應連接所述儲存器其中之一,以控制所述儲存器中所述配置設定對所述快捷外設互聯標準控制晶片進行配置,所述配置設定用以選擇所述第二快捷外設互聯標準埠其中之一設置為上游(upstream)快捷外設互聯標準埠,其於的所述第二快捷外設互聯標準埠不進行上游快捷外設互聯標準埠設置,被設置為上游快捷外設互聯標準埠的所述第二快捷外設互聯標準埠與所述第一快捷外設互聯標準埠電性連接以進行數據傳輸。 A microserver includes: at least one system on chip (SOC), each system single chip has a first fast peripheral interconnect standard (PCI-E); a fast peripheral interconnection a standard control chip, the fast peripheral interconnection standard control chip has a plurality of second shortcut peripheral interconnection standards, and the second shortcut peripheral interconnection standard is respectively corresponding to the first shortcut peripheral interconnection standard a connection, and the shortcut peripheral interconnection standard control chip generates a first selection signal; at least one memory, each of the storage and the shortcut peripheral interconnection standard control chip electrical connection And each storage device stores a configuration setting; and a selection controller, the selection controller is electrically connected to each of the system single-chips to receive the first selection signal and each system single-chip generation Control signal to generate the second selection signal, and each second selection signal corresponds to each system single chip; wherein each second selection signal is respectively connected to one of the storages to control the The configuration setting in the storage device configures the shortcut peripheral interconnection standard control chip, and the configuration setting is used to select the second shortcut peripheral interconnection standard, one of which is set as an upstream fast peripheral device The interconnection standard 埠, the second fast peripheral interconnection standard is not set by the upstream fast peripheral interconnection standard, and is set as the second shortcut peripheral interconnection standard of the upstream fast peripheral interconnection standard 埠The first fast peripheral interconnection standard is electrically connected for data transmission. 如申請專利範圍第8項所述的微伺服器,所述選擇控制器為複雜可程式邏輯裝置(Complex Programmable Logic Device,CPLD)或是現場可程式化閘陣列(Field-Programmable Gate Array,FPGA)。 The micro-server according to claim 8, wherein the selection controller is a Complex Programmable Logic Device (CPLD) or a Field-Programmable Gate Array (FPGA). . 一種快捷外設互聯標準的選擇設定系統,其包含:一快捷外設互聯標準控制晶片,用以產生一第一選擇訊號;至少一儲存器,每一個儲存自與所述快捷外設互聯標準控制晶片電性連接,且每一個儲存器中儲存有一配置設定;及一選擇控制器,用以接收所述第一選擇訊號以生成多個第二選擇訊號,每一個第二選擇訊號分別對應連接所述儲存器其中之一,以控制所述儲存器中所述配置設定對所述快捷外設互聯標準控制晶片進行配置。 A selection and setting system for a fast peripheral interconnection standard, comprising: a shortcut peripheral interconnection standard control chip for generating a first selection signal; at least one memory, each of which is stored and connected to the shortcut peripheral standard control The chip is electrically connected, and each of the memories stores a configuration setting; and a selection controller is configured to receive the first selection signal to generate a plurality of second selection signals, and each of the second selection signals respectively corresponds to the connection One of the storages is configured to control the shortcut peripheral interconnect standard control wafer by controlling the configuration settings in the storage. 如申請專利範圍第10項所述的快捷外設互聯標準的選擇設定系統,其中所述儲存器是透過晶片選擇訊號(Chip Select,CS)以及對應的第二選擇訊號進行儲存器中所述配置設定的選擇,且所述儲存器與所述快捷外設互聯標 準控制晶片電性連接以傳輸被選擇的配置設定至所述快捷外設互聯標準控制晶片以進行配置。 The selection and setting system of the fast peripheral interconnection standard according to claim 10, wherein the storage device performs the configuration in the storage through a chip selection signal (Chip Select, CS) and a corresponding second selection signal. a set selection, and the storage device and the shortcut peripheral are interconnected The quasi-control wafer is electrically connected to transfer the selected configuration settings to the fast peripheral interconnect standard control wafer for configuration. 如申請專利範圍第10項所述的快捷外設互聯標準的選擇設定系統,其中所述多個第二選擇訊號中僅有一個第二選擇訊號為有效狀態。 The selection setting system of the shortcut peripheral interconnection standard according to claim 10, wherein only one of the plurality of second selection signals is in an active state. 如申請專利範圍第10項所述的快捷外設互聯標準的選擇設定系統,其中所述選擇控制器更包含多個跳針(Jumper)以及分別與所述跳針對應的多個邏輯閘。 The selection setting system of the shortcut peripheral interconnection standard according to claim 10, wherein the selection controller further comprises a plurality of jumpers and a plurality of logic gates respectively corresponding to the jumps. 如申請專利範圍第13項所述的快捷外設互聯標準的選擇設定系統,其中每一個跳針由一第一接腳與一第二接腳所組成,所述第一接腳與電源連接並生成一第三選擇訊號,所述第二接腳與接地連接,每一個邏輯閘分別接收所述第一選擇訊號與對應的所述第三選擇訊號進行或邏輯運算以對應生成所述第二選擇訊號。 The selection and setting system of the fast peripheral interconnection standard described in claim 13 , wherein each of the jump pins is composed of a first pin and a second pin, and the first pin is connected to the power source. Generating a third selection signal, the second pin is connected to the ground, and each of the logic gates respectively receives the first selection signal and the corresponding third selection signal or logically operates to generate the second selection Signal. 如申請專利範圍第14項所述的快捷外設互聯標準的選擇設定系統,其中當跳針其中之一透過跳帽將所述第一接腳與所述第二接腳連接使被選擇,所述第一接腳所生成的所述第三選擇訊號為有效狀態,並當所述第一選擇訊號為有效狀態時,與被選擇跳針對應的邏輯閘進行或邏輯運算以對應生成有效狀態的所述第二選擇訊號,且有效狀態為邏輯低電壓狀態。 The selection and setting system of the shortcut peripheral interconnection standard according to claim 14, wherein one of the jump pins is connected to the second pin through the jump cap to be selected. The third selection signal generated by the first pin is in an active state, and when the first selection signal is in an active state, performing or logical operation on the logic gate corresponding to the selected hop to generate an effective state. The second selection signal, and the active state is a logic low voltage state.
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