TWI535216B - Phase and/or frequency detector, phase-locked loop and operation method for the phase-locked loop - Google Patents

Description

Phase and / or frequency detector, phase locked loop and phase locked loop operating method

The present invention relates to a phase-locked loop technology, and more particularly to a phase and/or frequency detector that can solve the problem of output signal jitter of a phase-locked loop, and a phase-locked loop using the aforementioned phase and/or frequency detector The method of operation with the aforementioned phase-locked loop.

A phase-locked loop (PLL) is an automatic control circuit that can track the frequency and phase of an input signal. It mainly tracks and locks the phase and frequency of the output signal and the input signal to make the phase of the output signal. The frequency can be fixed to a preset value or a predetermined range. For now, phase-locked loops have been widely used in computers and consumer products.

However, the phase-locked loop is susceptible to noise interference, causing the output signal to have a time offset problem, that is, a so-called jitter problem, which causes a clock error.

It is an object of the present invention to provide a phase and/or frequency detector that addresses the output signal jitter of a phase locked loop.

Another object of the present invention is to provide a phase locked loop employing the aforementioned phase and/or frequency detectors.

It is still another object of the present invention to provide a method of operating a phase locked loop.

The invention provides a phase and/or frequency detector comprising a first flip-flop, a second flip-flop, a logic gate, a control circuit and a delay circuit. The first flip-flop has a first data input end, a first data output end, a first clock input end and a first reset end. The first data input terminal is electrically coupled to the power supply voltage, and the first clock input terminal is configured to receive the reference signal having the reference frequency. The second flip-flop has a second data input end, a second data output end, a second clock input end and a second reset end. The second data input terminal is electrically coupled to the power supply voltage, and the second clock input terminal is configured to receive the frequency division signal. The de-frequency signal is obtained by dividing an oscillating signal having an oscillating frequency. The logic gate is configured to receive signals output by the first data output end and the second data output end. The control circuit is configured to generate a delay control signal according to the oscillation frequency of the oscillation signal. The delay circuit is configured to change the extended time according to the delay control signal to form a reset signal and output to the first reset end and the second reset end.

The invention further provides a phase locked loop comprising a phase and / or frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a frequency divider. The phase and/or frequency detector further includes a first flip-flop, a second flip-flop, a logic gate, a control circuit and a delay circuit. The first flip-flop has a first data input end, a first data output end, a first clock input end and a first reset end. The first data input terminal is electrically coupled to the power supply voltage, and the first clock input terminal is configured to receive the reference signal having the reference frequency. The second flip-flop has a second data input end, a second data output end, a second clock input end and a second reset end. The second data input terminal is electrically coupled to the power supply voltage, and the second clock input terminal is configured to receive the frequency division signal. The de-frequency signal is obtained by dividing an oscillating signal having an oscillating frequency. The logic gate is configured to receive signals output by the first data output end and the second data output end. The control circuit is configured to generate a delay control signal according to the oscillation frequency of the oscillation signal. The delay circuit is configured to change the extended time according to the delay control signal to form a reset signal and output to the first reset end and the second reset end. The charge pump is configured to determine the magnitude of the output current according to the signal output by the first data output end and the second data output end. The loop filter is configured to generate a frequency control voltage according to an output current. The voltage controlled oscillator is used to generate an oscillation signal, and determines the magnitude of the oscillation frequency according to the frequency control voltage. The frequency divider is configured to perform frequency division on the oscillating signal according to the frequency division multiple corresponding to the frequency division control signal, thereby generating a frequency division signal.

The invention further proposes a method of operating a phase locked loop. The phase locked loop has a phase and/or frequency detector, and the phase and/or frequency detector includes a first flip flop, a second flip flop, a logic gate and a delay circuit. The first flip-flop has a first data input end, a first data output end, a first clock input end and a first reset end. The first data input terminal is electrically coupled to the power supply voltage, and the first clock input terminal is configured to receive the reference signal having the reference frequency. The second flip-flop has a second data input end, a second data output end, a second clock input end and a second reset end. The second data input end is electrically coupled to the power supply voltage, and the second clock input end is configured to receive the frequency-divided signal, wherein the frequency-divided signal is obtained by dividing the oscillation signal outputted by the phase-locked loop, and the oscillation is performed. The signal has an oscillating frequency. The logic gate is configured to receive signals output by the first data output end and the second data output end, and the delay circuit is configured to extend the rise time of the signal output by the logic gate to form a reset signal and output Up to the first reset end and the second reset end. The operation method includes the following steps: determining whether the oscillation frequency is greater than or equal to the preset frequency; and when the determination is YES, controlling the delay circuit to shorten the extended time.

In an embodiment of the phase and/or frequency detector of the present invention and an embodiment of the phase locked loop, when the oscillating frequency is less than the preset frequency, the delay control signal controls the delay circuit to increase the extended time while oscillating When the frequency is greater than or equal to the preset frequency, the delay control signal controls the delay circuit to shorten the extended time.

In an embodiment of the phase and/or frequency detector of the present invention and the phase locked loop, the control circuit includes a frequency detector and a control unit. The frequency detector is configured to receive an oscillation signal to detect an oscillation frequency, and generate a detection result accordingly. The control unit is configured to generate a delay control signal according to the detection result.

In an embodiment of the phase and/or frequency detector of the present invention and the phase locked loop, the frequency detector includes a counter. The counter is used to count the length of the activation time of the pulse of the oscillation signal to use the count value as the detection result.

In an embodiment of the phase and/or frequency detector of the present invention and the phase locked loop, the control circuit includes a voltage detector and a control unit. The voltage detector is configured to detect the magnitude of the frequency control voltage and generate a detection result accordingly. The control unit is configured to generate a delay control signal according to the detection result.

In an embodiment of the phase and/or frequency detector of the present invention and the phase-locked loop, the delay control signal is a digital control signal having a plurality of bits, and the delay circuit includes a plurality of Buffer with multiple MOS transistors. The plurality of buffers are connected in series with each other. The MOS transistor system is connected between the input end and the output end of one of the buffers, and determines whether to be turned on according to the state of one of the digital control signals.

In an embodiment of the operating method of the present invention, when the oscillation frequency is less than the preset frequency, the delay circuit is controlled to increase the extended time.

The present invention adds a delay circuit and a control circuit to the phase and/or frequency detector. In this way, the delay circuit can be used to extend the rise time of the signal output by the logic gate to further extend the up-conversion control signal (ie, the output of the first flip-flop) and the frequency-reduction control output by the phase and/or frequency detector. The rise time of the pulse of the signal (ie, the output of the second flip-flop) is used to solve the dead zone problem of the phase-locked loop, and further solve the output signal jitter problem of the phase-locked loop. In addition, the control circuit can be used to determine whether the oscillation frequency output by the phase locked loop is greater than or equal to the preset frequency, and accordingly, the power consumption of the phase locked loop is dynamically controlled. When the determination is yes, the control circuit controls the delay circuit to shorten the extended time to reduce the power consumption of the phase-locked loop operating at a high frequency; and when the determination is no, the control circuit controls the delay circuit to increase the extended time. .

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Figure 1 is a block diagram of a phase locked loop. As shown in FIG. 1, the phase locked loop 100 includes a phase and/or frequency detector 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator 140, and a frequency divider 150. The phase and/or frequency detector 110 is configured to receive the frequency division signal FDIV and the reference signal FREF having the reference frequency, and determine whether to output the up-conversion control signal UP and the frequency-down control signal DN according to the phase difference between the two. The charge pump 120 is configured to determine the magnitude of the output current CC according to the above-mentioned up-conversion control signal UP and the down-conversion control signal DN. The loop filter 130 is configured to generate the frequency control voltage CV according to the output current CC described above. The voltage controlled oscillator 140 is configured to generate the oscillation signal FOUT, and determine the oscillation frequency of the oscillation signal FOUT according to the frequency control voltage CV described above. As for the frequency divider 150, the frequency division signal FOUT is divided according to the frequency division multiple corresponding to the digital frequency division control signal (having the bit Mo~Mn), and the above-mentioned frequency division signal FDIV is generated accordingly.

Figure 2 illustrates one implementation of a phase and/or frequency detector. As shown in FIG. 2, the phase and/or frequency detector 200 includes a flip-flop 210, a flip-flop 220, and a logic gate 230. In this implementation, each flip-flop is implemented by a D-type flip-flop triggered by a rising edge, and each flip-flop has a data input terminal D, a data output terminal Q, and a clock. Input terminal CLK and reset terminal R. The data input terminals D of the two flip-flops are electrically coupled to the power supply voltage VDD. In addition, the clock input terminal CLK of the flip-flop 210 is used to receive the aforementioned reference signal FREF, and the data output terminal Q is used to output the up-conversion control signal UP. As for the flip-flop 220, the clock input terminal CLK is used to receive the aforementioned frequency-divided signal FDIV, and the data output terminal Q is used to output the frequency-down control signal DN. In addition, the logic gate 230 in this example is implemented by an AND gate.

Figure 3 is a diagram for explaining the operation of the phase and / or frequency detector. In FIG. 3, the same reference numerals as those in FIG. 2 are denoted as the same signal, and the designation t is expressed as time. Referring to FIG. 2 and FIG. 3 simultaneously, when the phase of the frequency division signal FDIV is behind the phase of the reference signal FREF, the phase and/or frequency detector 200 outputs the up-conversion control signal UP to further control the voltage-controlled oscillator at the rear end. Increase the oscillation frequency of the oscillation signal. On the contrary, when the phase of the frequency division signal FDIV leads the phase of the reference signal FREF, the phase and/or frequency detector 200 outputs the frequency reduction control signal DN to further control the voltage controlled oscillator of the back end to reduce the oscillation frequency of the oscillation signal. The phase and/or frequency detector 200 continuously controls the voltage controlled oscillator to adjust the oscillation frequency of the oscillation signal until the phase of both the reference signal FREF and the frequency division signal FDIV is locked. In this way, the oscillation frequency of the oscillation signal can be stabilized at the target frequency. In addition, as shown in FIG. 3, the length of the enable time of the pulse of both the up-regulation control signal UP and the down-conversion control signal DN represents the phase difference between the reference signal FREF and the frequency-divided signal FDIV.

However, when the phases of the reference signal FREF and the frequency division signal FDIV are very close, the phase and/or frequency detector 200 simultaneously outputs the up-conversion control signal UP and the down-conversion control signal DN, and the up-conversion control signal UP The length of the enable time of the pulse with both the frequency reduction control signal DN will be very short, as shown in FIG. FIG. 4 illustrates the timing of the up-converted control signal and the down-converted control signal at this time. In FIG. 4, the same reference numerals as those in FIG. 2 are denoted as the same signal, and the designation t is expressed as time. Since the activation time of the pulse of both the up-regulation control signal UP and the down-conversion control signal DN is very short, the charge pump of the back end cannot be operated correspondingly according to the two signals, as shown in FIG. Explain it.

Figure 5 illustrates one of the implementations of a charge pump and one of the loop filters. As shown in FIG. 5, the charge pump 510 is composed of a current source 512, a switch 514, a switch 516, and a current source 518, and the current sources 512 and 514 are electrically coupled to the power supply voltage VDD and the ground potential GND, respectively, and the switch 514. And 516 are respectively controlled by the up-conversion control signal UP and the down-conversion control signal DN to determine whether to conduct. As for the loop filter 520, it is implemented with a capacitor. Since the switches 514 and 516 are implemented by MOS transistors (metal oxide semiconductor field effect transistors, MOSFETs), when the pulse-lengths of the up-conversion control signal UP and the down-conversion control signal DN are very short. The switches 514 and 516 are too late to react and are in an off state. That is to say, at this time, the charge pump 510 does not operate, thus creating a dead zone in operation, which is illustrated in FIG.

6 is a diagram showing the relationship between the phase difference between the reference signal and the frequency-divided signal of FIG. 5 and the output current of the charge pump. In FIG. 6, the CC is indicated as the output current of the charge pump 510, the indication θ is the difference between the reference signal FREF and the frequency-divided signal FDIV, and the label DZ is represented as the dead zone described above. On the right side of the vertical axis, the case where the frequency division signal FDIV is behind the reference signal FREF is shown, and on the left side of the vertical axis, the de-frequency signal FDIV advanced reference signal FREF is shown. As for the dead zone DZ, it means that the difference between the reference signal FREF and the frequency-divided signal FDIV is very small, so that the length of the pulse of the up-conversion control signal UP and the down-conversion control signal DN is very short. Happening. As can be seen from FIG. 6, when the length of the enablement time of the pulse of both the up-converting control signal UP and the down-conversion control signal DN is very short, the charge pump 510 does not operate, thereby making its output current CC zero.

FIG. 7 is a diagram showing the correspondence between the phase difference between the reference signal and the frequency-divided signal of FIG. 5 and the frequency control voltage. In FIG. 7, the symbol CV is represented as the frequency control voltage generated by the loop filter 520, the indication θ is represented as the phase difference between the reference signal FREF and the demultiplexed signal FDIV, and the label DZ is represented as the dead zone. On the right side of the vertical axis, the case where the frequency division signal FDIV is behind the reference signal FREF is shown, and on the left side of the vertical axis, the de-frequency signal FDIV advanced reference signal FREF is shown. As for the dead zone DZ, it means that the difference between the reference signal FREF and the frequency-divided signal FDIV is very small, so that the length of the pulse of the up-conversion control signal UP and the down-conversion control signal DN is very short. Happening. It can be seen from FIG. 7 that when the length of the energization time of the pulse of both the up-converting control signal UP and the down-conversion control signal DN is very short, the charge pump 510 does not operate and the output current CC is zero, thereby making the loop The frequency control voltage CV generated by the filter 520 is also zero.

Since the length of the enable time of the pulse of both the up-regulated control signal UP and the down-converted control signal DN is very short, the charge pump 510 cannot charge or discharge the loop filter 520, so The voltage controlled oscillator of the terminal oscillates an oscillation signal with a slight error from the reference signal FREF, as shown in FIG. Figure 8 is a diagram for explaining a slight error in the oscillation signal. In Fig. 8, the FREF is indicated as a reference signal, the FOUT is indicated as the oscillation signal generated by the voltage controlled oscillator, and the t is indicated as time. As can be seen from FIG. 8, in this case, the problem of time shifting of the oscillation signal FOUT, that is, the occurrence of jitter (Jitter).

In order to solve the dead zone problem of the phase locked loop, a phase and/or frequency detector as shown in FIG. 9 can be used. In FIG. 9, the same reference numerals as those in FIG. 2 are denoted as the same object or signal. The phase and/or frequency detector 900 shown in FIG. 9 differs from the phase and/or frequency detector 200 shown in FIG. 2 in that a delay circuit 910 is added to the phase and/or frequency detector 900. The delay circuit 910 is configured to extend the rise time of the signal output by the logic gate 230 to form a reset signal and output to the reset terminal R of the flip-flops 210 and 220 (also implemented by the D-type flip-flop). . In this way, when the phase difference between the reference signal FREF and the frequency-divided signal FDIV is very small, the rise time of the pulse of the up-converting control signal UP and the down-conversion control signal DN output by the phase and/or frequency detector 900 is Will be extended, as shown in Figure 10. FIG. 10 is a diagram showing an up-converted control signal and a down-conversion control signal in which the pulse rise time has been extended. In Fig. 10, the same reference numerals as those in Fig. 9 are denoted as the same signal, and the designation t is expressed as time.

Since the rise time of the pulse of both the up-regulation control signal UP and the down-conversion control signal DN has been extended, the switch inside the charge pump can be reacted to be in the on state, so the charge pump at this time The loop filter can be charged and discharged according to the up-conversion control signal UP and the down-conversion control signal DN, thereby solving the dead zone problem in operation.

However, since the rise time of the pulse of both the up-regulation control signal UP and the down-conversion control signal DN is extended, the charge pump simultaneously charges and discharges the loop filter, so if the phase-locked loop system operates At high frequencies, the power consumption of the phase-locked loop can be significant. In addition, please refer to FIG. 5 again, since the two switches inside the charge pump 510 are generally realized by an N-type MOS transistor and a P-type MOS transistor, respectively, and the N-type MOS transistor and the P-type MOS transistor. The conduction currents of the two are not equal. Therefore, when the rise time of the pulse of both the up-conversion control signal UP and the down-conversion control signal DN is prolonged, a current mismatch between the charging current and the discharge current occurs. The frequency control voltage CV generated by the loop filter 520 is disturbed. In this case, the oscillation signal outputted by the phase-locked loop is caused to be shaken. In order to solve the aforementioned problem, a phase and/or frequency detector as shown in FIG. 11 can be employed.

11 is a circuit block diagram of a phase and/or frequency detector in accordance with an embodiment of the present invention. As shown in FIG. 11, the phase/frequency detector 1100 includes a flip-flop 1110, a flip-flop 1120, a delay circuit 1130, a logic gate 1140, and a control circuit 1150. In this implementation, each flip-flop is a D-type flip-flop that uses a positive-edge trigger, and each flip-flop has a data input terminal D, a data output terminal Q, a clock input terminal CLK, and a reset. End R. The data input terminals D of the two flip-flops are electrically coupled to the power supply voltage VDD. In addition, the clock input terminal CLK of the flip-flop 1110 is for receiving the reference signal FREF from the outside of the phase locked loop, and the data output terminal Q is for outputting the up-conversion control signal UP. As for the flip-flop 1120, the clock input terminal CLK is used to receive the frequency-divided signal FDIV, and the data output terminal Q is used to output the frequency-down control signal DN. The above-mentioned frequency-divided signal FDIV is obtained by dividing the oscillation signal outputted by the phase-locked loop, and the oscillation signal has an oscillation frequency.

In addition, the logic gate 1140 is configured to receive the signals output by the data output terminal Q of both the flip-flops 1110 and 1120, that is, the up-conversion control signal UP and the down-conversion control signal DN. In this example, the logic gate 1140 is implemented using a gate. The control circuit 1150 is configured to generate a delay control signal according to the oscillation frequency of the oscillation signal. In this example, the delay control signal is implemented as a digital control signal having bits Co~Cn. However, the delay control signal of the present invention is not limited to a digital control signal, and may also be an analog control signal. The delay circuit 1130 is configured to extend the rise time of the signal output by the logic gate 1140, and change the extended time according to the delay control signal Co~Cn (described later) to form a reset signal and output to the flip-flop. The reset end of both 1110 and 1120.

Therefore, when the oscillating frequency is less than the preset frequency, the delay control signal Co~Cn can be used to control the delay circuit 1130 to increase the extended time; and when the oscillating frequency is greater than or equal to the preset frequency, the delay control signal can be utilized. Co~Cn controls the delay circuit 1130 to shorten the extended time. In this way, the power loss of the phase-locked loop can be dynamically reduced. When the phase-locked loop operates at a high frequency, the power loss of the phase-locked loop can be reduced by shortening the delay time of the delay circuit, and the chance of jitter of the oscillation signal is reduced.

In the related description of FIG. 11, both the flip-flops 1110 and 1120 are implemented by a general D-type flip-flop, which is not intended to limit the present invention, and is generally known in the art as a general D. The type of flip-flop can be implemented by a T-type flip-flop, a JK flip-flop or an RS flip-flop. In addition, in the above description, the logic gate 1140 is implemented by a general gate and is not intended to limit the present invention. It is known to those skilled in the art that the gate system can adopt different logic gates. To achieve it. Alternatively, the phase and/or frequency detector may be a phase detector that detects only the phase, a frequency detector that only detects the frequency, or a phase and frequency detector that detects both the phase and the frequency.

Some implementations of the control circuit 1150 of Figure 11 will be described below. Please refer to FIG. 12, which is a schematic diagram of one implementation of the control circuit. As shown in FIG. 12, the control circuit 1200 includes a control unit 1210 and a frequency detector 1220. The frequency detector 1220 is electrically coupled to the output of the voltage controlled oscillator of the phase locked loop to receive the oscillation signal FOUT outputted by the voltage controlled oscillator to detect the oscillation frequency thereof, and accordingly generate the detection result DR. In this example, the frequency detector 1120 can be implemented using a counter. In this way, the counter can be used to count the length of the enable time of the pulse of the oscillation signal FOUT to use the count value as the detection result DR. The control unit 1210 is configured to generate the delay control signals Co~Cn according to the detection result DR. For example, the control unit 1210 may internally build a look-up table of the frequency detection result and the delay control signal to find the delay control signal Co~Cn corresponding to the detection result DR from the comparison table.

Please refer to FIG. 13, which is a schematic diagram of another implementation of the control circuit. As shown in FIG. 13, the control circuit 1300 includes a control unit 1310 and a voltage detector 1320. The voltage detector 1320 is electrically coupled to the input of the voltage controlled oscillator of the phase locked loop to detect the magnitude of the frequency control voltage CV received by the voltage controlled oscillator, and accordingly generates the detection result DR. The control unit 1310 is configured to generate the delay control signals Co~Cn according to the detection result DR. The reason why this can be designed is because the magnitude of the frequency control voltage CV received by the voltage controlled oscillator is proportional to the oscillation frequency of the oscillation signal it outputs. Therefore, as long as the frequency control voltage CV can be known, it can be based on The relationship between the frequency control voltage CV and the oscillation frequency of the oscillation signal corresponds to the oscillation frequency of the oscillation signal. The control unit 1310 can establish a comparison table between the detection result of the voltage and the delay control signal, so as to find the delay control signal Co~Cn corresponding to the detection result DR from the comparison table.

One of the implementations of the delay circuit 1130 in FIG. 11 will be described below. Please refer to FIG. 14, which is a schematic diagram of one of the implementations of the delay circuit. As shown in FIG. 14, delay circuit 1400 includes a plurality of MOS transistors (as indicated by reference 1410) and a plurality of buffers (as indicated by reference 1420). The buffers 1420 are connected in series with each other, and the input of each stage buffer 1420 is electrically coupled to the output of the upper stage buffer 1420. In addition, the buffer 1420 of the first stage is used to receive the output signal IN of the logic gate, and the buffer 1420 of the last stage is used to output the reset signal RS. Such a buffer concatenation architecture is generally referred to as a delay chain. Each of the buffers 1420 can be composed of an even number of serially connected inverters. In addition, each MOS transistor 1410 is connected between the input end and the output end of one of the buffers 1420, and determines whether to be turned on according to the state of one of the digital control signals Co~Cn. It is worth mentioning that although in this example, all of the MOS transistors 1410 are implemented as N-type MOS transistors, this is not intended to limit the invention, and those skilled in the art will be aware of these MOS transistors 1410. It can also be implemented by using a P-type MOS transistor, as long as the digital control signal Co~Cn is also changed.

Figure 15 is a schematic illustration of a phase locked loop in accordance with an embodiment of the present invention. As shown in FIG. 15, the phase locked loop 1500 includes a phase and/or frequency detector 1510, a charge pump 1520, a loop filter 1530, a voltage controlled oscillator 1540, and a frequency divider 1550. In addition, in this figure, the FREF is indicated as an externally input reference signal, the FDIV is indicated as a de-frequency signal, the UP is indicated as an up-converted control signal, and the DN is represented as a de-frequency control signal, indicating the CC system. It is expressed as the output current of the charge pump 1520, the CV is indicated as the frequency control voltage, the FOUT is indicated as the oscillation signal, and the Mo~Mn is indicated as the digital frequency division control signal. In this example, the control circuitry within phase and/or frequency detector 1510 is implemented using the design shown in FIG.

16 is a schematic diagram of a phase locked loop in accordance with another embodiment of the present invention. As shown in FIG. 16, the phase locked loop 1600 includes a phase and/or frequency detector 1610, a charge pump 1620, a loop filter 1630, a voltage controlled oscillator 1640, and a frequency divider 1650. Further, in this figure, the same reference numerals as those in Fig. 15 are indicated as the same signals. In this example, the control circuitry within phase and/or frequency detector 1610 is implemented using the design shown in FIG.

Figure 17 is a schematic illustration of a phase locked loop in accordance with yet another embodiment of the present invention. As shown in FIG. 17, the phase locked loop 1700 includes a phase and/or frequency detector 1710, a charge pump 1720, a loop filter 1730, a voltage controlled oscillator 1740, and a frequency divider 1750. Further, in this figure, the same reference numerals as those in Fig. 15 are indicated as the same signals. In this example, the frequency divider 1750 can transmit the received frequency division control signal Mo~Mn to the phase and/or frequency detector 1710, and the phase and/or frequency detector 1710 can be based on the frequency division control signal Mo. The frequency division multiple corresponding to ~Mn is used to know the oscillation frequency of the oscillation signal FOUT, and then the delay control signal Co~Cn is generated correspondingly according to the oscillation frequency of the oscillation signal FOUT. The reason why this can be done is because the frequency division multiple corresponding to the frequency control signal Mo~Mn is also proportional to the oscillation frequency of the oscillation signal FOUT.

With the teachings of the various embodiments described above, those skilled in the art will be able to generalize some of the basic operations of the phase-locked loop of the present invention, as shown in FIG. 18 is a flow chart of a method of operating a phase locked loop in accordance with an embodiment of the present invention. The phase locked loop has a phase and/or frequency detector, and the phase and/or frequency detector includes a first flip flop, a second flip flop, a logic gate and a delay circuit. The first flip-flop has a first data input end, a first data output end, a first clock input end and a first reset end. The first data input terminal is electrically coupled to the power supply voltage, and the first clock input terminal is configured to receive the reference signal having the reference frequency. The second flip-flop has a second data input end, a second data output end, a second clock input end and a second reset end. The second data input end is electrically coupled to the power supply voltage, and the second clock input end is configured to receive the frequency-divided signal, wherein the frequency-divided signal is obtained by dividing the oscillation signal outputted by the phase-locked loop, and the oscillation is performed. The signal has an oscillating frequency. The logic gate is configured to receive signals output by the first data output end and the second data output end, and the delay circuit is configured to extend the rise time of the signal output by the logic gate to form a reset signal and output Up to the first reset end and the second reset end. Referring to FIG. 18, the operation method includes the following steps: determining whether the oscillation frequency is greater than or equal to the preset frequency (as shown in step S1810); and when the determination is yes, controlling the delay circuit to shorten the extended time (such as the step) S1820 shows).

In addition, when the oscillation frequency is less than the preset frequency, the delay circuit is controlled to increase the extended time.

In summary, the present invention adds a delay circuit and a control circuit to the phase and/or frequency detector. In this way, the delay circuit can be used to extend the rise time of the signal output by the logic gate to further extend the up-conversion control signal (ie, the output of the first flip-flop) and the frequency-reduction control output by the phase and/or frequency detector. The rise time of the pulse of the signal (ie, the output of the second flip-flop) is used to solve the dead zone problem of the phase-locked loop, and further solve the output signal jitter problem of the phase-locked loop. In addition, the control circuit can be used to determine whether the oscillation frequency output by the phase locked loop is greater than or equal to the preset frequency, and accordingly, the power consumption of the phase locked loop is dynamically controlled. When the determination is yes, the control circuit controls the delay circuit to shorten the extended time to reduce the power consumption of the phase-locked loop operating at a high frequency; and when the determination is no, the control circuit controls the delay circuit to increase the extended time. .

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100, 1500, 1600, 1700. . . Phase-locked loop

110, 200, 900, 1100, 1510, 1610, 1710. . . Phase and / or frequency detector

120, 510, 1520, 1620, 1720. . . Charge pump

130, 520, 1530, 1630, 1730. . . Loop filter

140, 1540, 1640, 1740. . . Voltage controlled oscillator

150, 1550, 1650, 1750. . . Frequency divider

210, 220, 1110, 1120. . . Positive and negative

230, 1140. . . Logic gate

512, 518. . . Battery

514, 516. . . switch

910. . . Delay circuit

1130. . . Delay circuit

1150. . . Control circuit

1200, 1300. . . Control circuit

1210, 1310. . . control unit

1220. . . Frequency detector

1320. . . Voltage detector

1400. . . Delay circuit

1410. . . MOS transistor

1420. . . buffer

Co~Cn. . . Digital control signal

CC. . . Output current

CLK. . . Clock input

CV. . . Frequency control voltage

D. . . Data input

DN. . . Frequency reduction control signal

DR. . . Detection result

DZ. . . dead zone

FDIV. . . Frequency signal

FOUT. . . Oscillating signal

FREF. . . Reference signal

GND. . . Ground potential

IN. . . Logic gate output signal

Mo~Mn. . . Frequency division control signal

Q. . . Data output

R. . . Reset end

RS. . . Reset signal

S1810, S1820. . . step

t. . . time

UP. . . Up-converting control signal

VDD. . . voltage

θ. . . difference

Figure 1 is a block diagram of a phase locked loop.

Figure 2 illustrates one implementation of a phase and/or frequency detector.

Figure 3 is a diagram for explaining the operation of the phase and / or frequency detector.

FIG. 4 illustrates a timing of the up-convert control signal and the down-conversion control signal.

Figure 5 illustrates one of the implementations of a charge pump and one of the loop filters.

6 is a diagram showing the relationship between the phase difference between the reference signal and the frequency-divided signal of FIG. 5 and the output current of the charge pump.

FIG. 7 is a diagram showing the correspondence between the phase difference between the reference signal and the frequency-divided signal of FIG. 5 and the frequency control voltage.

Figure 8 is a diagram for explaining a slight error in the oscillation signal.

9 is a circuit block diagram of a phase and/or frequency detector.

FIG. 10 is a diagram showing an up-converted control signal and a down-conversion control signal in which the pulse rise time has been extended.

11 is a circuit block diagram of a phase and/or frequency detector in accordance with an embodiment of the present invention.

Figure 12 is a schematic illustration of one implementation of a control circuit.

Figure 13 is a schematic illustration of another implementation of a control circuit.

Figure 14 is a schematic illustration of one implementation of a delay circuit.

Figure 15 is a schematic illustration of a phase locked loop in accordance with an embodiment of the present invention.

16 is a schematic diagram of a phase locked loop in accordance with another embodiment of the present invention.

Figure 17 is a schematic illustration of a phase locked loop in accordance with yet another embodiment of the present invention.

18 is a flow chart of a method of operating a phase locked loop in accordance with an embodiment of the present invention.

1100. . . Phase and / or frequency detector

1110, 1120. . . Positive and negative

1130. . . Delay circuit

1140. . . Logic gate

1150. . . Control circuit

Co~Cn. . . Digital control signal

CLK. . . Clock input

D. . . Data input

DN. . . Frequency reduction control signal

FDIV. . . Frequency signal

FREF. . . Reference signal

Q. . . Data output

R. . . Reset end

UP. . . Up-converting control signal

VDD. . . voltage

Claims (14)

A phase and/or frequency detector includes: a first flip-flop having a first data input terminal, a first data output terminal, a first clock input terminal and a first reset terminal, the first a data input end is electrically coupled to a power supply voltage, and the first clock input end is configured to receive a reference signal having a reference frequency; a second forward/reverse device has a second data input end, a second data output end, a second clock input end and a second reset end, wherein the second data input end is electrically coupled to the power supply voltage, and the second clock input end is configured to receive a second a frequency signal, wherein the frequency-divided signal is obtained by dividing an oscillation signal having an oscillation frequency; and a logic gate is configured to receive the signal output by the first data output end and the second data output end; a circuit for generating a delay control signal according to the oscillation frequency of the oscillation signal; and a delay circuit for changing the extended time according to the delay control signal to form a reset signal and outputting to the a reset end and the second Reset the end. The phase and/or frequency detector of claim 1, wherein the delay control signal controls the delay circuit to increase the extended time when the oscillation frequency is less than a predetermined frequency, and when the oscillation frequency is When the preset frequency is greater than or equal to the preset frequency, the delay control signal controls the delay circuit to shorten the extended time. The phase and/or frequency detector of claim 1, wherein the control circuit comprises: a frequency detector for receiving the oscillation signal to detect the oscillation frequency, and generating a detection accordingly a result; and a control unit configured to generate the delay control signal according to the detection result. The phase and/or frequency detector of claim 3, wherein the frequency detector comprises: a counter for counting the length of time of the pulse of the oscillation signal to use the count value as the Detect results, . The phase and/or frequency detector of claim 1, wherein the control circuit comprises: a voltage detector for detecting a frequency control voltage received by a voltage controlled oscillator, And generating a detection result, wherein the voltage controlled oscillator is configured to generate the oscillation signal; and a control unit is configured to generate the delay control signal according to the detection result. The phase and/or frequency detector of claim 1, wherein the delay control signal is a digital control signal having a plurality of bits, and the delay circuit comprises: a plurality of buffers, the buffers And MOS transistors, each MOS transistor system is connected between the input end and the output end of one of the buffers, and determines whether to conduct according to the state of one of the digital control signals . A phase-locked loop includes: a phase and/or frequency detector, comprising: a first flip-flop having a first data input, a first data output, a first clock input, and a first a first data input terminal for electrically coupling a power supply voltage, and the first clock input terminal for receiving a reference signal having a reference frequency; a second flip-flop having a first a second data input end, a second data output end, a second clock input end and a second reset end, wherein the second data input end is electrically coupled to the power supply voltage, and the second clock The input end is configured to receive a frequency-divided signal, wherein the frequency-divided signal is obtained by dividing an oscillation signal having an oscillation frequency; and a logic gate is configured to receive the first data output end and the second data output end a signal outputted by the control circuit for generating a delay control signal according to the oscillation frequency of the oscillation signal; and a delay circuit for changing the extended time according to the delay control signal to form a weight Set the signal to output to a first reset end and a second reset end; a charge pump for determining an output current according to the signal output by the first data output end and the second data output end; a loop filter a frequency control voltage is generated according to the output current; a voltage controlled oscillator is configured to generate the oscillation signal, and the magnitude of the oscillation frequency is determined according to the frequency control voltage; and a frequency divider is configured to The frequency division signal corresponding to the frequency control signal is divided by the frequency division signal to generate the frequency division signal. The phase-locked loop of claim 7, wherein when the oscillating frequency is less than a predetermined frequency, the delay control signal controls the delay circuit to increase the extended time, and when the oscillating frequency is greater than or equal to the pre- When the frequency is set, the delay control signal controls the delay circuit to shorten the extended time. The phase-locked loop of claim 7, wherein the control circuit comprises: a frequency detector for receiving the oscillation signal to detect the oscillation frequency, and generating a detection result; and The control unit is configured to generate the delay control signal according to the detection result. The phase-locked loop of claim 9, wherein the frequency detector comprises: a counter for counting the length of time of the pulse of the oscillating signal to use the count value as the detection result. The phase-locked loop of claim 7, wherein the control circuit comprises: a voltage detector for detecting the magnitude of the frequency control voltage, and generating a detection result; and a control unit And correspondingly generating the delay control signal according to the detection result. The phase-locked loop of claim 7, wherein the delay control signal is a digital control signal having a plurality of bits, and the delay circuit comprises: a plurality of buffers, the buffers being connected in series; And a plurality of MOS transistors, each MOS transistor system is connected between the input end and the output end of one of the buffers, and determines whether to be turned on according to the state of one of the digital control signals. A method for operating a phase-locked loop, the phase-locked loop having a phase and/or frequency detector, the phase and/or frequency detector comprising a first flip-flop, a second flip-flop, and a logic gate And a delay circuit, the first flip-flop has a first data input terminal, a first data output terminal, a first clock input terminal and a first reset terminal, wherein the first data input terminal is electrically The first clock input terminal is configured to receive a reference signal having a reference frequency, and the second flip-flop has a second data input end, a second data output end, and a second time And the second data input terminal is configured to electrically couple the power voltage, and the second clock input terminal is configured to receive a frequency-divided signal, where the frequency-divided signal is The oscillation signal is outputted by the phase-locked loop, and the oscillation signal has an oscillation frequency, and the logic gate is configured to receive the signal output by the first data output end and the second data output end, and the a delay circuit for extending the output of the logic gate The rising time of the number is formed to form a reset signal and is output to the first reset end and the second reset end, the operation method includes: determining whether the oscillation frequency is greater than or equal to a preset frequency; and when determining that it is At this time, the delay circuit is controlled to shorten the extended time. The method of operation of claim 13, wherein when the oscillation frequency is less than the predetermined frequency, the delay circuit is controlled to increase the extended time.