TWI531027B - Fabrication method and structure of through silicon via - Google Patents

Description

Method and structure for wearing 矽 conduction body

The invention relates to a through silicon via (TSV) method and a structure thereof.

In semiconductor technology, the operating speed of a conventional integrated circuit is affected by the distance between interconnecting components on the wafer. The shorter the signal transmission distance, the faster the operating speed of the circuit components can be achieved. For a chip structure, the vertical distance between the two layers may be much smaller than the width of the single layer, so the three-dimensional circuit design (3D IC) of the stacked pixels in a vertical manner will significantly reduce the components on the wafer. The connection distance, which effectively increases the overall operating speed. In order to integrate different components into a single wafer stack structure, interconnect conductors are formed between the die and the die to electrically connect the various layers of components, and there is a development of TSV structures, especially in the need of better performance and higher density. Among the components of the wafer bonding process, for example, in the structure of Wafer Level Package (WLP) such as MEMS, optoelectronics and electronic components.

Nowadays, the general TSV method is to etch a via hole on the front side of the wafer by etching or laser, and then fill a conductive material such as polysilicon, copper, tungsten or the like into the via hole (Via) to form a conductive channel. (ie, interconnecting internal and external interconnect structures). Finally, the wafer or die back is thinned to expose the vias. After the TSV is completed, by stacking the wafers or the dies and joining the via holes, the wafers or the dies can be electrically connected to form a three-dimensional stacked integrated circuit (3D IC). .

It is an object of the present invention to provide a TSV method and structure thereof which can improve the problem of liner overhang at the opening of the via hole when the conductive material is filled in the via hole.

A method of fabricating a TSV structure in accordance with an embodiment of the present invention is characterized by comprising the following steps. A patterned hard mask is formed on a substrate, the patterned hard mask having an opening. A gap wall is formed on the sidewall of the opening. After forming the spacer wall, the spacer wall and the substrate are etched through the opening to form a via hole having an enlarged opening in the substrate.

A TSV structure in accordance with another embodiment of the present invention includes a substrate, a dielectric liner, and a conductive material. The substrate includes a via hole. The via hole has an opening portion and a body portion. The opening portion has an inclined shape in which the opening size is larger than the opening size in the lower portion. The body portion has a cylindrical shape, a substantially cylindrical shape, a lower cylindrical shape with a lower diameter toward the bottom, or a substantially cylindrical shape with a lower aperture toward the bottom. A dielectric liner covers the sidewalls of the vias. The conductive material fills a via having a dielectric liner covering the sidewalls.

In one embodiment of the present invention, the via hole is formed into a configuration having an opening portion and a body portion, and the opening portion of the opening portion is larger than the opening size of the lower portion to improve the occurrence of overhang at the opening. The problem.

The inventors of the present invention have found that the vertical configuration of the via hole often forms an overhang in the aperture when the via hole is filled with the conductive material, so that the via hole is not filled with the conductive material, and tears appear. Drops, voids, or hollow holes. If the aperture of the via hole is directly formed into a large feature size by using a photoresist lithography and etching process, the size minimization requirement cannot be satisfied, and further, as one embodiment shown in FIG. Fig. 2 is a partial enlarged view of Fig. 1, and it can be seen that the wall 3 of the opening 2 of the via hole 1 formed in this manner tends to have a kink 4, which also promotes Overhangs are formed during the filling, which affects the quality of the filler, such as the creation of slit cavities 5.

Referring to Figures 3 through 8, there is shown a method of fabricating a TSV structure in accordance with another embodiment of the present invention. It should be noted that the dimensions of the various figures herein are not to be taken in their true proportions, but are merely for the purpose of illustration, and the same elements in the various embodiments may have the same reference numerals.

First, referring to FIG. 3, a substrate 10 is provided. Substrate 10 can be a monocrystalline silicon, gallium arsenide (GaAs) or other materials well known in the art. The substrate thickness is generally 700 to 1000 micrometers, but is not limited thereto. Several components, such as semiconductor components, may have been disposed or formed on the substrate 10. Then, a patterned hard mask 12 is formed on the substrate 10, and the patterned hard mask 12 has an opening 14. The patterned hard mask 12 can be fabricated by a lithography and etching process, and the material can be selected to have a higher etching selectivity than the substrate. For example, when the substrate is germanium, the patterned hard mask 12 can include, for example, nitriding. Materials such as tantalum, niobium carbide, or niobium carbonitride (Si(C,N)). Then, a gap wall 18 as shown in Fig. 4 is formed on the side wall 16 of the opening 14. The gap wall 18 can be formed by, for example, referring to FIG. 3, on the surface of the patterned hard mask 12, including the sidewall 16 of the opening 14, a gap wall material layer 20 is formed, and then an etching is performed. A gap 18 as shown in Fig. 4 is formed on the side wall 16. Suitable as the material of the spacer wall 18, it is mainly necessary to have an etching rate different from that of the patterned hard mask 12, preferably the etching rate of the spacer wall 18 is compared to the etching rate of the patterned hard mask 12. Fast. When the substrate 10 is a tantalum substrate, the material of the gap wall 18 may be, for example, an oxide such as hafnium oxide, an amorphous carbon film, or a photoresist material or the like. The manner of etch back can be wet etching or dry etching.

When considering other components that have been placed or formed on the substrate, the spacers 18 are preferably fabricated by a low temperature process to avoid high temperatures from damaging existing components. For example, a low temperature (eg, 100 ° C) thin film deposition process is formed on the patterned hard mask 12 and the sidewall 16 of the opening 14 to form a gap wall material layer 20, such as a yttrium oxide film formed by low temperature deposition or The tantalum nitride film is then etched back to the spacer wall material layer 20 to obtain a spacer wall 18 of predetermined thickness and width. A wet etch process can also be performed as needed to provide the desired gap wall 18 to a desired predetermined thickness and width.

As shown in FIG. 4, after the spacers 18 are formed, the patterned hard mask 12 and the spacers 18 are used as masks, and the substrate 10 is etched through the openings 14 to form a via. Wherein, although the etching rate of the spacers 18 is preferably faster than the etching rate of the patterned hard mask 12, the etching rate of the spacers 18 may be greater than, less than or equal to the etching rate of the substrate 10. During the etching process, the spacers 18 are gradually removed by etching simultaneously with the substrate 10 exposed by the openings. Since the thickness of the gap wall 18 is substantially thinner from the end of the side wall 16 toward the center of the opening, the outer edge 19 near the center of the opening is the thinnest, and is first removed by etching, and the lower substrate 10 is lost. The mask is initially etched, such that the spacer 18 is gradually removed from the outer edge 19 toward the side wall 16 over time, and the lower substrate 10 also gradually increases the etched area in this direction, thereby forming in the substrate 10. A recessed hole having a flared shape. As shown in FIG. 5, it is shown that the spacer wall 18 is completely removed by an etching process 22, such as an anisotropic dry etching process, and is etched in the substrate 10 to form an opening having inclined sidewalls. twenty four. The etching process 22 continues, after the gap wall 18 is completely removed, the patterning of the hard mask 12 continues as a mask, and the substrate 10 exposed by the opening 24 continues to be etched, the substrate 10 being The etching rate at the bottom of the opening is greater than the etching rate of the sidewall, and a via hole 26 as shown in FIG. 6 is formed, which has an opening portion 28 and a body portion 30.

The opening portion 28 has a tapered shape in which the opening size is larger than the opening size below. The inclined surface (the side wall of the opening) may be a flat surface, but is not limited thereto, or may be a curved surface or a folded surface as long as the opening size of the opening portion is larger than the opening size of the lower portion. The body portion 30 is directly adjacent to the opening portion 28 and has a side wall that is vertically or slightly inclined inwardly to be substantially vertical; in other words, the side wall of the body portion 30 has no significant vertices in the vertical direction. In one case, the opening size (also referred to as the aperture) anywhere in the opening portion 28 may be greater than or equal to the aperture of the horizontal section at any point of the body portion 30. In detail, the body portion 30 has a cylindrical shape, a substantially cylindrical shape, a cylindrical shape in which the lower aperture is tapered toward the bottom, or a substantially cylindrical shape in which the lower aperture is gradually reduced toward the bottom. In other words, the body portion 30 is Cylindrical holes, or cylindrical holes that taper to the bottom. As used herein, "columnar" refers to all cylinders and is not limited to cylindrical. The absolute value of the slope of a side wall 32 of the opening portion 28 is smaller than the absolute value of the slope of a side wall 34 of the body portion 30. The vias 26 may be sized from about 1 to 20 microns in aperture and from about 10 to 200 microns in depth, or about 10 microns (aperture) by 60 microns (hole depth).

The opening is the opening of the via hole and its vicinity, so the depth is much smaller than the depth occupied by the body portion, and the depth of the opening is not particularly limited. The thickness of the gap (for example, 2800 angstroms), the width, and the etching selectivity can be used to control the opening slope, and the depth of the opening is also controlled. The process by which the gap wall is consumed is the extent to which the reaction opening is tilted. For example, when the thickness and width of the same gap wall, that is, the shape are the same, the etching selectivity of the substrate to the gap wall is higher, that is, the etching rate of the substrate relative to the etching rate of the gap wall. When the angle is larger, the degree of inclination of the formed opening portion is larger or steeper in terms of the absolute value of the slope of the side wall of the opening portion. For example, in the etching selection ratio of the same substrate to the gap wall, the shape thickness of the gap wall is higher, and the degree of inclination of the formed opening portion is greater in terms of the absolute value of the slope of the side wall of the opening portion. Big, or steeper. The bottom shape of the body portion generally corresponds to the shape in which the substrate is exposed through the gap wall in the opening before etching, that is, corresponding to the width of the gap wall. The final shape of the vias is still determined by the final etching result, but due to the features of the process of the present invention, the vias have a relatively enlarged opening as compared to conventional configurations.

FIGS. 7 and 8 show still another embodiment in which, as shown in FIG. 7, which shows that the gap wall is removed by the etching process 22, the absolute value of the sidewall slope of the opening 36 is lower than that of the first embodiment. The absolute value of the slope of the side wall of the opening 24 shown in Fig. 5 is large, that is, steep. Moreover, since the etching rate of the substrate is large with respect to the etching rate of the spacer wall, a cylindrical recess has also been etched toward the bottom of the substrate 10 at the bottom of the opening 36. The etching is continued to obtain the via hole 38 as shown in FIG. The patterned hard mask 12 may be gradually removed as the etching process progresses, or if there is residue, stripping may be performed.

After the substrate is made to have the flared via holes as described above, the conductive material is filled in, thereby avoiding the liner overhang caused by the vertical shape, and thus avoiding the metal gap fill voiding. )The problem. Referring to FIG. 9, the sidewalls and the bottom of the via hole 40 obtained by the above method are covered with a dielectric liner 42 and then filled with a conductive material 44 for further thinning process, for example, by the substrate back surface 46. Polishing (e.g., chemical mechanical polishing) to the filled conductive material 44 is exposed, i.e., a specific embodiment of a TSV structure 48 in accordance with the present invention. The dielectric liner 42 can be a single layer structure or a multilayer structure. A barrier layer 50 may be further disposed between the dielectric liner 42 and the conductive material 44 in the via hole, and a buffer layer may be disposed between the barrier layer 50 and the conductive material 44 as needed. Conductive material 44 can be a metallic material such as Cu, W, Al, and the like. The barrier layer 50 may be a material such as Ti/TiN, Ta/TaN, or the like.

The method of fabricating a TSV structure according to the present invention can be applied to front side (Via-First), Via-Middle, or Via-Last technology of Frontside or Backside. . This is explained by Frontside Via-Last, which is the front-end-of-line (FEOL) and the back-end-of-line (BEOL) of the traditional IC process. After completion, the desired via holes are formed by etching, and then a dielectric liner, a desired barrier layer, a buffer layer as needed, and a conductive electrode are sequentially filled, and finally planarized and electrically formed. A redistribution layer and a pad layer connected to the conductive electrode. In addition, when applied to the implementation of the intermediate manufacturing process, the TSV is introduced between the front-end process and the back-end process of the conventional IC process, and the process of the redistribution layer and the pad layer is omitted, so after the entire TSV structure is completed, Then, a semiconductor back-end process, such as forming a metal interconnect or a contact pad, is used to connect the TSV to the component and the signal source by using the wiring of the back-end process. When a perforated intermediate or perforated final preparation is used, it is preferred to use a low temperature oxide film to form a gap wall. When applied to the practice of punching priority production, that is, the TSV is completed before the previous process of the conventional IC process is performed.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1, 26, 38, 40. . . Via

2, 28. . . Opening

3, 16, 32, 34. . . Side wall

4. . . Knot

5. . . Gap cavity

10. . . Substrate

12. . . Patterned hard mask

14, 24, 36. . . Opening

18. . . Clearance wall

20. . . Gap material layer

twenty two. . . Etching process

30. . . Body part

42. . . Dielectric liner

44. . . Conductive material

46. . . Back side of substrate

48. . . TSV structure

50. . . Barrier layer

Fig. 1 is a scanning electron micrograph showing the formation of a kink on the opening wall of the via hole.

Fig. 2 is a partial enlarged view of Fig. 1.

3 through 6 are schematic cross-sectional views showing a method of fabricating a TSV structure in accordance with another embodiment of the present invention.

7 through 8 are schematic cross-sectional views showing a method of fabricating a TSV structure in accordance with still another embodiment of the present invention.

Figure 9 is a schematic cross-sectional view of a TSV structure in accordance with yet another embodiment of the present invention.

10. . . Substrate

12. . . Patterned hard mask

14. . . Opening

16. . . Side wall

18. . . Clearance wall

Claims (11)

A method of fabricating a through-hole via structure includes: forming a patterned hard mask on a substrate, the patterned hard mask having an opening; forming a gap wall on a sidewall of the opening; and forming After the gap wall, the gap wall and the substrate are etched through the opening to form a via hole having an enlarged opening in the substrate. A method of fabricating a through-conductor via structure as claimed in claim 1 wherein the etch rate of the spacer wall is faster than the etch rate of the patterned hard mask. A method of fabricating a through-via via structure as claimed in claim 1 wherein the etch rate of the spacer is between an etch rate of the patterned hard mask and an etch rate of the substrate. The method of fabricating a through-conductor structure according to claim 1, wherein the step of forming the spacer on the sidewall of the opening comprises: performing a low temperature thin film deposition process on the patterned hard mask and the opening Forming a gap wall material layer on the sidewall; and etching back the gap wall material layer. The method of fabricating a through-conductor structure according to claim 1, wherein the step of forming the spacer on the sidewall of the opening comprises: performing a low temperature thin film deposition process on the patterned hard mask and the opening Forming a wall a gap wall material layer; an etch back process for the gap wall material layer; and a wet etching process to form the gap wall to have a predetermined thickness and width. The method of fabricating a through-conductor via structure according to any one of claims 1 to 5, wherein the spacer and the substrate are etched through the opening to form the via hole system having an enlarged opening It is carried out using an anisotropic dry etching process. A through-hole via structure includes: a substrate including a via hole, the via hole having an opening portion and a body portion directly adjacent to the body portion, the opening portion having an opening size on the upper portion The body portion has a cylindrical shape, a substantially cylindrical shape, a lower cylindrical shape with a lower diameter toward the bottom, or a substantially cylindrical shape with a lower aperture toward the bottom; a dielectric liner covering the sidewall of the via; and a conductive material filling the via having a dielectric liner covering the sidewall. The through-conductor structure of claim 7, wherein a sidewall of the opening has a first slope and a sidewall of the body has a second slope, the absolute value of the first slope being less than the second slope The absolute value. The through-conductor structure according to claim 7 or 8, wherein the dielectric liner comprises a Multi-layer structure. The through-conductor via structure of claim 7 or 8, further comprising a barrier layer between the dielectric liner and the conductive material in the via. The through-conductor via structure of claim 9, further comprising a barrier layer between the dielectric liner and the conductive material in the via.