TWI530972B - Embedded capacitor structure and the forming method thereof - Google Patents

Description

Embedded capacitor structure and forming method thereof

The present invention relates to an embedded capacitor structure, and more particularly to a method of depositing a tantalum nitride layer to form an embedded capacitor structure.

The integrated circuit integrates various electronic components into a semiconductor substrate in a miniaturized manner, and thus there is a demand for completing the capacitor in the integrated circuit. However, the conventional embedded capacitor process is too complicated. For example, it is necessary to perform multiple tantalum nitride deposition processes at different stages to complete the necessary structures of the conventional capacitors, resulting in excessive manufacturing cost of the product, and how to improve the practice. Knowing the lack of embedded capacitors is the main purpose of developing this case.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an embedded capacitor structure forming method which reduces the number of times of tantalum nitride layer deposition in a process to reduce process cost.

The present invention provides a method for forming an embedded capacitor structure, comprising the steps of: providing a substrate having a first dielectric layer, and having a trench in the first dielectric layer; forming a capacitor structure on the bottom surface of the trench, the capacitor structure including the first a metal layer, a capacitor insulating layer and a second metal layer exposed on a surface of the first metal layer on the bottom surface of the trench; a cover layer formed on the upper surface, the inner surface and the capacitor structure of the trench; Forming a second dielectric layer thereon; and removing a portion of the second dielectric layer and a portion of the cap layer in the trench to form a plurality of contact window structures, the plurality of contact window structures exposing a portion of the surface of the first metal layer And a portion of the surface of the second metal layer.

In an embodiment of the invention, the first dielectric layer is cerium oxide or It is Fluorinated Silica Glass (FSG).

In an embodiment of the invention, the forming the capacitor structure comprises the steps of: forming a first metal layer on the upper surface, the inner surface and the bottom surface of the trench; forming a capacitive insulating layer on the surface of the first metal layer; Forming a second metal layer on the surface of the capacitor insulating layer; forming an underlying anti-reflective coating layer on the second metal layer; the bottom anti-reflective coating layer fills the trench; forming a capacitive structure pattern over the bottom anti-reflective coating layer a photoresist layer; and etching to remove the underlying anti-reflective coating layer, a portion of the second metal layer, a portion of the capacitor insulating layer, and a portion of the first metal layer to form a capacitor structure on the underlying surface of the trench, and A portion of the surface of the first metal layer and a portion of the surface of the second metal layer on the underlying surface of the trench are exposed.

In an embodiment of the invention, the material of the underlying anti-reflective coating layer may be tantalum nitride, hafnium oxide or hafnium oxynitride.

In an embodiment of the invention, the first metal layer on the bottom surface of the trench is in contact with a portion of the inner side surface of the trench.

In an embodiment of the invention, the first metal layer is formed to a thickness of about 1000 angstroms.

In an embodiment of the invention, the capacitor insulating layer is formed to have a thickness ranging from 300 angstroms to 600 angstroms.

In an embodiment of the invention, the second metal layer is formed to a thickness ranging from 600 angstroms to 1000 angstroms.

In one embodiment of the invention, the cover layer is formed to a thickness in the range of from 350 angstroms to 700 angstroms.

In an embodiment of the invention, the contact window structure is a single damascene structure or a dual damascene structure.

In an embodiment of the invention, the method further includes forming a metal layer formed in the plurality of contact window structures to form a plurality of conductive connection structures.

According to the above method for forming an embedded capacitor structure, the present invention further provides an embedded capacitor structure comprising: a first dielectric layer on the substrate, and a trench in the first dielectric layer; the capacitor structure is disposed on the bottom surface of the trench The capacitor structure comprises a first metal layer disposed on the bottom surface of the trench, a capacitor insulating layer disposed on the first metal layer and the second metal layer, disposed on the capacitor insulating layer, and the capacitor insulating layer and the second metal The layer is exposed on a portion of the surface of the first metal layer and has a distance from the inner surface of the trench; the cover layer is disposed on the inner surface of the trench and overlies the capacitor structure; the second dielectric layer is disposed on And a plurality of conductive connection structures disposed in the second dielectric layer and the cover layer, wherein a portion of the conductive connection structure is electrically connected to a portion of the exposed surface of the first metal layer of the capacitor structure and the other portion The conductive connection structure is electrically connected to a portion of the surface exposed by the second metal layer.

In an embodiment of the invention, the material of the first dielectric layer is cerium oxide or Fluorinated Silica Glass (FSG).

In an embodiment of the invention, the surface of the first metal layer exposed is adjacent to one side of the trench or the inner side of the two sides.

In an embodiment of the invention, the distance between the capacitive insulating layer and the second metal layer and the inner surface of the trench ranges from 0.9 um to 1 um.

In an embodiment of the invention, the material of the capacitor insulating layer is ceria, tantalum nitride, tantalum pentoxide (Ta ₂ O ₅ ), aluminum oxide or other insulating material.

In an embodiment of the invention, the material of the cover layer is tantalum nitride or tantalum carbide.

In an embodiment of the invention, the material of the second dielectric layer is tantalum pentoxide (Ta ₂ O ₅ ) or aluminum oxide (Al ₂ O ₃ ).

In an embodiment of the invention, the conductive connection structure is a single damascene structure or a dual damascene structure.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Some embodiments of the invention are described in detail below. However, the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited, and the scope of the invention will be limited.

Please refer to FIG. 1 to FIG. 6 first, which is a method for forming an embedded capacitor structure developed in the present case. Referring first to FIG. 1, a first dielectric layer 12 is formed on a substrate 10, and then a photoresist layer having a trench pattern (not shown) is formed on the first dielectric layer 12 by an optical lithography process. An etching step is performed to remove a portion of the first dielectric layer 12 according to the pattern of the photoresist layer such that a trench 122 is formed on the substrate 10 and within the first dielectric layer 12. In this embodiment, the substrate 10 can be a germanium substrate, and the first dielectric layer 12 can be germanium dioxide or Fluorinated silica glass (FSG).

Next, please refer to Figure 2. In FIG. 2, a first metal layer 22 is conformally formed on the upper surface, the inner surface, and the bottom surface of the trench 122; then the capacitive insulating layer 24 is conformally formed on the surface of the first metal layer 22; The metal layer 26 is conformally formed on the surface of the capacitive insulating layer 24. In this embodiment, the first metal layer 22 is the same material as the second metal layer 26, which may be tungsten (W), titanium (Ti), titanium tungsten (TiW), tantalum (Ta), tantalum nitride ( TaN), aluminum (Al), copper (Cu) or an alloy of the above metals. The method for forming the first metal layer 22 and the second metal layer 26 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), evaporation, plating, or the combination of the above methods, and A metal layer 22 is formed on the bottom surface of the trench 122 to a thickness of about 1000 angstroms (depending on the application). The second metal layer 26 is formed over the thickness of the capacitive insulating layer 24 in the range of 600 angstroms to 1000 angstroms (depending on the application). In addition, the material of the capacitive insulating layer 24 formed between the first metal layer 22 and the second metal layer 26 includes cerium oxide, tantalum nitride, tantalum pentoxide (Ta ₂ O ₅ ), aluminum oxide (aluminum oxide). Or other insulation materials. The capacitor insulating layer 24 may be formed by chemical vapor deposition, physical vapor deposition or other deposition methods, and the capacitor insulating layer 24 is formed between the first metal layer 22 and the second metal layer 26 in a thickness range of 300. An angstrom to 600 angstroms (or depending on the application).

Next, referring also to FIG. 2, in order to avoid interference between the incident light and the reflected light in the subsequent optical lithography process, the standing wave effect and the notching effect of the photoresist layer are caused. This causes a problem that the accuracy of pattern transfer during the lithography process is greatly reduced. Therefore, in the present invention, a bottom anti-reflection coating (BARC) 30 is formed on the second metal layer 26 and fills the trench 122. Here, the underlying anti-reflective coating layer 30 may be formed by chemical vapor deposition or other deposition methods (recommended by the inventors), and the material thereof is tantalum nitride, hafnium oxide or hafnium oxynitride.

Next, a photoresist layer having a pattern of a capacitor structure (not shown) is formed over the underlying anti-reflective coating layer 30, and then an etching step is performed to sequentially remove a portion of the underlying anti-reflective coating layer 30, a portion of the portion The second metal layer 26, the partial capacitor insulating layer 26 and a portion of the first metal layer 22. Thereafter, the underlying anti-reflective coating layer 30 is completely removed, leaving only the first metal layer 222, the capacitive insulating layer 242, and the second metal layer 262 on the bottom surface of the trench 122, and exposing the first metal layer 222. Part of the surface, and the first metal layer 222 is connected to a portion of the inner surface of the trench 122 Touch, as shown in Figure 3. Here, a portion of the surface exposed by the first metal layer 222 is adjacent to one side of the trench 122 or an inner side surface of both sides. In addition, the width of a portion of the surface exposed by the first metal layer 222 on the bottom surface of the trench 122 is the distance between the capacitive insulating layer 242 and the inner surface of the second metal layer 262 and the trench 122. It is from 0.9um to 1um. In addition, the first metal layer 222, the capacitor insulating layer 242 and the second metal layer 262 on the bottom surface of the trench 122 constitute a metal/insulating layer/metal capacitor structure 20.

Next, please refer to Figure 4. In FIG. 4, a cover layer 40 is formed on the upper surface and the inner surface of the trench (not shown) and the capacitor structure 20, and the cover layer 40 is formed as a contact window structure (not shown in the figure). The etch stop layer, in this embodiment, the cap layer 40 can be formed by chemical vapor deposition, which is formed to a thickness ranging from 350 angstroms to 700 angstroms (or depending on process capability), and the material is nitrided.矽 or tantalum carbide. Next, referring also to FIG. 4, a second dielectric layer 50 is formed over the cap layer 40 and fills the entire trench.

Next, a planarization step, such as a chemical mechanical polishing (CMP), is performed on the structure of FIG. 4, and the second dielectric layer 50 and the overlying layer 40 on the upper surface of the trench are polished. Removing, and stopping on the second dielectric layer 50 to expose a surface of the upper surface of the trench, a portion of the second dielectric layer 50 and the cover layer 40, wherein the material of the second dielectric layer 50 may have High dielectric constant dielectric materials such as tantalum pentoxide (Ta ₂ O ₅ ) or aluminum oxide (Al ₂ O ₃ ), which have a high coupling ratio using a high dielectric constant dielectric material to improve the capacitance structure Capacitance density.

Next, referring to FIG. 5, a photoresist layer having a contact window structure pattern (not shown) is formed over the substrate 10. Then, an optical lithography process is performed, which is etched to remove the portion according to the pattern of the photoresist layer. a second dielectric layer 50 and a portion of the cover layer 40, forming a first contact window in the second dielectric layer 50 and in the cover layer 40 The contact window structure 72 and the second contact window structure 74, wherein the first contact window structure 72 is formed on the first metal layer 222 and exposes a portion of the surface of the first metal layer 222, and the second contact window structure 74 is formed. A portion of the surface of the second metal layer 262 is exposed on the second metal layer 262. In this embodiment, the first contact structure 72 and/or the second contact structure 74 may be a single damascene structure or a dual damascene structure. Thereafter, as shown in FIG. 6, a metal layer, such as copper, is formed in the first contact structure 72 and the second contact structure 74 to form a first conductive connection 721 and a second conductive connection 741, respectively. Next, another planarization step, such as a chemical mechanical polishing process, is performed to remove the excess metal layer to obtain a flat metal layer surface. In this structure, one end of the first conductive connection structure 721 and the first metal layer 222 are electrically connected to each other, and one end of the second conductive connection structure 741 and the second metal layer 262 are electrically connected to each other, and the embedded capacitor is completed. structure. Therefore, the first metal layer 222 can be used as a planar electrode of the embedded capacitor structure, and the second metal layer 262 can be used as another planar electrode, and the capacitive insulating layer 242 has a font structure interposed between the two planar electrodes. between.

According to the above, the following advantages can be obtained: the embedded capacitor structure disclosed in the present invention is formed in a trench, which can reduce the spatial structure on the die and improve the capacitance of the capacitor structure.

In addition, according to the embedded capacitor structure disclosed in the present invention, only one deposition step of the tantalum nitride layer is required, and the embedded capacitor structure pattern can be defined at the same time, thereby simplifying the deposition of tantalum nitride required for forming the capacitor structure. In addition, the process steps of the embedded capacitor structure described in the present invention are all compatible with the currently mature technology, thereby simplifying the process steps and reducing the process cost. In addition, due to the exposed area of the metal layer (the first metal layer or the second metal layer) of the present case It is sufficient for the contact window structure to be aligned and formed directly on the surface of the metal layer, so that there is no problem that the contact window structure and the metal layer are misaligned and cannot be aligned, resulting in an incomplete structure.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧Substrate

12‧‧‧First dielectric layer

122‧‧‧ Ditch

20‧‧‧Capacitor structure

22, 222‧‧‧ first metal layer

24, 242‧‧‧capacitor insulation

26, 262‧‧‧ second metal layer

30‧‧‧Bottom anti-coated reflective layer

40‧‧‧ Coverage

50‧‧‧Second dielectric layer

72‧‧‧ first contact window

74‧‧‧second contact window

721‧‧‧First conductive connection structure

741‧‧‧Second conductive connection structure

1 is a schematic cross-sectional view showing a dielectric layer having a trench formed above a substrate; and FIG. 2 is a view showing a first metal layer, a capacitor insulating layer, a second metal layer, and an underlying anti-reflective coating layer sequentially formed in the trench. 3 is a schematic cross-sectional view showing the formation of a capacitor structure on the bottom surface of the trench; FIG. 4 is a schematic cross-sectional view showing the cover layer and the second dielectric layer sequentially formed on the inner surface of the trench and the capacitor structure; A schematic cross-sectional view showing the formation of a contact window structure in the trench and above the capacitor structure; and FIG. 6 is a schematic cross-sectional view showing the formation of a metal layer in the contact window structure to form a conductive connection structure.

10‧‧‧Substrate

12‧‧‧First dielectric layer

20‧‧‧Capacitor structure

222‧‧‧First metal layer

242‧‧‧Capacitive insulation

262‧‧‧Second metal layer

40‧‧‧ Coverage

50‧‧‧ third dielectric layer

72‧‧‧First contact window structure

74‧‧‧Second contact window structure

Claims (21)

An embedded capacitor structure forming method includes the steps of: providing a substrate having a first dielectric layer, and having a trench in the first dielectric layer; forming a capacitor structure embedded in the trench, the capacitor structure including a first metal layer, a second metal layer, and a capacitor insulating layer are disposed between the first metal layer and the second metal layer, wherein the capacitor insulating layer is a font, and the first metal layer and the The second metal layer is respectively a first planar electrode and a second planar electrode of the capacitor structure; a cover layer is formed along a sidewall of the trench and covers the capacitor structure; and a second dielectric layer is formed on the cover layer And removing a portion of the second dielectric layer and a portion of the cover layer in the trench to form a plurality of contact window structures for exposing portions of the first metal layer to the contact window structures a surface and a portion of the surface of the second metal layer. The method for forming an embedded capacitor structure according to claim 1, wherein the material of the first dielectric layer is cerium oxide or Fluorinated Silica Glass (FSG). The method of forming an embedded capacitor structure according to claim 1, wherein the forming the capacitor structure comprises the steps of: forming a first conformal metal along an upper surface of the trench, the sidewall surface, and a bottom surface Forming a conformal capacitive insulating layer on a surface of one of the first conformal metal layers; forming a second conformal metal layer on a surface of the conformal capacitive insulating layer; and forming a second conformal metal layer on the surface of the first conformal metal layer Forming a bottom anti-reflective coating on a surface a layer, the underlying anti-reflective coating layer fills the trench; forming a photoresist layer having a capacitive structure pattern over the underlying anti-reflective coating layer; and etching to remove the underlying anti-reflective coating layer, portion The second conformal metal layer is formed to form the second metal layer, a portion of the conformal capacitive insulating layer to form the capacitive insulating layer, and a portion of the first conformal metal layer to form the first metal layer to Forming the capacitor structure on the underlying surface of the trench and exposing a portion of a surface of the first metal layer and a surface of the second metal layer on the underlying surface of the trench. The method for forming an embedded capacitor structure according to claim 3, wherein the material of the underlying anti-reflective coating layer is tantalum nitride, hafnium oxide or hafnium oxynitride. The method of forming the method of claim 1, wherein the first metal layer on the bottom surface of the trench is in contact with a portion of the sidewall surface of the trench. The method of forming an embedded capacitor structure according to claim 1, wherein the first metal layer is formed to a thickness of about 1000 angstroms. The method for forming an embedded capacitor structure according to claim 1, wherein the planar capacitor insulating layer is formed to have a thickness ranging from 300 angstroms to 600 angstroms. The embedded capacitor structure formed as described in claim 1 The method wherein the second metal layer is formed to a thickness ranging from 600 angstroms to 1000 angstroms. The method of forming an embedded capacitor structure according to claim 1, wherein the cover layer is formed to have a thickness ranging from 350 angstroms to 700 angstroms. The method for forming an embedded capacitor structure according to claim 1, wherein the contact window structure is a single damascene structure or a dual damascene structure. The method for forming an embedded capacitor structure according to claim 1, wherein a metal layer is further formed in the contact window structure to form a plurality of conductive connection structures. An embedded capacitor structure includes: a substrate having a first dielectric layer thereon; and the first dielectric layer has a trench therein; a capacitor structure embedded in the trench, the capacitor structure includes a first a metal layer, a second metal layer and a capacitor insulating layer are disposed between the first metal layer and the second metal layer, wherein the capacitor insulating layer is in a font shape, and the first metal layer and the second layer The metal layer is respectively a first planar electrode and a second planar electrode of the capacitor structure, and the capacitive insulating layer and the second metal layer expose a portion of the surface of the first metal layer and a sidewall of the trench Having a distance therebetween; a cover layer disposed conformally on the sidewall of the trench and covering the capacitor structure; a second dielectric layer disposed on the cover layer; and a plurality of conductive connection structures, Provided on the second dielectric layer and the cover layer a portion of the conductive connection structure electrically connected to a portion of the surface of the capacitor structure exposed by the first metal layer and another portion of the conductive connection structure and the exposed portion of the second metal layer The surface is electrically connected. The embedded capacitor structure of claim 12, wherein the material of the first dielectric layer is cerium oxide or Fluorinated Silica Glass (FSG). The embedded capacitor structure of claim 12, wherein a portion of the surface exposed by the first metal layer is adjacent to one side of the trench or sidewalls of the two sides. The embedded capacitor structure of claim 12, wherein the distance between the capacitive insulating layer and the second metal layer and the inner side surface of the trench ranges from 0.9 um to 1 um. The method for forming an embedded capacitor structure according to claim 12, wherein the capacitor insulating layer is made of cerium oxide, tantalum nitride, tantalum pentoxide (Ta ₂ O ₅ ), or aluminum oxide. Or other insulating materials. The embedded capacitor structure according to claim 12, wherein the material of the cover layer is tantalum nitride or tantalum carbide. The embedded capacitor structure according to claim 12, wherein the material of the second dielectric layer is tantalum pentoxide (Ta ₂ O ₅ ) or aluminum oxide (Al ₂ O ₃ ). The embedded capacitor structure according to claim 12, wherein the conductive connection structure is a single damascene structure or a dual damascene structure. The embedded capacitor structure of claim 11, wherein among the conductive connection structures, the two conductive connection structures are in direct contact with the first metal layer. The embedded capacitor structure of claim 12, wherein the two conductive connection structures of the conductive connection structures are in direct contact with a portion of the surface of the capacitor structure exposed by the first metal layer.