TWI529739B - Storage medium and accessing system utilizing the same - Google Patents

Description

Storage medium and access system

The present invention relates to a storage medium, and more particularly to a storage medium for data transmission using a serial Peripheral Interface (SPI).

In general, the storage medium can be divided into a volatile memory (Volatile memory) and a non-volatile memory (Non-Volatile memory). When the power supply is interrupted, the memory in which the data stored in the memory disappears is called volatile memory. Compared with volatile memory, non-volatile memory becomes a storage medium for various portable digital devices because the data stored in non-volatile memory does not disappear due to power supply interruption. Common non-volatile memory includes read-only memory (ROM), programmable read-only memory (PROM), and erasable programmable read-only memory. (Erasable programmable read only memory; EPROM), Electrically erasable programmable read only memory (EEPROM), and Flash memory.

The invention provides a storage medium for data transmission with a memory controller. The memory controller provides a read command. The storage medium of the present invention includes a plurality of memory units, a control unit, and a column of decoding units. A row of decoding units and a reading unit. Each memory unit has at least sixteen memory cells. The memory cells are coupled to a word line and a plurality of bit lines. The control unit receives a first address information according to the read command, and generates a column of read signals and a row of read signals according to the first address information. The column decoding unit enables the word line based on the column read signal. The row decoding unit enables the bit line according to the row read signal to output the plurality of memory data elements stored by the sixteen memory cells. The reading unit processes the memory data element to generate a plurality of read data elements. The control unit sequentially outputs the complex read data elements to the memory controller in a serial manner.

The invention further provides an access system comprising a memory controller and a storage medium. The memory controller provides a read command and a first address information. The storage medium sequentially outputs at least sixteen read data elements to the memory controller in a serial manner according to the first address information, and includes a plurality of memory units, a control unit, a column of decoding units, a row of decoding units, and a read unit. Each memory unit has at least sixteen memory cells. The memory cells are coupled to a word line and a plurality of bit lines. The control unit generates a column of read signals and a row of read signals according to the read command and the first address information. The column decoding unit enables the word line based on the column read signal. The row decoding unit enables the bit line according to the row read signal to output the plurality of memory data elements stored by the sixteen memory cells. The reading unit processes the plurality of memory data elements for generating a plurality of read data elements. The control unit sequentially outputs the complex read data elements to the memory controller in a serial manner.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

Figure 1 is a schematic illustration of one of the access systems of the present invention. As shown, the access system 100 includes a memory controller 110 and a storage medium 120. The memory controller 110 accesses the storage medium 120. In a possible embodiment, the storage medium 120 performs data transmission with the memory controller by using a Serial Peripheral Interface (SPI) 130. The serial peripheral interface 130 has pins CLK, /CS, IO0~IO3. The pin CLK is used to transmit a clock signal. The pin/CS is used to transmit a chip select signal. Pins IO0~IO3 are used to transmit instruction packets, address packets and data packets. In addition, the present invention does not limit the kind of the storage medium 120. In this embodiment, the storage medium 120 is a non-volatile memory such as a flash memory.

In a read mode, the memory controller 110 provides a read command and a read address information to the storage medium 120 through the pins IO0~IO3. The storage medium 120 sequentially outputs at least sixteen bits of data (ie, read data elements) to the memory controller 110 in a serial manner according to the read command and the read address information. In a write mode, the memory controller 110 provides a write command and a write address information. The storage medium 120 stores the corresponding data according to the write command and the write address information.

In this embodiment, the storage medium 120 receives the read address information or the write address information through the pins IO0 IO IO3. In the write mode, the pins IO0~IO3 receive a write data provided by the memory controller 110. In the read mode, the pins IO0~IO3 output at least sixteen read data elements to the memory controller 110. In a possible embodiment, at least one of the pins IO0~IO3 outputs a read data element to the memory controller 110.

For each address information, the storage medium 120 provides at least sixteen bits of data to the memory controller 110, so that the transmission time between the memory controller 110 and the storage medium 120 can be increased.

In this embodiment, the storage medium 120 includes a control unit 121, a column of decoding units 122, a memory array 123, a row of decoding units 124, and a reading unit 125. The control unit 121 distinguishes an instruction (such as a read command or a write command) provided by the memory controller 110, and generates a corresponding control signal according to the resolved result. In a possible embodiment, the control unit 121 is an SPI command control logic.

In the read mode, the memory controller 110 provides a read command and a read address information. The control unit 121 generates a column of read signals SR _R and a row of read signals SC _R according to the read command and the read address information. In a write mode, the memory controller 110 provides a write command and a write address information. The control unit 121 generates a column of the write signal SR _W and a row of the write signal SC _w according to the write command and the write address information.

Column decoding unit 122 enables a word line within memory array 123 based on the output (SR _R or SR _W ) of control unit 121. In one possible embodiment, column decoding unit 122 has a counter (not shown) for sequentially enabling word lines within memory array 123.

The row decoding unit 124 enables the complex bit lines in the memory array 123 according to the output (SC _R or SC _W ) of the control unit 121 for outputting the memory cells corresponding to the enabled bit lines. The data, or the stored data in the memory cells corresponding to the enabled bit line. The invention does not limit the number of enabled bit lines. In this embodiment, the row decoding unit 124 enables sixteen bit lines each time for accessing sixteen memory data elements. In other embodiments, row decoding unit 124 enables thirty-two or sixty-four word lines at a time.

In a read mode, the row decoding unit 124 outputs the data elements stored by the memory cells corresponding to the enabled bit lines. In a possible embodiment, the number of data elements output by the row decoding unit 124 is a multiple of 16.

In a write mode, the control unit 121 receives a write data provided by the memory controller 110. The row decoding unit 124 writes at least one external data element to at least one of the sixteen memory cells at a time. The present invention does not limit the number of data elements written by the row decoding unit 124 each time. In a possible embodiment, the row decoding unit 124 simultaneously writes sixteen external data elements into sixteen memory cells one-to-one, or divides sixteen data elements into two groups, each group having eight Information element. In this example, the row decoding unit 124 first writes a group of data elements to the corresponding memory cells, and then writes the data elements of the other group into the corresponding memory cells. In other embodiments, row decoding unit 124 writes two, four, or six external data elements in a corresponding memory cell at a time.

The reading unit 125 processes at least sixteen memory data elements output by the row decoding unit 124 for generating a plurality of read data elements. In a possible embodiment, the reading unit 125 detects at least sixteen memory data elements output by the row decoding unit 124 to learn that the memory data element is 0 or 1. In this embodiment, the reading unit 125 amplifies the memory data elements, and then transmits the amplification results to the memory controller 110 in a serial manner through the control unit 121.

The present invention does not limit the internal architecture of the reading unit 125. In a possible embodiment, the reading unit 125 has at least sixteen detection amplifiers (not shown). Show) and at least sixteen latches (not shown). The detection amplifiers amplify the memory data elements stored in the memory cells to generate a plurality of read data elements. The latch stores the read data elements and sequentially outputs the read data elements in a serial manner. In this embodiment, the number of amplifiers and latches is the same as the number of enabled bit lines.

Figure 2 is a schematic illustration of a memory array of the present invention. As shown, the memory array 123 includes complex digital elements WL ₁ ~ WL _n , complex bit lines BL1 ₁ - BL1 ₁₆ , BL2 ₁ - BL2 ₁₆ , BLM ₁ - BLM _16, and a plurality of memory cells 200. Each memory cell 200 is coupled to a corresponding word line and bit line.

In this embodiment, every sixteen memory cells on the same word line constitute a memory unit. For example, the memory cells of the word line WL ₁ and the bit lines BL1 ₁ to BL1 ₁₆ constitute the memory unit MU ₁₁ . In other embodiments, the number of memory cells per memory unit is a multiple of 16. For example, each memory unit has thirty-two or sixty-four memory cells.

In this embodiment, each memory unit corresponds to address information. Assume that the read address information is 0000 0000 0000 0000 0000 0000. The control unit 121 generates a column read signal SR _R and a row read signal SC _R based on the read address information. Column decoding unit 122 enables word line WL ₁ based on column read signal SR _R . The row decoding unit 124 enables the bit lines BL1 ₁ BLBL1 ₁₆ to output the sixteen memory cells stored by the memory unit MU ₁₁ according to the row read signal SC _R .

In this embodiment, the number of memory cells of each memory unit is the same as the number of detection amplifiers and latches in the reading unit 125, but is not intended to limit the present invention. In other embodiments, the number of detection amplifiers and latches in the reading unit 125 may be less than the number of memory cells in each memory unit. The amount is as long as the detection amplifier and the latch in the reading unit 125 are sufficient to process the data elements stored in the memory cells of the memory unit.

For each address information, the present invention can provide at least sixteen bits of data, so that the speed of data transmission can be greatly increased, and the number of address pins is not required to be additionally increased, so that the size of the storage medium can be maintained. Furthermore, the present invention only needs to provide a single piece of information (such as address information) without providing other information (such as incremental information), so that the storage medium 120 can output at least sixteen bits of data, and therefore, Increase the complexity of access.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Access system

110‧‧‧ memory controller

120‧‧‧Storage media

130‧‧‧Listing peripheral interfaces

121‧‧‧Control unit

122‧‧‧ column decoding unit

123‧‧‧ memory array

124‧‧‧ line decoding unit

125‧‧‧Reading unit

200‧‧‧ memory cells

SR _R ‧‧‧ column read signal

SC _R ‧‧‧ lines read signals

SR _W ‧‧‧ column write signal

SC _w ‧‧‧ write signal

CLK, /CS, IO0~IO3‧‧‧ pins

WL ₁ ~ WL _n ‧‧‧ character line

BL1 ₁ ~BL1 ₁₆ , BL2 ₁ ~BL2 ₁₆ , BLM ₁ ~BLM ₁₆ ‧‧‧ bit line

MU ₁₁ ~MU _nM ‧‧‧ memory unit

Figure 1 is a schematic illustration of one of the access systems of the present invention.

Figure 2 is a schematic illustration of a memory array of the present invention.

100‧‧‧Access system

110‧‧‧ memory controller

120‧‧‧Storage media

130‧‧‧Listing peripheral interfaces

CLK, /CS, IO0~IO3‧‧‧ pins

121‧‧‧Control unit

122‧‧‧ column decoding unit

123‧‧‧ memory array

124‧‧‧ line decoding unit

125‧‧‧Reading unit

SR _R ‧‧‧ column read signal

SC _R ‧‧‧ lines read signals

SR _W ‧‧‧ column write signal

SC _w ‧‧‧ write signal

Claims (17)

A storage medium for data transmission with a memory controller, the memory controller providing a read command, the storage medium comprising: a plurality of memory units, each memory unit having at least sixteen memory cells, the sixteen The memory cell is coupled to a word line and a plurality of bit lines; a control unit having a serial peripheral interface command control logic circuit, and receiving a first address information according to the read command, and according to the first bit Address information, generating a column of read signals and a row of read signals; a column of decoding units, according to the column read signal, enabling the word line; a row of decoding units, reading signals according to the line, enabling the bit lines a plurality of memory data elements stored by the sixteen memory cells; and a reading unit that processes the memory data elements to generate a plurality of read data elements, wherein the control unit is serialized, sequentially Outputting the plurality of read data elements to the memory controller, wherein the row decoding unit enables at least sixteen bit lines at a time for accessing one of the memory cells, such that The storage medium outputs at least sixteen bits of data according to each first address information, wherein the storage medium performs data transmission with the memory controller by a serial peripheral interface, and the serial peripheral interface uses only six pins. Transmitting a clock signal, a wafer selection signal, a complex instruction packet, the first address information, and a plurality of data packets. The storage medium of claim 1, further comprising: at least one pin for receiving the first address information. The storage medium of claim 1, wherein the reading unit comprises: At least sixteen amplifiers for amplifying the memory data elements for generating the read data elements; and at least sixteen latches for storing the read data elements and sequentially outputting the reads in a serial manner Take the data element. The storage medium of claim 3, wherein the number of the amplifiers and the latches is the same and is the same as the number of memory cells of each memory unit. The storage medium of claim 1, wherein the number of memory cells per memory unit is a multiple of 16. The storage medium of claim 1, wherein when the memory controller provides a write command, the control unit receives a second address information according to the write command, and according to the second bit Address information, generating a column of write signals and a row of write signals; the column decoding unit enables the word line according to the column write signal; the row decoding unit enables the bit lines according to the row write signal For writing sixteen external data elements to the sixteen memory cells. The storage medium of claim 6, wherein the row decoding unit simultaneously writes the external data elements to the sixteen memory cells. The storage medium of claim 6, wherein the row decoding unit writes at least one external data element to at least one of the sixteen memory cells at a time. The storage medium of claim 1, wherein each memory unit corresponds to address information. An access system for a storage medium, comprising: a memory controller for providing a read command and a first bit Address information; and a storage medium for performing data transmission with the memory controller by a series of peripheral interfaces, and the serial peripheral interface transmits only one clock signal, one wafer selection signal, and a plurality of instruction packets by using the six pins. An address information and a plurality of data packets, the storage medium sequentially outputting at least sixteen read data elements to the memory controller in a serial manner according to the read command and the first address information, and includes: a plurality of a memory unit, each memory unit having at least sixteen memory cells coupled to a word line and a plurality of bit lines; a control unit having a serial peripheral interface command control logic circuit, and according to the read Taking a command, receiving the first address information, and generating a column of read signals and a row of read signals according to the first address information; a column of decoding units, enabling the word line according to the column read signal; a decoding unit, according to the row reading signal, enabling the bit line to output a plurality of memory data elements stored by the sixteen memory cells; and a reading unit for processing And a plurality of memory data elements for generating the plurality of read data elements, wherein the row decoding unit enables at least sixteen bit lines each time for accessing one of the memory units to cause the storage medium According to each first address information, at least sixteen bits of data are output. The storage medium access system of claim 10, wherein the storage medium further comprises: at least one pin for receiving the first address information. The access system of the storage medium of claim 10, wherein the reading unit comprises: at least sixteen amplifiers, and the memory data elements are enlarged to generate the And reading the data element; and at least sixteen latches, storing the read data elements, and sequentially outputting the read data elements in a serial manner. An access system for a storage medium according to claim 12, wherein the number of the amplifiers and the latches is the same and is the same as the number of memory cells of each memory unit. An access system for a storage medium according to claim 10, wherein the number of memory cells per memory unit is a multiple of 16. The access system of the storage medium of claim 10, wherein when the memory controller provides a write command, the control unit receives a second address information according to the write command, and according to the The second address information generates a column of write signals and a row of write signals; the column decoding unit enables the word line according to the column write signal; the row decoding unit enables the signal according to the row write signal An equipotential line for writing sixteen external data elements to the sixteen memory cells. An access system for a storage medium according to claim 15 wherein the row decoding unit simultaneously writes the external data elements to the sixteen memory cells. An access system for a storage medium according to claim 15, wherein the row decoding unit writes at least one external data element to at least one of the sixteen memory cells at a time.