TWI529736B - Test method and system for memory device - Google Patents

Description

Memory device test method and system

The present invention relates to a memory having a security protection function, and more particularly to a system and method for a memory having a security protection function in a test mode.

Many memory devices with security protection use a secret key to encrypt the data to be stored. Such a memory device with security protection is likely to be attacked, so that the originally stored important data is improperly accessed or changed and/or interrupted.

The method provided by the present invention is applied to a memory device operating in a test mode, comprising receiving a vector to be written into the memory device. When the vector belongs to a preset set of one of the complex test vectors, the vector is written to the memory device. When the vector does not belong to the preset set of test vectors, the vector is converted into one of the test vectors to generate a conversion vector, and the conversion vector is written into the memory device.

In some embodiments, the step of converting the vector to one of the test vectors includes selecting a one-bit set of vectors; and periodically replacing the other bits of the vector with the set of bits. In other embodiments, the values of all the even bits of each of the test vectors are equal to a first bit value, and the values of all odd bits of each of the test vectors are equal to a second bit value. And the step of converting the vector into one of the test vectors includes, in the vector, selecting a representative Singular even bits and a representative odd bit; replacing the even bits of the vector with representative even bits; and replacing the odd bits of the vector with representative odd bits.

In a possible embodiment, the method for testing a memory device of the present invention includes: reading a data character of a previously written test vector; and outputting an encoded data of the memory device, encoding the data and reading the data character It is related to the error. In another embodiment, the encoding of the output memory device includes outputting an error amount. In other embodiments, an encoded material of the output memory device includes: not outputting the actual location at which the error occurred.

In some embodiments, the step of not outputting the actual location at which the error occurred includes shifting the even bit and the odd bit, the even bits and the odd bits indicating that the error occurred in the corresponding even or odd bit . In other embodiments, an encoded material of the output memory device includes an actual location at which an output error occurs.

The invention further provides a memory device comprising a memory and a memory controller. In a test mode, the memory controller receives a vector. The vector is intended to be written into the memory. The memory controller writes the vector into the memory only when the vector belongs to one of the preset sets of the complex test vectors. When the vector does not belong to the preset set of test vectors, the memory controller converts the vector into one of the test vectors to generate a conversion vector and writes the conversion vector into the memory.

The present invention provides a test method comprising reading at least one character of a memory device in a test mode. A one-way function operation is performed on the character to generate an operation result, and the character cannot be retrieved from the operation result. according to As a result of the operation, an output error occurs in a coded information of the character.

In some embodiments, the step of reading a character comprises: receiving a public result of the one-way function after the memory device stores the character; and performing the one-way function operation on the character comprises: reading the character Then, the one-way function operation is performed on a set of characters. In other embodiments, the step of outputting the encoded information includes outputting a binary result of a comparison of the published result and the computed result. In another embodiment, the step of receiving the public result includes receiving the public result multiple times, and initiating a protection mechanism when the number of times the public result is received is greater than a predetermined threshold.

The invention further provides a memory device comprising a memory; and a memory controller. In a test mode, the memory controller reads at least one character from the memory and performs a one-way function operation on the character to generate an operation result, so that the character cannot be retrieved from the operation result. And according to the operation result, the output error occurs in a coded information of the character.

The present invention further provides a test method comprising confirming in a memory device whether a secret key has been set. When the secret key is set, a test mode of the memory device is disabled until at least the secret key in the memory device is cleared.

In some embodiments, the secret key is set in the memory device, and at least the step of clearing the secret key in the memory device includes clearing all memory spaces of the memory device.

The invention further provides a memory device comprising a memory; and a memory controller. The memory controller confirms whether a secret key has been set, and when the secret key is set, disables a test mode of the memory device until at least the secret key of the memory is cleared.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

20‧‧‧Test system

24‧‧‧ memory device

28‧‧‧Host

32‧‧‧ memory controller

34‧‧‧Memory interface

38‧‧‧Unsafe links

40‧‧‧ Non-volatile memory

44‧‧‧Mode configuration unit

48‧‧‧Selector

52‧‧‧Encryption Engine

56‧‧‧secret key unit

60‧‧‧Test read/write unit

64‧‧‧ test pattern

260, 268‧‧‧ memory area

100, 104, 108, 112, 200, 204, 208, 212, 216, 220, 224, 228 ‧ ‧ steps

Figure 1 is a schematic illustration of a test system in accordance with an embodiment of the present invention.

2 is a flow chart showing a method of secretly writing a test pattern according to an embodiment of the present invention.

3 is a flow chart showing a test method of a memory device according to an embodiment of the present invention.

4 is a schematic diagram of a method for testing a memory device using a one-way function according to an embodiment of the present invention.

The method and system provided by the present invention are for preventing a memory device from being attacked to avoid a test mode in which the memory device is not normally used. In the test mode, the test pattern is stored and read, but the test pattern is not encrypted when the test pattern is stored or read, so it is easy to know the test result. Although only authorized testers can test the memory device, because the memory device is weak in the test mode, unauthorized personnel may attempt to access or change the stored data or perform other attacks on the memory device, thus interrupting The operation of the memory device. In the following description, it is assumed that the memory device communicates with an external host (such as a tester) through an unsecure connection.

In some embodiments, the test mode is related to a small set of preset test patterns (hereinafter also referred to as test vectors). When the memory device operates in the test mode, the memory device only writes data characters that match the set of preset active patterns. Into the memory array. In addition, if a data character that does not belong to the set of test patterns is received, the memory device converts the data character into one of the preset test patterns before storing the character, and then stores the converted character. The security of the memory device is improved by defining a pattern of writes to the memory device rather than defining meaningful information.

In some embodiments, the memory device reads the previously deposited test pattern and the read result may have at least one error. The memory device converts the read pattern into one of the active patterns, and compares the conversion result with the read pattern to generate a character having an erroneous bit. This character hides the actual location where the error occurred, but the memory device can still process the character for the tester to test and debug. For example, the above process may shift the wrong bit to other bit positions. In other words, the memory device determines the number of errors, but does not tell where the error occurred. In a possible embodiment, the memory device encodes the number of errors and the most significant error bits.

In some embodiments, the host writes test data to a particular memory area (and does not need to be a neighboring area). The host further informs the memory device of a public result, which is the result of the test data stored in the specific memory region being subjected to a one-way function operation. The characteristics of the one-way function cannot push back the test data stored in the memory area. In order to test the accuracy of the test data in the memory region, the memory device again calculates the result of the one-way function and compares the recalculated result with the public result.

If the result of the recalculation is different from the public result, it means that the data read from the memory area has at least one error. The memory device will only output the binary of the comparison result, so only the necessary information will be disclosed. This test mechanism can Test the correctness of the written data, but can not guess the data.

In some embodiments, when an attack occurs, a number of different one-way function results are provided to investigate the stored data, at which point the memory device provides a protection mechanism. The memory device counts the number of received one-way function results, and when the number of times is greater than a predetermined threshold, the memory device disables the test mode or initiates a protection mechanism.

In a possible embodiment, the memory device determines whether at least one secret key has been set, and disables the test mode according to the determination result. For example, a secret key may be used for encryption and/or identification. In other embodiments, the memory device is unable to perform encryption and/or identification operations when the secret key has not been set. Therefore, after setting a secret key, in the test mode, the memory device does not write unencrypted data and/or does not read the stored data. In this example, in order to start the test, the memory device first clears all the data, including any set secret keys and other stored secret information. Of course, the memory device can also selectively clear only the set secret key or only the stored secret information.

There are many ways to achieve the above-mentioned security for improving the memory device test, such as limiting the written data must conform to a small set of test patterns, only provide the code of the test results and specific information, and only clear all secret keys and The test action is performed only when the secret data is available.

Figure 1 is a schematic illustration of a test system in accordance with an embodiment of the present invention. Test system 20 is used to test memory device 24. Test system 20 includes a host 28. The host 28 writes data and/or commands to the memory device 24 and reads data and/or test results from the memory device 24. Memory device 24 includes a memory controller 32. The memory controller 32 utilizes a memory interface 34 through an insecure link 38 communicates with the host 28.

The memory device 24 further includes a non-volatile memory 40. The non-volatile memory 40 stores the data provided by the memory controller 32 and provides the stored data to the memory controller 32 as required. In the present embodiment, the non-volatile memory 40 includes a flash memory. In another possible embodiment, the non-volatile memory 40 can include non-volatile memory generated by any other suitable technique, such as solid state hard disk (SSD), electronic erasable rewritable read only memory (EEPROM), One Programmable Read Only Memory (OTP ROM), Variable Resistive Memory (RRAM), Magnetic Storage, such as Hard Disk Drive (HDD), Optical Storage And so on. In the following description, it is assumed that the non-volatile memory 40 has a flash memory, but is not intended to limit the present invention. In other embodiments, other suitable memory may be utilized in place of the flash memory.

A mode configuration unit 44 causes the memory device 24 to operate in one of two modes of execution, such as an operational mode or a test mode. Although the test mode is generally limited to authorized users, other unauthorized users can also put the memory device into test mode.

In the operation mode, the memory controller 32 encrypts the data to be stored in the non-volatile memory 40, and uses an encryption engine 52 to retrieve the data stored in the non-volatile memory 40. In the operational mode, a selector 48 is coupled between the encryption engine 52 and the non-volatile memory 40. In other embodiments, prior to storing the data, the encryption engine 52 first encrypts the data and decrypts the data when the non-volatile memory is read.

In another embodiment, the encryption engine 52 calculates an encryption of the data. A cryptographic signature is stored and the signature is stored in non-volatile memory 40 along with the data. When the data is retrieved, the encryption engine 52 restores the correctness of the data by calculating the signature of the read data and comparing the stored signatures. A secret key unit 56 has at least one secret key for use by the encryption engine 52.

In the test mode, the memory controller 32 causes the selector 48 to be passed through the encryption engine 52 to be coupled to the non-volatile memory 40 via a test read/write unit 60. Therefore, in the test mode, the test read/write unit 60 can control the exchange of information between the non-volatile memory and the host.

In some embodiments, in the test mode, if the data is to be written to the non-volatile memory, the test read/write unit 60 writes only a small set of data characters that conform to the preset test pattern 64 to the non-volatile memory. body. Additionally, test read/write unit 60 receives and converts data from memory interface 34 into a legal test pattern, wherein the unconverted material does not conform to any portion of test pattern 64. In a possible embodiment, an unauthorized user cannot write meaningful information to the non-volatile memory, and therefore cannot change important information in the non-volatile memory.

In the test mode, when the memory device 24 reads the data stored in the non-volatile memory 40, the test read/write unit 60 confirms whether the read data has an error. The test read/write unit 60 encodes the wrong information, so that only the necessary error information is disclosed and the encoded information is provided to the host 28 via the memory interface 34. Therefore, the insecure link 38 will only transmit the minimum necessary information.

In other embodiments, the test of memory device 24 performs a one-way function operation on data stored in non-volatile memory. The one-way function conforms to two standards. The first is that the change of data is likely to cause a function. The result is changed, and the second is that the data cannot be recovered from the results.

In general, the one-way function operation is performed by the test read/write unit 60, but may also be part of the encryption engine 52 or split into the test read/write unit 60 and the encryption engine 52. When the host wants to store the data in the memory device, the test read/write unit 60 performs a one-way function operation on the data, stores the data and the operation result, and returns the data and the operation result to the host. In another possible embodiment, the host has a means for performing a one-way function result operation to generate a corresponding public result and storing the public result in a local memory of the host.

In the test mode, the host provides the public result of the one-way function operation to the test read/write unit 60 for reading back the data, and the test read/write unit 60 reads the data stored in the memory, and then performs the read data. A one-way function operation, and then compare the result of the operation with the public result provided by the host. If the two results match, it can be assumed that it is very possible to read the correct data. The test read/write unit 60 may provide only the result of the comparison or the result of the recalculation of the one-way function to the host 28.

In some embodiments, the test read/write unit 60 further maintains tracking the number of times the public result of the one-way function is received, and the published result is used to compare with the recalculated result. When the number of times of tracking is greater than a predetermined threshold, it indicates that a brute force attack is performed, and the memory device may pass the test mode to achieve the protection function or use other suitable protection mechanisms.

In some embodiments, test read/write unit 60 includes a means for detecting if secret key unit 56 is ready and can disable the memory device until the secret key and/or other important information has been cleared, later. An example will be given.

The architecture of the memory device 24 shown in Figure 1 is merely an exemplary architecture and is purely illustrative. In other embodiments, other suitable memory device architectures may be used. Different components in the memory device 24 can be realized by other suitable hardware architectures, such as an Application-Specific Integrated Circuit (ASIC) or a Field-Programmable Gate Array (FPGA). For example, the test read/write unit 60 and the encryption engine 52 are tested. In some embodiments, some of the components in memory device 24 may be implemented using a combination of software or software and hardware.

In some embodiments, certain components of test system 20, such as components of host 28 or memory controller 32, may include a general-purpose processor that can perform the functions described above using software. The software can be downloaded to the processor in an electronic format, such as a network, or provided and/or stored in non-transitory tangible media, such as magnetic, optical or electronic memory.

Figure 2 is a flow chart showing the secret writing test pattern of the present invention. In the present embodiment, steps 100, 104, 108, and 112 are performed on a memory device. Assume that the memory device operates in test mode. In addition, it is assumed that the non-volatile memory 40 stores 32-bit data, and the test pattern 64 has four 32-bit patterns as shown in Table 1 below. In Table 1, even bits have a first bit value and odd bits have a second bit value.

First, in the receiving step 100, a test word to be written from the host 28 is received by the test read/write unit 60. In the test mode, the data characters are generally one of the test patterns 64, for example, the data characters are equal to a pattern of Table 1 above. In another embodiment, the receiving step 100 utilizes the test read/write unit 60 to receive a command from the host that includes a data character to be written.

In a confirmation step 104, the test read/write unit 60 determines whether the received data character matches any of the test patterns 64. If the data character is different from all valid test patterns, in the conversion step 108, the test read/write unit converts the data character into a valid test pattern, otherwise the test read/write unit ignores the data character, so the data character is not Was changed. In the above two examples, the test read/write unit outputs an effective test pattern. In some embodiments, when the received data character does not conform to all of the test patterns, the memory device ignores the data character or the command with the data character.

Test read/write unit 60 may convert the received data characters into a valid pattern using any suitable method. In some embodiments, to perform the conversion action, the test read/write unit first selects a representative even bit and a representative odd bit from the 32 bits of the received data character. The test read/write unit may select any suitable even and odd representative bit. For example, the test read/write unit selects the most significant bit (MSB) and its adjacent bit from the received data word. Or select the least significant bit (LSB) and its adjacent bits yuan. The test read/write unit 60 then replaces the value of the even bit in the data character with the value of the selected representative even bit selected above, and replaces the data word with the value of the selected representative odd bit selected above. The value of the odd bit is used to convert the received data character into a valid test pattern. In general, the test read/write unit may select the appropriate bit from the bits of the received data character and then periodically replace the received data character with the value of the selected appropriate bit. The remaining bits are used to convert the received data characters into a valid pattern.

In one embodiment, in step 108, test read/write unit 60 copies the value of the most significant bit and its neighboring bits 15 times to convert the received data word into a valid pattern. For example, the test read/write unit converts the 32-bit data character 00XX...XXXX into a pattern 0x00000000, where x represents a binary value, which may be 0 or 1, and converts the characters 01XX...XXXX into a pattern 0x55555555 (The binary value is "0101...01010101").

In the storing step 112, the test read/write unit 60 writes the pattern generated in step 108 into the non-volatile memory 40, and ends the writing operation. As described above, the pattern generated in step 108 is an effective test pattern. .

The write flow presented in Figure 2 prevents an unauthorized user from writing meaningful information into the memory while attempting to read or tamper with the secret data or cause other damage to the memory device.

Figure 3 is a flow chart showing the test method of the memory device of the present invention. The test method of Fig. 3 can be started after the completion of the write operation of Fig. 2 or independently of the write operation of Fig. 2. In this embodiment, Steps 200, 204, 208, 212, 216, and 220 are performed on the memory device, and steps 224 and 228 are performed on the host. In Fig. 3, it is assumed that the pattern 0x55555555 (the binary value is "0101...01010101") has been previously written into the non-volatile memory. The results of writing other values are disclosed in Table 2 below.

Initially, in a read step 200, the test read/write unit 60 reads a character stored in the non-volatile memory 40. In some embodiments, the test read/write unit performs step 200 for reading at least one character in the memory according to a command (not shown) provided by the host. The 32-bit characters read in step 200 may be correct or incorrect. In Table 2, assuming that the read character has 21 errors and replaces the previously written pattern 0x55555555, the character R_WORD read by the test read/write unit 60 is 0x93209A6A.

In the read conversion step 204, the test read/write unit 60 converts the character R_WORD into one of the test patterns 64. In a possible embodiment, the conversion method of step 204 is the same as the confirmation and conversion method of steps 104 and 108 above. In Table 2, the most significant bit of the character R_WORD and its neighboring bit have a value of 10, so the character R_WORD is converted into a pattern R_PATTERN having a hexadecimal value of 0xAAAAAAAA.

In an error capture step 208, the test read/write unit 60 compares the character R_WORD with the pattern R_PATTERN using a 32-bit XOR operation, which yields a 32-bit value, represented by the symbol R_ERRORS. When the character R_WORD has no errors, all the bit values of the character R_ERRORS should be equal to zero.

In the most significant error bit extraction step 212, the test read/write unit retrieves a 32-bit character, represented by the symbol MS_ERROR_BIT, and the character MS_ERROR_BIT has only one bit having a value of 1, which is a character. The location of the most significant error bit of R_ERRORS. For example, when all the bit values of R_ERRORS are not 0, the test read/write unit 60 can clear all the bits of the character MS_ERROR_BIT, and the non-zero bit according to the leftmost value of the character R_ERRORS, The corresponding bit of the character MS_ERROR_BIT is the value 1. In Table 2, the character MS_ERROR_BIT is 0x20000000. In some embodiments, test read/write unit 60 does not provide actual information on the most significant error bit, so step 212 can be omitted.

In step 212, test read/write unit 60 retrieves a 32-bit character that includes the least significant error bit, represented by the symbol LS_ERROR_BITS. In addition to the most significant error bit, the character LS_ERROR_BITS is equal to R_ERRORS (eg XOR operations on the characters R_ERRORS and MS_ERROR_BIT). In Table 2, the character LS_ERROR_BITS is 0x198A30C0.

In error encoding step 216, test read/write unit 60 encodes the error of character LS_ERROR_BITS into a 32-bit character to find the number of errors, but it is not known which bits the error occurred in. The test read/write unit 60 processes the values of the even and odd bits of the character LS_ERROR_BITS, respectively. In the present embodiment, among the even and odd bits of the character LS_ERROR_BITS, a bit having a value of 1 is referred to as a "1" bit.

In step 216, to process the even "1" bits, the test read/write unit 60 sequentially shifts the even "1" bits of the character LS_ERROR_BITS to the active rightmost even bit. The result of the movement is as shown by the symbol EVN_SHIFT_ERRORS, and its value is 000...01010101. Among all the bits of the symbol EVN_SHIFT_ERRORS, the number of bits having a value of 1 is the number of even "1" bits of the character LS_ERROR_BITS. In Table 2, The character LS_ERROR_BITS has four even "1" bits, so the character EVE_SHIFT_ERRORS is 0x00000055.

Similarly, to process odd "1" bits, test read/write unit 60 sequentially shifts the odd "1" bits of character LS_ERROR_BITS to the active rightmost odd bit. The result of the movement is as shown by the symbol ODD_SHIFT_ERRORS, and its value is 000...101010. In the symbol ODD_SHIFT_ERRORS, the number of bits having a value of 1 represents the number of odd "1" bits of the character LS_ERROR_BITS. In Table 2, the character LS_ERROR_BITS has six odd "1" bits, so the character ODD_SHIFT_ERRORS is 0x00000AAA.

The characters EVE_SHIFT_ERRORS and ODD_SHIFT_ERRORS tell the number of errors, but do not know the actual location of the error.

In the error encoding step 220, the test read/write unit 60 integrates the most significant error bit MS_ERROR_BIT of step 212, the even-numbered displacement error character EVN_SHIFT_ERRORS of step 216 and the odd-numbered displacement error character ODD_SHIFT_ERRORS, and the pattern R_PATTERN of step 204, Generate the character ENCODED_ERRORS. In some embodiments, the integration operation of step 220 performs an XOR operation on the characters R_PATTERN, MS_BIT_ERROR, EVEN_SHIFTED_ERRORS, and ODD_SHIFTED_ERRORS. In Table 2, the character ENCODED_ERRORS is 0x8AAAA055. Next, the memory device provides the character ENCODED_ERRORS obtained in step 220 to the host 28.

In the present embodiment, the test read/write unit 60 performs an XOR operation on the character R_PATTERN twice, the first time in step 208, To capture the error, the second is in step 220 to encode the error. In addition, between the two XOR operations, the even "1" bit and the odd "1" bit are placed at other even and odd positions. If the most significant bit of the character R_WORD and its neighboring bits have an error, the value of the character R_PATTERN will be different from the stored true pattern value. In this example, the error and the correct bit in the character R_ERRORS will be switched (ie, the value 0 indicates the error bit and the value 1 indicates the correct bit), but the XOR operation in step 220 will position the error bit in order. Move back.

As described above, the test read/write unit maintains the position of the most significant error bit and shifts the position of the least significant error bit to the active rightmost side, thus maintaining the position of the most significant error bit, but not maintaining the minimum effective position. The error bit, the number of test read/write unit output errors, but does not know where the error occurred.

Next, the operation performed by the host 28 after receiving the character ENCODED_ERRORS generated in the above step 220 will be described. In a comparison step 224, the host compares the character ENCODED_ERRORS with the public test pattern (W_PATTERN). The host performs an XOR operation on the character ENCODED_ERRORS and the pattern W_PATTERN, and the operation result is represented by the symbol EST_ERRORS. As shown in Table 2, the character EST_ERRORS is 0xDFFFF500.

In error decoding step 228, the host retrieves a respective read error from the character EST_ERRORS. In this embodiment, the host retrieves the exact location of the most significant error and the number of errors. As shown in Table 2, the most significant error is located at the leftmost position and there are 21 errors.

Form 2

The test architecture of Figure 3 is just an implementation and other test architectures can be utilized. For example, in some embodiments, the host provides a public pattern to the memory device that compares the public pattern to the stored value and returns the encoded information back to the host in the event of a read error.

In the above embodiment, the erroneous coded information is read including the exact position of the most significant error and the number of errors. In another embodiment, the encoded information includes only the exact location or number of errors of the most significant error. In other embodiments, the encoded information may include other locations that are different from the most significant error (such as the location of the least significant error) and/or a number of erroneous locations.

In the present embodiment, the four test patterns shown in Table 1 are utilized. However, in another possible embodiment, any other suitable effective pattern can also be used for testing. For example, the number of test patterns may be greater than four. In other embodiments, the value of the test pattern may differ from the test pattern of Table 1.

In the test method of Figure 3, the error bit is shifted to the rightmost even or odd effective position. In another embodiment, the error bit is shifted to a position other than the rightmost even or odd effective position. For example, if a single error occurs at the location of the least significant bit, the error bit may be shifted to the position of the other odd bit.

Although the test method in Figure 3 is used to test 32-bit characters, it can also be tested in other bits.

Figure 4 is a schematic diagram of the invention for testing a memory device using a one-way function. Figure 4 includes a write period and a read period. in During writing, the host writes test data to a memory area 260 of the memory device. It is assumed that the host system transmits a public result, which is a one-way function operation result of a test data, and the test read/write unit 60 has a means for performing the same one-way function operation on the written data.

The host and test read/write unit 60 may utilize any suitable one-way function F(.) whose characteristics provide an input A, B=F(A) which is easily calculated, but cannot be pushed back against B. In addition, the probability of F(A) = F(A') for two different inputs A and A' is very low. The operations of the exemplary one-way function include cryptographic hash functions SHA-1 and SHA-2.

During the reading, the memory device judges whether or not the material stored in the memory area MEM_A is changed. The memory area 268 (indicated by the symbol MEM_A') is the same as the memory area MEM_A (i.e., has the same memory address), but the data in the memory area 268 may be different from the data originally stored in the memory area 260 due to an error.

In some embodiments, in order to test the data accuracy of the region MEM_A, the test read/write unit calculates F(MEM_A') and compares the calculated result with the public result F(MEM_A), wherein the public result F(MEM_A) is Provided by the host. The host may initialize the read period after writing the test data or at any suitable time. If F(MEM_A') is equal to F(MEM_A), it means that the data is likely to be correct. Test read/write unit 60 will only provide the tested binary pass/fail results to host 28. When only a binary pass/fail result is exposed, the test mechanism confirms whether the test data has been correctly written by comparing the data itself, rather than the signature of the data. In addition, an unauthorized user cannot know the stored data by an encrypted storage one-way function.

Unauthorized users may send out many different versions of the public one-way function results to guess the correct public results. In a possible embodiment, the test read/write unit 60 records the number of attempts to modify the data, and when the number of modifications is greater than a predetermined threshold, the test read/write unit 60 initiates appropriate protection measures, such as the test mode of the disable device. .

In some embodiments, memory device 24 performs a memory test only if the secret key is not set. In this example, if the memory device is operating in the test mode (eg, using the mode configuration unit 44) and determines that a secret key has been set, the test action will be disabled until the memory (including the secret key) is Cleared. In another possible embodiment, the memory device allows the test action to be performed when the secret key and the memory area in which the important material is stored are just cleared.

Embodiments of test system 20 have been disclosed above and are merely illustrative of the invention. In other embodiments, the test system can be implemented in other suitable ways. For example, while the above description separately discloses many embodiments, the at least two embodiments described above may be utilized simultaneously to form other test systems.

While most of the above embodiments disclose how to safely test non-volatile memory, the above-described embodiments can also be applied to other technical fields, such as to safely test any size and any kind of storage system.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Steps 100, 104, 108, 112‧‧

Claims (16)

A test method includes: operating a memory device in a test mode and receiving a vector to be written into the memory device; writing the vector when the vector belongs to a preset set of a plurality of test vectors Entering the memory device; and when the vector does not belong to the preset set of the test vectors, converting the vector to one of the test vectors to generate a conversion vector and writing the conversion vector In the memory device. The test method of claim 1, wherein the converting the vector into one of the test vectors comprises: selecting a one-bit set of the vector; and periodically replacing the set of bits with the set of bits Other bits of the vector. The test method of claim 1, further comprising: reading a data character previously written to the test vector for testing the memory device; and outputting an encoded data of the memory device, the encoded data It is related to the error that occurred when reading the data character. The test method of claim 3, wherein outputting the encoded data of the memory device comprises: outputting an error quantity, and not outputting an actual position where the error occurs; wherein the step of not outputting the actual position where the error occurs includes , shifting even bits and odd bits, the even bits and the odd bits indicate that an error occurred in the corresponding even or odd bit. The test method described in claim 3, wherein the memory device is output The set of encoded data includes: the actual location where the output error occurred. A memory device comprising: a memory; and a memory controller, in a test mode, receiving a vector to be written into the memory, only when the vector belongs to one of a plurality of test vectors When merging, the vector is written into the memory, and when the vector does not belong to the preset set of the test vectors, the vector is converted into one of the test vectors to generate a conversion vector. And the conversion vector is written into the memory. The memory device of claim 6, wherein the memory controller selects one of the bit sets of the vector and periodically replaces the other bits of the vector with the set of bits. The memory device of claim 6, wherein the memory controller reads a data character previously written into the test vector and outputs a coded information to the memory device according to an error occurring in the data character. . The memory device of claim 8, wherein the memory controller outputs an error quantity, and does not output an actual position where the error occurs; wherein the memory controller shifts the complex even bit and the complex odd bit by The element is used to not output the location where the error occurred, and the even and odd bits represent the location where the error occurred. The memory device of claim 8, wherein the memory controller outputs the location where the error occurred. A test method includes: reading at least one character of a memory device in a test mode; Performing a one-way function operation on the character to generate an operation result, and the character cannot be re-acquired by the operation result; and outputting an error occurrence in the coded information of the character according to the operation result, wherein the code The data includes: outputting an error quantity and not outputting the actual position where the error occurred. The test method of claim 11, wherein the step of outputting the encoded information comprises outputting a binary result of a comparison result between the public result and the operation result. The test method of claim 11, wherein the step of receiving the public result comprises receiving the public result multiple times, and initiating a protection mechanism when the number of the received public results is greater than a predetermined threshold. A memory device comprising: a memory; and a memory controller, in a test mode, reading at least one character from the memory, and performing a one-way function operation on the character to generate An operation result is such that the character cannot be retrieved from the operation result, and according to the operation result, the output error occurs in an encoded information of the character, wherein the encoded data includes: outputting an error quantity, and not outputting the error occurrence The actual location. The memory device of claim 14, wherein the memory controller outputs a binary result of a comparison result between the public result and the operation result. The memory device of claim 14, wherein the memory controller receives the publicity result multiple times, and when receiving the publicly disclosed result When greater than a predetermined threshold, the memory controller initiates a protection mechanism.