TWI527050B - Data storage device and method for error correction and data reading thereof - Google Patents

Description

Data storage device, error correction method thereof, and data reading method

The present invention relates to an error correction method for a data storage device; and more particularly to an error correction method for correcting a voltage distribution.

Flash memory is a popular non-volatile data storage medium that is electrically erased and programmed. For example, NAND FLASH, which is not a gate type, is often used as a memory card, a universal flash memory device, a solid state drive (SSD), and an embedded flash. Storage media such as memory modules (eMMC).

A storage array of flash memory (eg, NAND FLASH) includes a plurality of blocks, and each block includes a plurality of pages. Since the error of the data content may occur during the access process of the flash memory, the original data is encoded and the corresponding check code is generated when the data is stored, and then the encoded data and the verification are stored. The code is in the flash memory, and when the data is read, the encoded data and the check code are read, and the read encoded data is decoded to obtain the original data. Although the encoding/decoding operation can perform debugging, there is still an upper limit to the correction capability. When an error exceeding a certain level occurs, the flash memory controller will find that the encoded data cannot be effectively decoded after the decoding operation is performed, that is, the data cannot be completely corrected into the original data, and the data is damaged.

The data storage device and the error correction method provided by the present invention can correct the voltage distribution of the target page in a non-single-order storage unit mode by correcting the voltage distribution program. In addition, the repeated reading program can repeatedly read the target page to read the data of the target page according to different reading voltages.

The invention provides a data storage device. The data storage device includes a flash memory and a controller. The flash memory is used to operate in a single-order storage unit mode and a non-single-order storage unit mode. The controller is configured to perform, in a single-stage storage unit mode, a first reading operation on a page corresponding to a first character line in the flash memory according to a read command of one host, and when the first time When the read operation reads an error corresponding to the page of the first word line that cannot be repaired by the codec, a correction voltage distribution program is executed, wherein in the correction voltage distribution program, the controller causes the flash memory Switching to the non-single-order memory cell mode, and in the non-single-order memory cell mode, writing a digital logic 1 to the most significant bit page corresponding to one of the first word lines to correct corresponding to the first word line The voltage distribution of the memory storage unit. In an embodiment of the invention, the non-single-order storage unit mode is a second-order storage unit mode.

When the non-single-order storage unit mode is the second-order storage unit mode, the controller is further configured to cause the flash memory to return to the single-order storage after the digital logic 1 writes the most significant bit page in the calibration voltage distribution program. In the unit mode, and in the single-stage storage unit mode, a second reading operation is performed on the page corresponding to the first word line. When the second read operation reads an error corresponding to the page of the first word line that cannot be repaired by the codec, the controller marks the page corresponding to the first word line as a damaged page.

In another embodiment of the invention, the non-single-order storage unit mode is a third-order storage unit mode. When the non-single-order storage unit mode is the third-order storage unit mode, the controller is further configured to write a digital logic 1 corresponding to the first character line in the third-order storage unit mode in the correction voltage distribution program. One of the central valid bit pages to correct the voltage distribution of the memory storage unit corresponding to the first word line. The controller is further configured to cause the flash memory to return to the single-order storage unit mode and the single-stage storage unit after the digital logic 1 writes the most significant bit page and the central effective bit page in the calibration voltage distribution program. In the mode, a second reading operation is performed on the page corresponding to the first word line. When the second read operation reads an error corresponding to the page of the first word line that cannot be repaired by the codec, the controller marks the page corresponding to the first word line as a damaged page.

In still another embodiment of the present invention, when the first read operation reads an error corresponding to the page of the first word line and cannot be repaired by the codec, the controller is further configured to correct the voltage distribution. Executing a repeated reading program before the program, wherein in the repeated reading program, the controller is configured to perform a voltage setting action on one of the scratchpads in the flash memory according to a repeated reading table, so as to be in the temporary register The value is used as the read voltage of the flash memory.

The invention also provides an error correction method suitable for use in a data storage device. The data storage device includes a flash memory for operating in a single-stage storage unit mode and a non-single-order storage unit mode. The error correction method includes: performing a first reading operation on a page corresponding to a first character line in the flash memory according to a read command of one host; determining that the first reading action reads the first Whether there is an error that cannot be fixed by codec when the page is used; And when the first read operation reads an error corresponding to the page of the first word line and cannot be repaired by the codec, a correction voltage distribution program is executed. The calibration voltage distribution program includes: causing the flash memory to switch to the non-single-order memory cell mode; and in the non-single-order memory cell mode, writing a digital logic 1 to the most significant bit corresponding to one of the first word lines a page to correct the voltage distribution of the memory storage unit corresponding to the first word line.

In an embodiment of the invention, the non-single-order storage unit mode is a second-order storage unit mode. In the second-order storage unit mode, the step of correcting the voltage distribution program further includes: after the digital logic 1 writes the most significant bit page, causing the flash memory to return to the single-order storage unit mode; in the single-order storage unit mode, And performing a second reading operation on the page corresponding to the first word line; when the second reading operation reads an error corresponding to the first word line, the error cannot be repaired by the codec. The page corresponding to the first word line is marked as a damaged page.

In another embodiment of the invention, the non-single-order storage unit mode is a third-order storage unit mode. The step of correcting the voltage distribution program in the non-single-order memory cell mode further includes writing a digital logic 1 to a central valid bit page corresponding to one of the first word lines in the third-order memory cell mode to correct the corresponding The voltage distribution of the memory storage unit of the first word line; after the digital logic 1 writes the most significant bit page and the central effective bit page, causing the flash memory to return to the single-order storage unit mode; In the unit mode, a second reading operation is performed on the page corresponding to the first character line; and when the second reading operation reads the page corresponding to the first character line, the encoding cannot be performed by the codec. When the error is fixed, the page corresponding to the first character line is marked as damaged. page.

In addition, when the first read operation reads an error corresponding to the page of the first word line and cannot be repaired by the codec, an embodiment of the present invention is further used to perform a repetition before correcting the voltage distribution program. The reading program, wherein the repeating the reading process comprises: performing a voltage setting action on one of the scratchpads in the flash memory according to a repeated reading table to read the value in the scratchpad as a flash memory Take the voltage.

The present invention also provides a data reading method, which is applicable to a data storage device, wherein the data storage device includes a flash memory for operating in a single-stage storage unit mode and a multi-level storage unit mode, and the data reading method includes : in the single-stage storage unit mode, performing a first reading operation on a page corresponding to a first character line in the flash memory according to a read command of one host to obtain a first data; When the first data fails to be repaired, the flash memory is switched to the multi-level storage unit mode; in the multi-level storage unit mode, a preset data is written to the most significant bit corresponding to one of the first character lines. a page; causing the flash memory to switch to the single-order storage unit mode; and reading the page of the first word line again to obtain a second data.

The present invention also provides a data reading method, which is suitable for a data storage device, wherein the data storage device comprises a flash memory for operating in a single-stage storage unit mode and a multi-level storage unit mode. The data reading method includes: performing a first reading operation of the single-order storage unit mode on a page corresponding to a first character line in the flash memory according to a read command of a host to obtain a first Data; when the first data fails to be repaired, a preset data is written in the multi-level storage unit mode to correspond to one of the first character lines. The valid bit page; reading the page of the first word line in the single-order storage unit mode to obtain a second data; and transmitting the second data to the host when the second data has no error or the error can be corrected.

electronic system;

120‧‧‧Host

140‧‧‧Data storage device

160‧‧‧ Controller

162‧‧‧ arithmetic unit

164‧‧‧Permanent memory

180‧‧‧Flash memory

1102, 1104, 1202, 1204‧‧‧ curves

S500-S516, S600-S624, S700-S716, S800-S824, S900-S910‧‧ steps

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an electronic system in accordance with one embodiment of the present invention.

Figure 2 is a table showing the correspondence between pages and word lines in the flash memory of the present invention operating in a single-order memory cell mode.

Figure 3 is a table showing the correspondence between pages and word lines in the flash memory operating mode of the present invention in a second-order memory cell mode.

Figure 4 is a table showing the correspondence between pages and word lines in the flash memory operating mode of the present invention in a third-order memory cell mode.

Figure 5 is a flow chart of an error correction method of an embodiment of the present invention.

6A-6B are flowcharts of an error correction method of another embodiment of the present invention.

Figure 7 is a flow chart showing an error correction method of another embodiment of the present invention.

8A-8B is a flow chart of an error correction method of another embodiment of the present invention.

Figure 9 is a flow chart showing a method of reading data according to an embodiment of the present invention.

Figure 10 is a flow chart showing a method of reading data according to another embodiment of the present invention.

Fig. 11 is a simulation diagram of the error rate before the target page is not read by the error correction method disclosed in the present invention.

Fig. 12 is a simulation diagram of the error rate after the target page is read by the error correction method disclosed in the present invention.

The apparatus and method of use of various embodiments of the present invention are discussed in detail below. However, it is to be noted that many of the possible inventive concepts provided by the present invention can be implemented in various specific ranges. These specific examples are only intended to illustrate the apparatus and methods of use of the present invention, but are not intended to limit the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an electronic system in accordance with one embodiment of the present invention. The electronic system 100 includes a host 120 and a data storage device 140. The data storage device 140 includes a flash memory 180 and a controller 160, and is operable according to commands issued by the host 110. The controller 160 includes an arithmetic unit 162 and a permanent memory (e.g., read only memory ROM) 164. The permanent memory 164 and the stored code and data constitute a firmware, which is executed by the operation unit 162, so that the controller 160 controls the flash memory 180 based on the firmware. The flash memory 180 includes a plurality of pages and complex digital and complex bit lines, wherein each of the word lines is used to control at least one page to select a page to be read. It should be noted that the flash memory 180 of the present invention can operate in different memory access modes, such as a single-level cell (SLC) mode and a non-single-order memory cell mode, where non-single order The (or multi-level) storage unit mode includes a Multi-Level Cell (MLC) mode and a Triple-Level Cell (TLC) mode.

For example, when the flash memory 180 operates in the single-stage storage unit mode, a memory storage unit (cell) of the flash memory 180 is used to store 1-bit data and a word position. The meta line is used to control to one page The corresponding relationship between the character line and the page is as shown in Fig. 2. Figure 2 is a table showing the correspondence between pages and word lines in the single-order memory cell mode of the flash memory of the present invention. As can be seen from FIG. 2, each character line in the flash memory 180 corresponds to one page. In other words, in the single-order storage unit mode, one word line corresponds to one page. In addition, since the flash memory 180 operates in the single-stage storage unit mode, one memory storage unit needs to store one bit. Therefore, in the voltage distribution, the flash memory 180 requires two information levels to store data, wherein the two information states correspond to 0 and 1, respectively.

When the flash memory 180 operates in the second-order storage unit mode, a memory storage unit (cell) of the flash memory 180 is used to store 2-bit data, and a word bit line is used to control To two pages, where the correspondence between the word line and the page is as shown in Figure 3. Figure 3 is a table showing the correspondence between pages and word lines in the second-order storage unit mode of the flash memory of the present invention. As can be seen from FIG. 3, each word line is used to control a Least-Significant Bit Page (LSB page) and a Most-Significant Bit Page (MSB page). In other words, in the second-order storage unit mode, one word line corresponds to two pages. In addition, since the flash memory 180 operates in the second-order storage unit mode, one memory storage unit needs to store two bits. Therefore, in the voltage distribution, the flash memory 180 requires four information levels to store data, wherein the two information states correspond to 00, 01, 10, and 11, respectively, and the four information states are The two information states in the order storage unit mode are respectively separated.

When the flash memory 180 operates in the third-order storage unit mode, one of the memory cells in the flash memory 180 is used to store the 3-bit memory. (bit) data, and a word bit line is used to control to three pages, wherein the correspondence between the word line and the page is as shown in FIG. Figure 4 is a table showing the correspondence between pages and word lines in the second-order storage unit mode of the flash memory of the present invention. As can be seen from FIG. 4, each word line is used to control a least significant bit page, a Central Significant Bit page (CSB page), and a most significant bit page. In other words, in the third-order storage unit mode, one word line corresponds to three pages. In addition, since the flash memory 180 operates in the third-order storage unit mode, one memory storage unit needs to store three bits. Therefore, in the voltage distribution, the flash memory 180 requires eight information levels to store data, wherein the two information states correspond to 000, 001, 010, 011, 100, 101, 110, and 111, respectively. The eight information states are respectively separated from the four information states in the second-order storage unit mode.

According to the technique disclosed in the present disclosure, the tough system is designed to provide an error correction method required for the host 120 to read the flash memory 180 to correct the data that cannot be read by the normal program. For example, when the controller 160 makes a data error in reading the flash memory 180 and cannot successfully correct the error by using an error-correcting code (ECC), the controller 160 can be disclosed by the present invention. The error correction method corrects the data that cannot be read. The error correction method disclosed in the present invention includes a correction voltage distribution program, but the present invention is not limited thereto. In another embodiment of the invention, the error correction method includes a correction voltage distribution program and a repeat reading procedure. The calibration voltage distribution program disclosed in the present invention corrects the voltage distribution of the memory storage unit (Cell) in the corresponding bit line by switching the memory access mode.

For example, in one embodiment of the invention, the controller 160 will The operation mode is switched from the single-order storage unit mode to the second-order storage unit mode, and the digital logic 1 (for example, 0xFF) is written to the most significant bit controlled by the first bit line to be corrected in the single-order storage unit. The voltage distribution of the page corresponding to a bit line. In other words, the controller 160 switches the operation mode from the single-stage storage unit mode to the second-order storage unit mode, and moves the information states of the voltage distributions 00 and 01 to 11 and 10, respectively, to correct in the single-stage storage unit, first The voltage distribution of the page corresponding to the bit line.

In another embodiment of the present invention, the controller 160 switches the operation mode from the single-order storage unit mode to the third-order storage unit mode, and writes the digital logic 1 (for example, 0xFF) to be controlled by a first bit line. The most significant bit and the central significant bit to correct the voltage distribution of the page corresponding to the first bit line in the single-order memory cell. In other words, the controller 160 switches the operation mode from the single-stage storage unit mode to the third-order storage unit mode, and moves the information states of 000, 001, 010, 011, 100, and 101 in the voltage distribution to 111 and 110, respectively, to correct In a single-stage memory cell, the voltage distribution of the page corresponding to the first bit line.

In addition, the repeated reading program disclosed in the present invention is for resetting the reading voltage of the target page that has an error during the reading process according to a read retry table to repeatedly read the target page. (Read Retry). It should be noted that the target page described above is a read command sent by the host 120 to the data storage device 140, which is required to be read. The detailed actions are as follows.

In an embodiment of the present invention, the controller 160 is configured to read commands from the host 120 in the single-stage storage unit mode to the flash memory 180. A first reading operation is performed corresponding to one of the first character line pages. In other words, the controller 160 is configured to perform a first reading operation on the page controlled by the first word line in the flash memory 180 according to a read command of the host 120. When the first read operation reads the first page and an error occurs that cannot be repaired by the codec, the controller 160 executes the correction voltage distribution program. In the correction voltage distribution procedure, the controller 160 causes the flash memory 180 to switch to the second order storage unit mode, and in the second order storage unit mode, writes a digital logic 1 (eg, 0xFF) corresponding to the first word line. A most significant bit page to correct the voltage distribution of the memory storage unit corresponding to the first word line. Then, the controller 160 is further configured to cause the flash memory 180 to return to the single-order storage unit mode after the digital logic 1 (eg, 0xFF) is written to the most significant bit page corresponding to the first word line, and In the stage storage unit mode, a second reading operation is performed on the page corresponding to the first word line. When the controller 160 successfully reads the page corresponding to the first word line in the second reading action (ie, the data is error-free or the error can be corrected), the controller 160 will successfully read the corresponding character corresponding to the first character. The data of the page of the line is transmitted to the host 120. When the controller 160 still fails to read the page corresponding to the first word line in the second reading action (ie, the data still cannot be corrected), the controller 160 marks the page corresponding to the first word line as A damaged page, or the block corresponding to the first character line is marked as a damaged block.

In a correction voltage distribution routine of another embodiment of the present invention, the controller 160 causes the flash memory 180 to switch to the third-order storage unit mode, and in the third-order storage unit mode, a digit logic 1 (for example, 0xFF) A page corresponding to one of the first word line and the most significant bit page is written to correct the voltage distribution of the memory storage unit corresponding to the first word line. Then, the controller 160 is further configured to cause the flash memory 180 to return to the single-order storage after the digital logic 1 (eg, 0xFF) is written to the most significant bit page corresponding to the first word line and the central effective bit page. In the unit mode, and in the single-stage storage unit mode, a second reading operation is performed on the page corresponding to the first word line. Similarly, when the controller 160 successfully reads the page corresponding to the first word line in the second reading action (ie, the data is error-free or the error can be corrected), the controller 160 will successfully read the corresponding page. The data of the page of the word line is transmitted to the host 120. When the controller 160 still fails to read the page corresponding to the first word line in the second reading action (ie, the data still cannot be corrected), the controller 160 marks the page corresponding to the first word line as A damaged page, or the block corresponding to the first character line is marked as a damaged block.

In another embodiment of the present invention, when the first read operation reads an error corresponding to the page of the first word line and cannot be repaired by the codec, the controller 160 is further configured to correct the voltage distribution. Perform a repeat reading procedure before the program. In the repeated reading process, the controller 160 is configured to perform a voltage setting action on one of the registers in the flash memory 180 according to a repeated reading table to use the value in the register as a flash memory. The reading voltage of the body 180. Then, the controller 160 is further configured to perform a second reading operation on the page corresponding to the first word line by the read voltage of the set flash memory 180, and add one repeated reading count. .

When the controller 160 successfully reads the page corresponding to the first word line in the second read operation, the controller 160 transmits the data of the page corresponding to the first word line successfully read to the host 120. The second reading operation performed by the controller 160 after repeatedly reading the program still cannot be successfully read corresponding to After the page of the first word line, the repeated reading process is repeated until the data of the first page can be successfully read, or until the number of times the repeated reading program is repeatedly executed reaches a first predetermined value. When the number of times the repeated reading program is repeatedly executed reaches the first predetermined value, the controller 160 is configured to execute the corrected voltage distribution program. For example, the first predetermined value may be 1 time, 5 times, 10 times, 20 times, 50 times, 100 times, or 500 times, etc., and the experimental data of the success rate after the inventor rereads the target page according to the voltage setting program The numerical values of the design, the invention is not limited thereto.

Figure 5 is a flow chart of an error correction method of an embodiment of the present invention. The error correction method is applied to the data storage device 140 shown in FIG. The flow begins in step S500.

In step S500, the controller 160 is configured to perform a first reading on the page corresponding to one of the first character lines in the flash memory 180 according to the read command of the host 120 in the single-stage storage unit mode. Take action. In other words, the controller 160 is configured to perform a reading operation on the first page of the flash memory 180 controlled by the first word line according to a read command of the host 120.

Next, in step S502, the controller 160 determines whether an error that cannot be repaired by the codec occurs when the page corresponding to the first word line is read. When there is no error that cannot be repaired by the codec, the flow proceeds to step S504. Otherwise, the flow proceeds to step S506.

In step S504, the controller 160 transmits the data of the page of the first character line successfully read to the host 120. The flow ends in step S504.

In step S506, the controller 160 causes the flash memory 180 to switch to the second-order storage unit mode.

Next, in step S508, the controller 160 is in the second-order storage unit. In the mode, a digital logic 1 (eg, 0xFF) is written to the most significant bit page corresponding to one of the first word lines to correct the voltage distribution of the memory storage unit corresponding to the first word line.

Next, in step S510, the controller 160 causes the flash memory 180 to revert to the single-stage storage unit mode.

Next, in step S512, the controller 160 performs a second reading operation on the page corresponding to the first word line in the single-order storage unit mode.

Next, in step S514, the controller 160 determines whether an error that cannot be repaired by the codec occurs when the second reading operation reads the page corresponding to the first word line. When there is no error that cannot be repaired by the codec, the flow proceeds to step S504. Otherwise, the flow proceeds to step S516.

In step S516, the controller 160 marks the page corresponding to the first word line as a damaged page or marks the block corresponding to the first word line as a damaged block. The flow ends in step S516.

6A-6B is a flow chart of an error correction method of an embodiment of the present invention. The error correction method is applied to the data storage device 140 shown in FIG. The flow begins in step S600. It should be noted that steps S600-S604 are similar to steps S500-S504. For detailed description, please refer to the process of FIG. 5, and details are not described herein.

In step S606, the controller 160 determines whether a repeated read count corresponding to the number of voltage setting actions exceeds a first predetermined value. For example, the controller 160 can use one of the memory blocks or a temporary memory implemented in the flash memory 180 or other memory to repeatedly execute the repeated reading program. The number of rows is counted for a repeat read. When the repeated read count exceeds the first predetermined value, the flow proceeds to step S614. Otherwise, the flow proceeds to step S608.

In step S608, the controller 160 is configured to perform a voltage setting operation on one of the registers (not shown) in the flash memory 180 according to the repeated reading table, so as to compare the value in the temporary register. The read voltage of the flash memory 180. For example, the repeated read list can be stored in the permanent memory 164.

Next, in step S610, the controller 160 is configured to perform a second reading operation on the page corresponding to the first word line by the read voltage of the set flash memory 180.

Next, in step S612, the controller 160 increments the repeated read count by one. For example, the controller 160 increments the value in the memory block or a register for performing repeated read counts. Next, the flow returns to step S602.

In step S614, the controller 160 causes the data storage device 140 to switch to the second-order storage unit mode.

Next, in step S616, the controller 160 writes a digit logic 1 (for example, 0xFF) to the most significant bit page corresponding to one of the first word lines in the second-order storage unit mode to correct the corresponding word. The voltage distribution of the memory storage unit of the line.

Next, in step S618, the controller 160 causes the flash memory 180 to revert to the single-order storage unit mode.

Next, in step S620, the controller 160 performs a second reading operation on the page corresponding to the first word line in the single-order storage unit mode.

Next, in step S622, the controller 160 determines whether an error that cannot be repaired by the codec occurs when the second reading operation reads the page corresponding to the first word line. When there is no error that cannot be repaired by the codec, the flow proceeds to step S604. Otherwise, the flow proceeds to step S624.

In step S624, the controller 160 marks the page corresponding to the first word line as a damaged page or marks the block corresponding to the first word line as a damaged block. The flow ends in step S624.

Figure 7 is a flow chart of an error correction method of an embodiment of the present invention. The error correction method is applied to the data storage device 140 shown in FIG. The flow begins in step S700. It should be noted that steps S700-S704 and S710-S716 are similar to steps S500-S504 and S510-S516. For details, please refer to the process of FIG. 5, and details are not described herein.

In step S706, the controller 160 causes the data storage device 140 to switch to the third-order storage unit mode.

Next, in step S708, the controller 160 writes a digit logic 1 (for example, 0xFF) to the most significant bit page corresponding to one of the first word lines and an intermediate significant bit in the third-order storage unit mode. a page to correct the voltage distribution of the memory storage unit corresponding to the first word line.

8A-8B are flowcharts of an error correction method of an embodiment of the present invention. The error correction method is applied to the data storage device 140 shown in FIG. The flow begins in step S800. It should be noted that steps S800-S812 and S818-S824 are similar to steps S600-S612 and S618-S624. For detailed description, please refer to the process of FIG. 5, and details are not described herein.

In step S814, the controller 160 causes the flash memory 180 to be cut. Change to the third-order storage unit mode.

Next, in step S816, the controller 160 writes a digital logic 1 (for example, 0xFF) to the most significant bit page corresponding to one of the first word lines and an intermediate effective bit in the third-order storage unit mode. a page to correct the voltage distribution of the memory storage unit corresponding to the first word line.

Figure 9 is a flow chart showing a method of reading data according to an embodiment of the present invention. The data reading method is applied to the data storage device 140 shown in FIG. The flow begins in step S900.

In step S900, the controller 160 is configured to perform a first time on the page corresponding to one of the first character lines in the flash memory 180 according to the read command of the host 120 in the single-stage storage unit mode. Read the action to get a first data. In other words, the controller 160 is configured to perform a reading operation on the first page of the flash memory 180 controlled by the first word line according to a read command of the host 120.

Then, the first data read may have two situations, including an error that the first data cannot be repaired, and the first data has no error or the error can be corrected, wherein when the first data has no error or the error can be corrected, the controller The first data is transmitted to the host 120. In addition, the case shown in step S902 is another case. In step S902, when an error occurs in the first data that cannot be repaired, the controller 160 causes the flash memory 180 to switch to the multi-level storage unit mode.

Next, in step S904, the controller 160 writes a preset data to the most significant bit page corresponding to one of the first word lines in the multi-level storage unit mode. In an embodiment, the preset material is 0Xff, but the invention is not limited thereto.

Next, in step S906, the controller 160 causes the flash memory to be 180 switches to single-stage storage unit mode.

Next, in step S908, the controller 160 reads the page of the first word line again in the single-stage storage unit mode to obtain a second data.

Then, the second data read may have two situations, including an error that the second data cannot be repaired, and the second data has no errors or errors can be corrected. In step S910, when the second data has no error or the error can be corrected, the controller 160 transmits the second data to the host 120; when the second data fails to be repaired, the controller 160 will correspond to the first character. The page of the line is marked as a damaged page or the first block corresponding to the first word line is marked as a damaged block. The flow ends in step S910.

Figure 10 is a flow chart showing a method of reading data according to another embodiment of the present invention. The data reading method is applied to the data storage device 140 shown in FIG. The flow begins in step S1000.

In step S1000, the controller 160 performs a first reading operation of the single-order storage unit mode on the page corresponding to one of the first character lines in the flash memory 180 according to a read command of a host 120. Get a first data.

Then, the first data read may have two situations, including an error that the first data cannot be repaired, and the first data has no error or the error can be corrected, wherein when the first data has no error or the error can be corrected, the controller The first data is transmitted to the host 120. In addition, the case shown in step S1002 is another case. In step S1002, when the first data fails to be repaired, a preset data is written in the multi-level storage unit mode to the most significant bit page corresponding to one of the first character lines. In an embodiment, the preset material is 0Xff, but the invention is not limited thereto.

Next, in step S1004, the controller 160 reads the page of the first word line in the single-order storage unit mode to obtain a second material.

Next, in step S1006, when the second data has no errors or the error can be corrected, the controller 160 transmits the second data to the host 120; when the second data fails to be repaired, the controller 160 corresponds to the first The page of the word line is marked as a damaged page or the first block corresponding to the first word line is marked as a damaged block. The flow ends in step S1006.

Fig. 11 is a simulation diagram of the error rate before the target page is not read by the error correction method disclosed in the present invention. In the simulation diagram, the curve 1102 is the number of error bits before the page is read by the error correction method of the present invention, and the curve 1104 is the number of error bits after the page is read only by repeating the program. As can be seen from Figure 11, the repeated reading process can only reduce the limited error rate, but it still cannot reduce the number of error bits of the page to a readable level.

Fig. 12 is a simulation diagram of the error rate after the target page is read by the error correction method disclosed in the present invention. In the simulation diagram, the curve 1202 is the number of error bits after the page is corrected only by the correction voltage distribution program, and the curve 1204 is the number of error bits after the page is read through the repeated reading program and the correction voltage distribution program. As can be seen from Fig. 12, the correction voltage distribution program can greatly reduce the error rate of the page. In addition, after performing the correction voltage distribution program and repeating the reading process, the error rate of the page can be further reduced.

It can be seen from the above that the data storage device 140 and the error correction method provided by the present invention can correct the voltage distribution of the target page in a non-single-order storage unit mode by correcting the voltage distribution program. In addition, the repeat reader can read the target page repeatedly (Read Retry) to read according to different read voltages. Information on the target page.

The method of the invention, or a particular type or portion thereof, may exist in the form of a code. The code can be stored in a physical medium such as a floppy disk, a CD, a hard disk, or any other machine readable (such as computer readable) storage medium, or is not limited to an external form of computer program product, wherein When the code is loaded and executed by a machine, such as a computer, the machine becomes a device for participating in the present invention. The code can also be transmitted via some transmission medium, such as a wire or cable, fiber optics, or any transmission type, where the machine becomes part of the program when it is received, loaded, and executed by a machine, such as a computer. Invented device. When implemented in a general purpose processing unit, the code combination processing unit provides a unique means of operation similar to application specific logic.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

100‧‧‧Electronic system

120‧‧‧Host

140‧‧‧Data storage device

160‧‧‧ Controller

162‧‧‧ arithmetic unit

164‧‧‧Permanent memory

180‧‧‧Flash memory

Claims (28)

A data storage device includes: a flash memory for operating in a single-stage storage unit mode and a non-single-order storage unit mode; and a controller for operating in the single-stage storage unit mode The one read command of the host performs a first read operation on the page corresponding to one of the first character lines in the flash memory, and when the first read operation reads the first word When the above-mentioned page of the meta-line fails to be repaired by the codec, a correction voltage distribution program is executed, wherein in the correction voltage distribution program, the controller causes the flash memory to switch to the non-single-order Storing the unit mode, and in the non-single-order storage unit mode, writing a first digit logic 1 to the most significant bit page corresponding to one of the first word lines to correct corresponding to the first word line The voltage distribution of the memory storage unit. According to the data storage device of claim 1, wherein the non-single-order storage unit mode is a second-order storage unit mode. The data storage device of claim 2, wherein the controller is further configured to: after the first digital logic 1 writes the most significant bit page in the calibration voltage distribution program, causing the flash memory to be Reverting to the single-stage storage unit mode, and in the single-stage storage unit mode, performing a second reading operation on the page corresponding to the first word line. The data storage device of claim 3, wherein the controller is further configured to read the first character line when the second reading operation is performed When the above page fails to be repaired by the codec, the page corresponding to the first word line is marked as a damaged page. The data storage device of claim 1, wherein the non-single-order storage unit mode is a third-order storage unit mode. The data storage device of claim 5, wherein the controller is further configured to write a second digit logic 1 corresponding to the first in the third-order storage unit mode in the calibration voltage distribution program A central effective bit page of one of the word lines to correct the voltage distribution of the memory storage unit corresponding to the first word line. The data storage device of claim 6, wherein the controller is further configured to: after the second digit logic 1 writes the most significant bit page and the central valid bit page in the calibration voltage distribution program And causing the flash memory to return to the single-stage storage unit mode, and performing a second reading operation on the page corresponding to the first word line in the single-stage storage unit mode. According to the data storage device of claim 7, wherein the controller is further configured to: when the second reading operation reads the page corresponding to the first character line, an error cannot be repaired by the codec. When the page corresponding to the first word line is marked as a damaged page. According to the data storage device of claim 1, wherein the controller is further configured to detect an error that cannot be repaired by codec when the first read operation reads the page corresponding to the first word line And a repeating reading program is executed before the correcting voltage distribution program, wherein in the repeating reading program, the controller is configured to read the table according to a repeat One of the flash memories performs a voltage setting operation to set the value in the register as the read voltage of the flash memory. The data storage device of claim 5, wherein the controller is further configured to, in the repeat reading process, set the read voltage pair of the flash memory to correspond to the first word line The above page performs a second read operation and increments a repeated read count by one. The data storage device of claim 10, wherein in the repeating reading process, the controller is further configured to determine whether the repeated reading count exceeds a first predetermined value, and when the repeated reading count exceeds the above When the first predetermined value is used, the above-described corrected voltage distribution program is performed. An error correction method is applicable to a data storage device, wherein the data storage device comprises a flash memory for operating in a single-order storage unit mode and a non-single-order storage unit mode, wherein the error correction method comprises: In the single-stage storage unit mode, performing a first reading operation on a page corresponding to a first character line in the flash memory according to a read command of a host; determining the first reading action When the first page is read, whether an error cannot be repaired by the codec occurs; and when the first read operation reads the page corresponding to the first word line, the page cannot be repaired by the codec. In the case of an error, a calibration voltage distribution program is executed, wherein the correction voltage distribution program includes: causing the flash memory to switch to the non-single-order storage unit mode; In the non-single-order memory cell mode, writing a first digit logic 1 to a most significant bit page corresponding to one of the first word lines to correct a memory storage unit corresponding to the first word line Voltage distribution. According to the error correction method of claim 12, wherein the non-single-order storage unit mode is a second-order storage unit mode. According to the error correction method of claim 13, wherein the step of correcting the voltage distribution program further comprises: after the first digital logic 1 writes the most significant bit page, causing the flash memory to return to the single a storage unit mode; and in the single-stage storage unit mode, performing a second reading operation on the page corresponding to the first word line. According to the error correction method of claim 14, wherein the step of correcting the voltage distribution program further comprises: when the second reading operation reads the page corresponding to the first word line, the encoding cannot be performed by codec When the error is fixed, the above page corresponding to the first word line is marked as a damaged page. According to the error correction method of claim 12, wherein the non-single-order storage unit mode is a third-order storage unit mode. According to the error correction method of claim 16, wherein the step of correcting the voltage distribution program further comprises writing a second digit logic 1 to one of the first word lines in the third-order storage unit mode. The central effective bit page is for correcting the voltage distribution of the memory storage unit corresponding to the first word line. According to the error correction method of claim 17 of the scope of patent application, wherein the above correction The step of the voltage distribution program further includes: after the second digit logic 1 writes the most significant bit page and the central effective bit page, causing the flash memory to return to the single-stage storage unit mode; In the single-stage storage unit mode, a second reading operation is performed on the page corresponding to the first word line. According to the error correction method of claim 18, wherein the step of correcting the voltage distribution program further comprises: when the second reading operation reads the page corresponding to the first word line, the codec cannot be performed by codec When the error is fixed, the above page corresponding to the first word line is marked as a damaged page. According to the error correction method of claim 12, the method further includes: when the first reading operation reads an error corresponding to the page of the first character line and cannot be repaired by codec, Performing a repeated reading process before the voltage distribution program, wherein the repeating reading program includes performing a voltage setting action on one of the flash memory in the flash memory according to a repeated reading table to be used in the temporary register The value is used as the read voltage of the above flash memory. According to the error correction method of claim 20, wherein the step of repeating the reading process further comprises: performing, by setting the read voltage of the flash memory, a page corresponding to the first word line; The second read action, and a repeat read count is incremented by one. According to the error correction method of claim 21, wherein the step of repeatedly reading the program further comprises: Determining whether the repeated read count exceeds a first predetermined value; and when the repeated read count exceeds the first predetermined value, performing the corrected voltage distribution procedure. A data reading method is applicable to a data storage device, wherein the data storage device comprises a flash memory for operating in a single-stage storage unit mode and a multi-level storage unit mode, wherein the data reading method comprises: In the single-stage storage unit mode, a first reading operation is performed on a page corresponding to a first character line in the flash memory according to a read command of a host to obtain a first data; When the first data fails to be repaired, the flash memory is switched to the multi-level storage unit mode; and in the multi-level storage unit mode, a preset data is written corresponding to the first character. One of the most significant bit pages of the line; causing the flash memory to switch to the single-stage memory cell mode; and reading the page of the first word line again to obtain a second data. According to the data reading method of claim 23, wherein the preset data is 0xFF. According to the data reading method of claim 23, the method further includes: transmitting the second data to the host when the second data is error-free or the error can be corrected. According to the data reading method of claim 23, the method further includes: when the second data fails to be repaired, marking the page corresponding to the first character line as a damaged page. According to the data reading method of the 23rd patent application scope, the method further includes: When the second data fails to be repaired, the first block corresponding to the first character line is marked as a damaged block. A data reading method is applicable to a data storage device, wherein the data storage device comprises a flash memory for operating in a single-stage storage unit mode and a multi-level storage unit mode, wherein the data reading method comprises: a host read command performs a first read operation of the single-stage storage unit mode on a page corresponding to a first word line in the flash memory to obtain a first data; When an error occurs that cannot be repaired, a predetermined data is written into the most significant bit page corresponding to one of the first word lines in the multi-level storage unit mode; and the above-mentioned first-order storage unit mode is read. The above page of the word line is used to obtain a second data; and when the second data has no error or the error can be corrected, the second data is transmitted to the host.