TWI525624B - Memory and operating method thereof - Google Patents

Description

Memory and its operation method

The present invention relates to the field of data storage technology, and more particularly to a memory and method of operation thereof.

A non-volatile memory is a type of memory that retains stored data even when it is not powered by an external power source. Since the memory itself does not need to waste power on the memory of the data, it is particularly suitable for use on a portable device.

Non-volatile memory has three modes of operation: read, write, and erase. Among them, the write operation is a so-called program operation. In general, non-volatile memory requires different voltages to perform these three operations. Since the non-volatile memory requires more and more stringent precision for the stylized voltages required to perform the stylized operation, the required stylized voltage must be very precise and cannot be greatly changed.

The present invention provides a memory that stabilizes the stylized voltage by stabilizing the magnitude of the load.

The present invention further provides a method of operating a memory suitable for use in the aforementioned memory.

The invention provides a memory comprising a decoder, a memory array, a plurality of loads, a load detection circuit and a load control circuit. The decoder includes an input terminal and a plurality of output terminals, and the input terminal is configured to receive a power supply voltage. The memory array includes a plurality of source lines and a plurality of memory cells, each source line electrically coupled to one of the output ends of the decoder, and electrically coupled to the N memory cells of the memory cells . Each of the loads is equal in size to the load corresponding to each memory unit. The load detection circuit is configured to obtain one N-bit input data of the memory, and determine how many memory unit contents need to be changed when the memory performs a stylized operation according to the N-bit input data. And according to the results of the first judgment. The load control circuit is configured to receive the first determination result, and when the first determination result indicates that the storage content of the M memory units needs to be changed, the load control circuit provides the NM load according to the first determination result. The decoder is further provided to further connect the supplied NM loads to a transmission path of the above-mentioned power supply voltage, wherein N and M are both natural numbers.

The invention further proposes a method of operating a memory. The memory includes a decoder and a memory array. The decoder includes an input end and a plurality of output ends, and the input end is configured to receive a power supply voltage. The memory array includes a plurality of source lines and a plurality of memory cells, each of the source lines being electrically coupled to one of the output ends of the decoder, and electrically coupling the N memories in the memory units unit. The operation method includes the following steps: obtaining N-bit input data of one of the memory, and determining how many memory unit contents need to be changed when the memory performs a stylized operation according to the N-bit input data. And generating a first judgment result; and when the first judgment result indicates that the storage contents of the total M memory units need to be changed, providing NM loads to the decoder according to the first determination result, to further provide the provided NM The load is connected in parallel to a transmission path of the above power supply voltage, wherein N and M are both natural numbers.

In the invention, a plurality of loads, a load detecting circuit and a load control circuit are added in the memory, and the size of each load is equal to the load corresponding to each memory unit. In addition, the present invention also utilizes the load detection circuit to obtain one N-bit input data of the memory, and determines how many memory cells need to be changed when the memory performs a stylized operation according to the N-bit input data. Content, and according to the results of the first judgment. When the first judgment result indicates that the storage contents of the M memory cells need to be changed, the load control circuit provides the NM load to the decoder of the source line according to the first determination result to further connect the supplied NM loads in parallel. To a transmission path of the above power supply voltage. Therefore, when the decoder uses the received power voltage as a stylized voltage to perform the above-mentioned stylization operation, the load of the load required to drive the voltage can be maintained at the load corresponding to the N memory cells. The size of the program allows the stylized voltage to remain stable.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 is a schematic diagram of a memory structure according to an embodiment of the present invention, which only shows a circuit architecture related to the present invention in a memory, and takes a circuit architecture inside a flash memory as an example. Referring to FIG. 1, the memory 100 includes a data input/output interface 110, a load detection circuit 120, a load control circuit 130, a plurality of loads (as indicated by a reference numeral 140), a power supply voltage generating circuit 150, and a power voltage switch. 160. Decoder 170 and memory array 180. Said The decoder 170 includes an input 171 and a plurality of outputs (as indicated by the numerals 172-1 to 172-N). The memory array 180 includes a plurality of source lines (as indicated by the numeral 181) and a plurality of memory cells (as indicated by the numeral 182), and each of the source lines 181 is electrically coupled to the decoder 180. An output terminal is electrically coupled to the N memory cells 182 of the memory cells 182, where N is a natural number. As can be seen from the above description, the decoder 170 is a source line decoder.

The power supply voltage switching switch 160 is electrically coupled between the output end of the power supply voltage generating circuit 150 and the input end 171 of the decoder 170, and is configured to receive the power supply voltage PV1 generated by the power supply voltage generating circuit 150 and a predetermined voltage PV2. The output power voltage PV1 or the preset voltage PV2 is selected to the input terminal 171 of the decoder 170 according to the control command CM. In this example, the supply voltage generating circuit 150 can be implemented using a low dropout regulator. In addition, the above-mentioned power supply voltage PV1 is used as a stylized voltage, and the preset voltage PV2 is used, for example, as a read voltage.

Each of the loads 140 has a size equal to the load corresponding to each memory unit 182. In this example, each load 140 is implemented as a redundant memory unit. The redundant memory unit referred to herein means that its internal circuit architecture is the same as the internal circuit architecture of the memory unit 182. This means that each memory cell 182 and each redundant memory cell in the memory 100 includes a floating-gate transistor (shown as reference numeral 141). In this example, one of the source/drain electrodes of each of the redundant memory cells is electrically coupled to the input terminal 171 of the decoder 170, and each of the redundant memory cells The other source/drain of the floating gate transistor 141 is electrically coupled to a reference potential, such as a ground potential GND.

The load detecting circuit 120 is configured to obtain one N-bit input data of the memory 100, and determine that the memory 100 is executed according to the N-bit input data. In a stylized operation, it is necessary to change the storage contents of the memory unit 182, and accordingly generate the first determination result DS1. The load control circuit 130 is electrically coupled to the gate of each of the floating memory transistors 141, and is configured to determine the redundant memory cells according to the first determination result DS1. The on state of the floating gate transistor 141. When the first determination result DS1 indicates that the storage contents of the M memory units 182 need to be changed, the load control circuit 130 turns on the NM floating gate transistors 141 according to the first determination result DS1, that is, provides NM loads 140 for decoding. The device 180 further parallels the supplied NM loads 140 to a transmission path (described later) of the power supply voltage PV1, where M is also a natural number. As can be seen from the above description, the more the number of memory cells 182 that need to change the stored content, the less the load 140 needs to be connected in parallel; the fewer the number of memory cells 182 that need to change the stored content, the more loads 140 need to be connected in parallel. In addition, the sum of the number of memory cells 182 that need to change the stored content and the number of loads 140 that need to be connected in parallel is always N.

An actual operation of one of the memories 100 will be exemplified below, and N is assumed to be equal to 8. Referring to FIG. 1 again, after the load detection circuit 120 obtains an 8-bit input data of the memory 100, the load detection circuit 120 determines that the memory 100 performs a program operation based on the 8-bit input data. At this time, it is necessary to change the storage contents of the memory unit 182, and accordingly, the first judgment result DS1 is generated. If the first determination result DS1 indicates that the storage contents of the six memory units 182 need to be changed, the load control circuit 130 turns on the two floating gate transistors 141 of the redundant memory units according to the first determination result DS1. That is, two loads 140 are provided to the decoder 180 to further parallel the two supplied loads 140 to a transmission path of the power supply voltage PV1.

Taking the case shown in the figure as an example, the memory 100 is eight memories electrically coupled to the output terminal 172-1 of the decoder 170 according to the 8-bit input data described above. The unit 182 performs the above-mentioned stylization operation. Therefore, when the memory 100 performs the above-mentioned stylized operation, the decoder 170 forms an electrical path 173 therein to input the input terminal 171 and the output terminal 172-1. Electrically coupled to each other. At this time, the electrical path between the power supply voltage switch 160 and the input terminal 171, the input end 171, the electrical path 173, the output end 172-1 and the output end 172-1 are electrically coupled to the source line. 181 will form the transmission path of the power supply voltage PV1. Therefore, when the memory 100 performs the above-described stylized operation, the two loads 140 provided by the load control circuit 130 are connected in parallel on this transmission path.

The advantage of the above method is that when the decoder 170 uses the received power voltage PV1 as a stylized voltage to perform the above stylized operation, the load required to drive the programmed voltage can be maintained. The size of the load corresponding to the N memory cells 182, in turn, enables the stylized voltage to remain stable.

Further, in order to check whether the result of the above stylization operation is correct, the load detection circuit 130 can further determine the data of how many bits of the N-bit output data of the memory 100 relative to the N-bit input data. Differently, the N-bit output data is an N-bit storage data stored in the plurality of memory cells 182 of the memory 100 that have been subjected to the procedural operation according to the N-bit input data. In this way, the load detection circuit 130 can generate the second determination result DS2, and output the second determination result DS2 to the load control circuit 130, so that the load control circuit 130 determines whether to provide the load 140 according to the second determination result DS2. Decoder 170. The number of loads 140 to be provided is not limited as long as the load required to drive the programmed voltage can be maintained at the size of the load corresponding to the N memory cells 182. Of course, the above verification operation can be repeated until the N-bit input data coincides with the N-bit output data.

In addition, in order to obtain the N-bit input data and the N-bit output data, the load detection circuit 130 is further electrically coupled to the data input/output interface 110 to receive the N-bit transmitted by the data input/output interface 110. Meta input data and N bit output data. The data input/output interface 110 is also used to latch the N-bit input data. In this example, the data input/output interface 110 further includes an input data transmission unit 112 and an output data transmission unit 114, wherein the input data transmission unit 112 is configured to transmit and latch the N-bit input data, and output data transmission. The unit 114 is configured to transmit the N-bit output data described above.

2 is a schematic diagram of a memory according to another embodiment of the present invention, which only shows the circuit architecture related to the present invention in the memory, and also takes the circuit architecture inside the flash memory as an example. In FIG. 2, the same reference numerals as those in FIG. 1 are indicated as the same object or signal. Referring to FIG. 2, the memory 200 differs from the memory 100 of FIG. 1 mainly in the electrical coupling manner of the floating gate transistors 141 in each redundant memory unit. In addition, the memory 200 also employs a load control circuit 230 to control the floating gate transistors 141 and adds a word line 242.

As shown in FIG. 2, the gate terminals of each of the redundant memory cells 141 are electrically coupled to the same word line 242, and each of the redundant memory cells is electrically One of the source/drain electrodes of the crystal 141 is electrically coupled to the input terminal 171 of the decoder 170. Additionally, load control circuit 230 includes a control unit 231 and a plurality of switches (as indicated by reference numeral 232). Each switch 232 is electrically coupled between one of the redundant memory cells and another source/drain of the floating gate 141 and the ground potential GND, and the control unit 231 is electrically coupled to each of the switches 231. The control terminal of the switch 232 is configured to determine whether to turn on at least one switch 232 according to the first determination result DS1 or the second determination result DS2. In this example, each switch 232 can be implemented by using an NMOS transistor, but the invention is not limited thereto.

FIG. 3 is a schematic diagram of a memory structure according to still another embodiment of the present invention, which only shows the circuit architecture related to the present invention in the memory, and also takes the circuit architecture inside the flash memory as an example. In FIG. 3, the same reference numerals as those in FIG. 2 are indicated as the same object or signal. Referring to FIG. 3, the difference between the memory 300 and the memory 200 of FIG. 2 is mainly that each load 340 used in the memory 300 is implemented by using a resistor.

4 is a schematic diagram of a memory according to still another embodiment of the present invention, which only shows the circuit architecture related to the present invention in the memory, and also takes the circuit architecture inside the flash memory as an example. In FIG. 4, the same reference numerals as those in FIG. 1 are indicated as the same object or signal. Referring to FIG. 4, the memory 400 differs from the memory 100 of FIG. 1 mainly in the electrical coupling manner of the floating gate transistors 141 in each redundant memory unit. In addition, the memory 400 also uses the decoder 470 to electrically couple the source line 181 in the memory array 180 and add a source line 483. The decoder 470 includes an input 471 and a plurality of outputs (as indicated by the symbols 472-1~472-N and N+1). When the memory 400 is performing a program operation, the decoder 470 electrically couples the two outputs to each other. One of the two outputs is the output terminal N+1, and the other output terminal is electrically coupled to the memory unit 182 to be programmed by the source line 181 of the memory array 180.

Taking the case shown in this figure as an example, when the memory 400 performs a stylization operation, the decoder 470 forms an electrical path 474 therein to input its input terminal 471, output terminal 472-1, and output. The terminals N+1 are electrically coupled to each other. At this time, the electrical path between the power supply voltage switch 160 and the input terminal 471, the input terminal 471, the electrical path 474, the output terminal 472-1, and the output terminal 472-1 are electrically coupled to the source line. 181. The output terminal N+1 and the source line 483 form a transmission path of the power supply voltage PV1. Therefore, when the memory 400 performs the above stylized operation, negative The load 140 provided by the load control circuit 130 is connected in parallel to this transmission path.

FIG. 5 is a schematic diagram of a memory according to still another embodiment of the present invention, which only shows the circuit architecture related to the present invention in the memory, and also takes the circuit architecture inside the flash memory as an example. In FIG. 5, the same reference numerals as those in FIG. 4 are denoted as the same object or signal. Referring to FIG. 5, the memory 500 differs from the memory 400 of FIG. 4 mainly in the manner of electrically coupling the floating gate transistors 141 in the redundant memory cells. In addition, the memory 500 also uses the aforementioned load control circuit 230 to control the floating gate transistors 141 and adds a word line 242.

As shown in FIG. 5, the gate terminals of each of the redundant memory cells 141 are electrically coupled to the same word line 242, and each of the redundant memory cells is electrically One of the sources/drains of the crystal 141 is electrically coupled to the input terminal N+1 of the decoder 470. In addition, each switch 232 in the load control circuit 230 is electrically coupled between one of the redundant memory cells and another source/drain of the floating gate 141 and the common potential. The potential is, for example, a ground potential GND.

FIG. 6 is a schematic diagram of a memory according to still another embodiment of the present invention, which only shows the circuit architecture related to the present invention in the memory, and also takes the circuit architecture inside the flash memory as an example. In Fig. 6, the same reference numerals as those in Fig. 5 are indicated as the same object or signal. Referring to FIG. 6, the difference between the memory 600 and the memory 500 of FIG. 5 is mainly that each load 340 used in the memory 600 is implemented by using a resistor.

Although the above embodiments are all based on the circuit architecture inside the flash memory, it is not intended to limit the present invention. Those skilled in the art should be aware that any of the foregoing embodiments can be extended to other types. Memory.

According to the teachings of the above embodiments, those skilled in the art are entitled to return A method of operating a memory is presented. The memory includes a decoder and a memory array. The decoder includes an input and a plurality of outputs for receiving a supply voltage. The memory array includes a plurality of source lines and a plurality of memory units. Each of the source lines is electrically coupled to one of the outputs of the decoder and electrically coupled to the N of the memory units. FIG. 7 is a flow chart showing a method of operating a memory according to an embodiment of the invention. Referring to FIG. 7, the steps of the operation method include: acquiring one N-bit input data of the memory, and determining how many memory cells need to be changed when the memory performs a stylization operation according to the N-bit input data. And storing the content, and generating a judgment result (as shown in step S702); and when the judgment result indicates that the storage contents of the M memory units need to be changed, the NM load is provided to the decoder according to the judgment result, To further parallel the supplied NM loads to a transmission path of the power supply voltage, wherein N and M are both natural numbers (as shown in step S704).

In summary, the present invention adds a plurality of loads, a load detection circuit and a load control circuit to the memory, and the size of each load is equal to the load corresponding to each memory unit. In addition, the present invention also utilizes the load detection circuit to obtain one N-bit input data of the memory, and determines how many memory cells need to be changed when the memory performs a stylized operation according to the N-bit input data. Content, and according to the results of the first judgment. When the first judgment result indicates that the storage contents of the M memory cells need to be changed, the load control circuit provides the NM load to the decoder of the source line according to the first determination result to further connect the supplied NM loads in parallel. To a transmission path of the above power supply voltage. Therefore, when the decoder uses the received power voltage as a stylized voltage to perform the above-mentioned stylization operation, the load of the load required to drive the voltage can be maintained at the load corresponding to the N memory cells. The size of the program allows the stylized voltage to remain stable.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100, 200, 300, 400, 500, 600‧‧‧ memory

110‧‧‧Data input/output interface

112‧‧‧Input data transmission unit

114‧‧‧Output data transmission unit

120‧‧‧Load detection circuit

130‧‧‧Load control circuit

140, 340‧‧‧ load

141‧‧‧Floating transistor

150‧‧‧Power supply voltage generating circuit

160‧‧‧Power supply voltage switch

170, 470‧‧‧ decoder

171, 471‧‧‧ input

172-1~172-N, 472-1~472-N, N+1‧‧‧ output

173, 474‧‧‧ electrical path

180‧‧‧ memory array

181, 483‧‧‧ source line

182‧‧‧ memory unit

230‧‧‧Load control circuit

231‧‧‧Control unit

232‧‧‧Switch

242‧‧‧ character line

CM‧‧‧ control order

DS1‧‧‧ first judgment result

DS2‧‧‧ second judgment result

GND‧‧‧ Ground potential

PV1‧‧‧Power supply voltage

PV2‧‧‧Preset voltage

S702~S704‧‧‧Steps

1 is a schematic diagram of a memory in accordance with an embodiment of the present invention.

2 is a schematic diagram of a memory in accordance with another embodiment of the present invention.

3 is a schematic diagram of a memory in accordance with still another embodiment of the present invention.

4 is a schematic diagram of a memory in accordance with still another embodiment of the present invention.

FIG. 5 is a schematic diagram of a memory according to still another embodiment of the present invention.

Figure 6 is a schematic illustration of a memory in accordance with still another embodiment of the present invention.

7 is a flow chart of a method of operating a memory in accordance with an embodiment of the present invention.

S702~S704‧‧‧Steps

Claims (20)

A memory comprising: a decoder comprising an input end and a plurality of output terminals for receiving a power supply voltage; a memory array comprising a plurality of source lines and a plurality of memory units, each source The pole line is electrically coupled to one of the outputs of the decoder, and is electrically coupled to the N memory units of the memory units; the plurality of loads, each load being sized to correspond to the load of each memory unit Equal in size; a load detection circuit for obtaining N-bit input data of the memory, and determining how many memory units the memory needs to change when performing a stylized operation according to the N-bit input data And storing a content, and generating a first determination result; and a load control circuit, configured to receive the first determination result, and when the first determination result indicates that the storage content of the M memory units needs to be changed, the load The control circuit provides NM loads to the decoder according to the first determination result, so as to further connect the supplied NM loads to a transmission path of the power voltage, wherein N and M are Natural number. The memory of claim 1, wherein the load detecting circuit is further configured to determine, according to how many bits of the N-bit output data are different from the N-bit input data, to generate a second determination result, and outputting the second determination result to the load control circuit, so that the load control circuit determines whether to provide a load to the decoder according to the second determination result, wherein the N-bit output data is The memory has been processed according to the N-bit input data. An N-bit stored data stored in a plurality of memory cells of a stylized operation. The memory of claim 2, further comprising a data input/output circuit, wherein the load detecting circuit comprises: obtaining the N-bit input data and the N-bit through the data input/output circuit Meta output data. The memory of claim 1, wherein each load is implemented by a redundant memory unit, and each memory unit and each redundant memory unit includes a floating gate transistor. The gate terminals of each of the floating gates are electrically coupled to the same word line, and one of the source/drain electrodes of each of the redundant memory cells The input of the decoder is coupled. The memory device of claim 1, wherein the load control circuit includes a control unit and a plurality of switches, each of the open contacts electrically coupled to one of the redundant memory cells and the corresponding floating gate transistor. The other source/drain is electrically connected to a reference potential, and the control unit is electrically coupled to the control end of each switch, and is configured to determine whether to turn on at least one switch according to the first determination result. The memory of claim 1, wherein each load is implemented by a redundant memory unit, and each memory unit and each redundant memory unit includes a floating gate transistor. One source/drain of each of the floating gates is electrically coupled to the input of the decoder, and another of the floating gates of the redundant memory cells The source/drain is electrically coupled to a reference potential. The memory of claim 6, wherein the load control circuit is electrically coupled to the gate of each of the redundant memory cells, and is configured to be based on the first determination result. Determining whether to turn on at least one of the redundant memory cells. The memory of claim 1, wherein each load comprises a resistor, and one end of each resistor is electrically coupled to the input end of the decoder. The memory device of claim 8, wherein the load control circuit comprises a control unit and a plurality of switches, each of the open contacts electrically coupled between the other end of the one of the resistors and a reference potential, and The control unit is electrically coupled to the control end of each switch, and is configured to determine whether to turn on at least one switch according to the first determination result. The memory of claim 1, wherein the decoder further electrically connects a first output end and a second output end of the output ends when the memory operation is performed. The first output end is electrically coupled to the memory unit that needs to perform the stylizing operation through one of the source lines. The memory of claim 10, wherein each load is implemented by a redundant memory unit, and each memory unit and each redundant memory unit includes a floating gate transistor. The gate terminals of each of the floating gates are electrically coupled to the same word line, and one of the source/drain electrodes of each of the redundant memory cells The second output of the decoder is coupled. The memory device of claim 11, wherein the load control circuit includes a control unit and a plurality of switches, each of which is electrically coupled to one of the redundant memory cells and the corresponding floating gate transistor. The other source/drain is electrically connected to a reference potential, and the control unit is electrically coupled to the control end of each switch, and is configured to determine whether to turn on at least one switch according to the first determination result. The memory of claim 10, wherein each load is implemented by a redundant memory unit, and each memory unit and each redundant memory unit includes a floating gate transistor. One of the source/drain electrodes of each of the redundant memory cells is electrically coupled to the second output of the decoder, and each of the redundant memory cells The other source/drain is electrically coupled to a reference potential, and the load control circuit is electrically coupled to the gate of each of the redundant memory cells and used to determine the first The result is to decide whether to turn on at least one of the floating memory cells. The memory of claim 10, wherein each load comprises a resistor, and one end of each resistor is electrically coupled to the second output of the decoder. The memory device of claim 14, wherein the load control circuit includes a control unit and a plurality of switches, each of which is electrically coupled between the other end of one of the resistors and a reference potential, and The control unit is electrically coupled to the control end of each switch, and is configured to determine whether to turn on at least one switch according to the first determination result. A method of operating a memory, the memory comprising a decoder and a memory array, the decoder comprising an input end and a plurality of output terminals for receiving a power supply voltage, and the memory array includes a plurality of a source line and a plurality of memory units, each source line is electrically coupled to one of the output ends of the decoder, and electrically coupled to the N memory units of the memory units, the method comprising: obtaining the Inputting data to one of the N bits of the memory, and determining how many memory cells need to be changed when the memory performs a stylized operation according to the N-bit input data, and accordingly generating a first determination result; And when the first judgment result indicates that the storage contents of the M memory units need to be changed, the NM loads are provided to the decoder according to the first determination result, so as to further connect the supplied NM loads to the power source. On a transmission path of voltage, where N and M are both natural numbers. The method of operation of claim 16, wherein the size of each load is equal to the load corresponding to each memory unit. For example, the method of operation described in claim 16 further includes: a. determining that the N-bit output data of the memory is different from the number of bits of the N-bit input data, Generating a second determination result, wherein the N-bit output data is an N-bit storage data stored in a plurality of memory cells of the memory that have undergone the stylized operation according to the N-bit input data; and b And determining whether to provide a load to the decoder according to the second determination result. The method of operation of claim 18, further comprising repeatedly performing steps a and b until one of the N-bit output data of the memory matches the N-bit input data. The method of claim 16, further comprising: obtaining the N-bit input data and the N-bit output data through a data input/output circuit of the memory.