TWI520488B - Pulse latching apparatus and method for generating pulse signal of pulse latch thereof - Google Patents

Description

Method for generating pulse signal of pulse type latch device and pulse type latch

The present disclosure relates to a pulse type latching device, and more particularly to a method of generating a pulse signal of a pulse type latch.

The pulsed latching device, also known as a pulsed flip-flop, is a high speed clocked storage element. In the past, the pulse width of the pulse type latch device was not strictly required, resulting in a lack of pulse signal generator design standards for the pulse type latch device. However, in the actual state, the width of the pulse signal provided by the pulse signal generator is quite sensitive to the voltage level of the operating voltage received by the pulse latch device, and therefore, the pulse latch device is generally not capable of operating voltage. Used in systems with a wide range of dynamic voltage scaling.

In general, if the pulse width of the pulse signal generated by the pulse signal generator is designed to be too wide, the hold time of the pulse type latch device is increased to increase the hold time violation time; On the contrary, the pulse signal The pulse width of the pulse signal generated by the generator is too narrow, which increases the latch delay of the pulse latch device, that is, increases the set time violation probability, and increases the error rate ( Error rate). Designing a pulse signal with an appropriate pulse width is relatively simple for a single operating voltage, but it must be stable under a wide range of operating voltages, which may be difficult. Therefore, in the application of a pulse-type latch device for a wide range of operating voltages, how to provide a most efficient pulse signal is an important issue for designers in the field.

The present disclosure provides a pulsed latching device and a pulse signal generating method thereof for a pulse latch that can provide a pulse signal of sufficient pulse width when the pulse latching device is applied to a wide operating voltage.

The pulse latching device of the present disclosure includes a pulse latch and a pulse signal generator. The pulse latch has a data input end, a pulse signal receiving end and a data output end. The data input end of the pulse latch receives the input data, and the pulse latch latches the input data according to the pulse signal received by the pulse signal receiving end, and transmits the latched input data as the output data through the data output end. . The pulse signal generator is coupled to the pulse signal receiving end of the pulse latch. The pulse signal generator replicates the data transmission delay between the data input and the data output of the pulse latch to obtain a copy delay. The pulse signal generator receives the clock signal and processes the clock signal according to the copy delay to generate a pulse signal.

The pulse signal generating method of the pulse latch of the present disclosure, wherein the pulse The punch latch has a data input and a data output. The step of generating a pulse signal method includes copying a data transmission delay between a data input end and a data output end of the pulse latch to obtain a copy delay, and receiving a clock signal, and processing the clock signal according to the copy delay to generate Pulse signal.

Based on the above, the pulse signal generator provided by the present disclosure obtains a copy delay according to a data transmission delay caused by a circuit between the data input terminal and the data output terminal in the replica pulse latch, and the pulse signal generator obtains according to the obtained The delay is copied to match the clock signal to generate a pulse signal. In this way, regardless of the voltage level of the operating voltage applied in the pulse latch device, the pulse signal generator can provide a pulse signal with a wide and narrow pulse width to the pulse latch, so that the pulse latch can be effective. work. In other words, a pulse-type latching device operating at a low operating voltage can be implemented and effectively reduce power consumption.

The above described features and advantages of the present invention will be more apparent from the following description.

100, 400, 500, 600, 700, 800‧‧‧pulse latching devices

110, 410, 510, 610, 710, 810 ‧ ‧ pulse latch

111‧‧‧ Data transmission delay

120, 310, 320, 420, 520, 620, 720, 820‧‧‧ pulse signal generator

210, 311, 321, 421, 521, 621, 721, 821‧‧‧ delayed replication circuits

220, 312, 322, 422, 522, 622, 722, 822‧‧‧ logic operation circuit

411, 511, 611, 711, 811, 8211‧‧ ‧ feedback circuit

121‧‧‧Copy delay

dCKIN‧‧‧ delayed clock signal

DIT‧‧‧ data input

CKT‧‧‧ pulse signal receiving end

DQT‧‧‧ data output

DIN‧‧‧ input data

PULSE‧‧‧ pulse signal

Inverted signal of PULSEB‧‧‧ pulse signal

SET‧‧‧ setting signal

SETB‧‧‧Set signal inverted signal

CLR‧‧‧clear signal

CLRB‧‧‧ Clear signal inverted signal

DOUT‧‧‧Output data

CKIN‧‧‧ clock signal

IV1, IV2, IVB1, IV11~IV59, IBUF1, IBUF2, IV2I~IV5I‧‧·Inverter

AND1, AND2‧‧‧ and gate

TR11~TR43‧‧‧Transmission gate

NAND1, NAND21~NAND53‧‧‧ reverse gate

NOR21‧‧‧Anti-gate

MP1~MP3, MN1~MN3, MP51~MP56, MN51~MN56‧‧‧O crystal

VDD, GND‧‧‧ reference voltage

OT, OTA‧‧‧ output

Steps of S910~S920‧‧‧ pulse signal generation method

FIG. 1 is a schematic diagram of a pulse latch device 100 according to an embodiment of the present disclosure.

2 is a schematic diagram of an embodiment of a pulse signal generator 120 in accordance with an embodiment of the present disclosure.

3A and 3B are schematic diagrams respectively showing pulse signal generators of different embodiments of the present disclosure.

FIG. 4 is a schematic diagram of a pulse latch device 400 according to another embodiment of the present disclosure.

FIG. 5 is a schematic diagram of a pulse latch device 500 according to still another embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a pulse latch device 600 according to still another embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a pulse latch device 700 according to still another embodiment of the present disclosure.

FIG. 8 is a schematic diagram of a pulse latch device 800 according to still another embodiment of the present disclosure.

FIG. 9 is a flow chart showing a method for generating a pulse signal of a pulse latch according to an embodiment of the present disclosure.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a pulse latch device 100 according to an embodiment of the present disclosure. The pulse latch device 100 includes a pulse latch 110 and a pulse signal generator 120. The pulse latch 110 has a data input terminal DIT, a pulse signal receiving terminal CKT, and a data output terminal DQT. The data input DIT of the pulse latch 110 receives the input data DIN. The pulse latch 110 latches the input data DIN in accordance with the pulse signal PULSE received by the pulse signal receiving terminal CKT. The pulse latch 110 transmits the latched input data DIN as an output data DOUT through the data output terminal DQT. It should be noted that the data input terminal DIT of the pulse latch 110 has a data transmission delay 111 between the data output terminals DQT. This data transmission delay 111 may be caused by a transmission delay common to the circuit elements between the data input terminal DIT of the pulse latch 110 and the data output terminal DQT and the wires between the circuit components, but is not limited thereto.

The pulse signal generator 120 is coupled to the pulse signal of the pulse latch 110 No. Receiver CKT. The pulse signal generator 120 copies the data transfer delay 111 between the data input terminal DIT of the pulse latch 110 and the data output terminal DQT to generate a copy delay 121. The pulse signal generator 120 receives the clock signal CKIN and processes the clock signal CKIN according to the copy delay 121 to generate the pulse signal PULSE.

Here, the pulse width of the pulse signal PULSE generated in accordance with the copy delay 121 and the clock signal CKIN is associated with the copy delay 121. Conceptually, the pulse width of the pulse signal PULSE can be proportional to the size of the replication delay 121. Since the copy delay 121 is obtained by copying the data transfer delay 111, when the data transfer delay 111 becomes large, the copy delay 121 becomes large, and the pulse width of the pulse signal PULSE also increases accordingly. In contrast, when the data transmission delay 111 becomes small, the copy delay 121 becomes smaller, and the pulse width of the pulse signal PULSE is correspondingly reduced.

Specifically, in the pulse signal generator 120, the copy operation of the data transfer delay 111 can be performed by providing the same circuit as that between the data input terminal DIT and the data output terminal DQT of the pulse latch 110. In this way, when the operating voltages accepted by the pulse signal generator 120 and the pulse latch 110 are changed, the circuit providing the data transmission delay 111 in the pulse latch 110 and the copy signal generator 120 provide the copy delay 121. The circuit, the amount of change provided by the delay is similar (approximately the same), and therefore, the pulse signal PULSE generated by the pulse signal generator 120 can cause the pulse latch 110 to normally perform data latching. The action of the lock.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of an embodiment of a pulse signal generator 120 according to an embodiment of the present disclosure. The pulse signal generator 120 includes a delay replica circuit 210 and a logic operation circuit 220. The delay replica circuit 210 receives the clock signal CKIN. In addition, the delay replica circuit 210 provides a copy delay, and performs a delay action for the clock signal CKIN in accordance with the copy delay, and accordingly generates a delayed clock signal dCKIN. The logic operation circuit 220 is coupled to the delay replica circuit 210, and performs a logic operation according to the clock signal CKIN and the delayed clock signal dCKIN, thereby generating a pulse signal PULSE.

Specifically, the logic operation circuit 220 can detect the phase difference between the delayed clock signal dCKIN and the clock signal CKIN, and generate the pulse width of the pulse signal PULSE according to the detected phase difference. In other words, when the replication delay provided by the delay replica circuit 210 is larger, the phase difference between the delayed clock signal dCKIN and the clock signal CKIN is larger, and the pulse signal PULSE generated by the logic operation circuit 220 is also Larger pulse width. In contrast, the smaller the copy delay provided by the delay replica circuit 210, the smaller the phase difference between the delayed clock signal dCKIN and the clock signal CKIN, and the smaller the pulse signal PULSE generated by the logic circuit 220 is. Pulse width.

Please refer to FIG. 3A and FIG. 3B respectively. FIG. 3A and FIG. 3B respectively illustrate schematic diagrams of pulse signal generators according to different embodiments of the present disclosure. In FIG. 3A, the pulse signal generator 310 includes a delay replica circuit 311 and a logic operation circuit 312. The logic operation circuit 312 includes a AND gate AND1 and an inverter IV1. The inverter IV1 is connected in series between the paths of the clock signal CKIN received by the delay replica circuit 311. The input end of the inverter IV1 receives the clock signal CKIN, and the output end of the inverter IV1 is coupled to the delay replica circuit 311. The two inputs of the AND gate AND1 receive the clock signal CKIN and the delayed clock signal dCKIN generated by the delay replica circuit 311, respectively. The AND gate AND1 performs an AND operation on the delayed clock signal dCKIN and the clock signal CKIN, and generates a pulse signal PULSE at the output of the AND gate AND1. Of course, the gate AND1 can also be replaced by an inverter connected to an inverter, or the gate AND1 can be replaced by another logic gate or gates having the same logic operation effect.

In other embodiments of the present disclosure, the logic operation circuit 312 may also be composed of one or more odd-numbered inverters and the AND gate AND1. These inverters may all be connected in series between the paths of the clock signal CKI received by the delay replica circuit 311.

It is further explained that the pulse width of the pulse signal PULSE generated by detecting the phase difference between the delayed clock signal dCKIN and the clock signal CKIN is greater than or equal to the data transmission delay of the pulse latch 110.

In FIG. 3B, the pulse signal generator 320 includes a delay replica circuit 321 and a logic operation circuit 322. The logic operation circuit 322 includes a AND gate AND2 and an inverter IV2. The input terminal of the inverter IV2 is coupled to the output of the delay replica circuit 321 and receives the delayed clock signal dCKIN generated by the delay replica circuit 321. The output of the inverter IV2 is coupled to an input of the AND gate AND2. The other input of the AND gate AND2 receives the clock signal CKIN. The AND gate AND2 performs an AND operation on the delayed clock signal dCKIN and the clock signal CKIN, and generates a pulse signal PULSE at the output of the AND gate AND2. Similarly, and gate AND2 can also It is replaced by an inverter connected in series with an inverter, or the gate AND2 can be replaced by another logic gate or gates having the same logic operation effect.

In other embodiments of the present disclosure, the logic operation circuit 322 may be configured by one or more odd-numbered inverters and the AND gate AND1. These odd-numbered inverters can be connected in series with each other between the path of the AND gate AND2 reception delay clock signal dCKIN.

Referring to FIG. 4, FIG. 4 is a schematic diagram of a pulse latching device 400 according to another embodiment of the present disclosure. The pulse latch device 400 includes a pulse latch 410 and a pulse signal generator 420. The pulse signal generator 420 generates a pulse signal PULSE and provides a pulse signal PULSE to the pulse latch 410. The pulse latch 410 includes inverters IV11, IV12, a transfer gate TR11, and a feedback circuit 411. The input end of the inverter IV11 is coupled to the data input terminal DIT to receive the input data DIN, and the output end of the inverter IV11 is coupled to the first end of the transmission gate TR11. The second end of the transmission gate TR11 is coupled to the input end of the inverter IV12, and the output end of the inverter IV12 is coupled to the data output terminal DQT to generate the output data DOUT. The control terminal of the transmission gate TR11 receives the pulse signal PULSE and the inverted signal PULSEB of the pulse signal PULSE, and turns-on or turn-off according to the pulse signal PULSE and the inverted signal PULSEB of the pulse signal PULSE. The inverted signal PULSEB of the pulse signal PULSE is generated by the inverter IV18 receiving the pulse signal PULSE. In the present embodiment, when the pulse signal PULSE is at a logic high level (the inverted signal PULSEB is at a logic low level), the transfer gate TR11 is turned on. When the pulse signal PULSE is at a logic low level (the inverted signal PULSEB is a logic high) Bit), the transfer gate TR11 is turned off.

The feedback circuit 411 is connected in series between the output of the inverter IV12 and the input of the inverter IV12 (the end of the inverter IV12 coupled to the transfer gate TR11). The feedback circuit 411 includes an inverter IVB1. The input of the inverter IVB1 is coupled to the output of the inverter IV12 to receive the output data DOUT, and the output of the inverter IVB1 is coupled to the input of the inverter IV12. The inverter IVB1 is coupled to the reference voltage VDD and the reference voltage GND through the transistors MP1 and MN1, respectively, wherein the reference voltage VDD may be an operating voltage of the pulse latch device 400, and the reference voltage GND may be a ground voltage.

The transistors MP1 and MN1 function as switching elements, and the transistors MP1 and MN1 are controlled by the pulse signal PULSE and the inverted signal PULSEB of the pulse signal PULSE, respectively. The transistors MP1 and MN1 are turned on at the same time or turned off at the same time. When the transistors MP1 and MN1 are simultaneously turned on, the output of the inverter IVB1 generates an inversion of the output data DOUT to the input of the inverter IV12. In contrast, when the transistors MP1 and MN1 are simultaneously turned off, the output of the inverter IVB1 does not provide a signal output while maintaining a high impedance state.

The pulse signal generator 420 includes a delay replica circuit 421 and a logic operation circuit 422. The delayed replica circuit 421 includes inverters IV14 and IV15 and a transfer gate TR12. The logic operation circuit 422 includes inverters IV19, IV16 and an anti-gate NAND1. In the delay replica circuit 421, the inverter IV14, the transfer gate TR12, and the inverter IV15 are serially connected in series, and the control terminals of the transfer gate TR12 are commonly coupled to the input terminal of the inverter IV14 to determine to remain in the on state. . It is worth noting that The circuit formed by the inverter IV14, the transmission gate TR12 and the inverter IV15 is between the data input terminal DIT and the data output terminal DQT of the pulse latch 410, and is composed of an inverter IV11, a transmission gate TR11 and an inverter. The circuit formed by IV12 is similar. That is, the copy delay generated by the delayed copy circuit 421 is almost the same as the data transfer delay between the data input terminal DIT of the pulse latch 410 and the data output terminal DQT.

Further, in the present embodiment, the transfer gates TR11 and TR12 can be constituted by a transistor having a low threshold voltage, and the data transfer speed can be accelerated. Moreover, by using a transistor having a low threshold voltage only on the transmission gates TR11 and TR12, the data transmission speed is increased without excessive leakage current. Therefore, in the present embodiment, the transmission gates TR11 and TR12 constituted by the transistors having a low threshold voltage can obtain a large amount of speed increase under a small amount of leakage.

Please note that in the present embodiment, the copy delay generated by the delay replica circuit 421 and the data transmission delay between the data input terminal DIT and the data output terminal DQT of the pulse latch 410 may be in accordance with the voltage of the operating voltage VDD. Change and dynamically adjust. The important point is that the pulse width of the pulse signal PULSE is dynamically adjusted with the data transmission delay. That is, even if the pulse latch device 400 operates in a state of so-called sub-threshold voltage, the sensitivity of the circuit voltage of the sub-threshold voltage to the voltage has been different from the circuit delay of the high-threshold voltage, the pulse signal PULSE. It is also possible to adjust to have a suitable pulse width so that the pulse latch device 400 can maintain normal operation.

Please refer to FIG. 5. FIG. 5 illustrates a pulse latching device according to still another embodiment of the present disclosure. Set the schematic diagram of 500. The pulse latch device 500 includes a pulse latch 510 and a pulse signal generator 520. The pulse latch 510 includes inverters IV21, IBUF1 and IBUF2, a transfer gate TR21, a NAND gate NAND21, a NAND24, and transistors MP2 and MN2. Unlike the foregoing embodiment, the pulse latch 510 also receives the inverted signal SETB of the set signal SET and the inverted signal CLRB of the clear signal CLR. The input terminal of the NAND gate NAND21 is coupled to the transmission gate TR21, and the other input terminal of the NAND gate NAND21 receives the inverted signal SETB of the setting signal SET. An input terminal of the NAND gate NAND24 is coupled to the output terminal of the NAND gate NAND21, and the other input terminal of the NAND gate NAND24 receives the inverted signal CLRB of the clear signal CLR. When both the set signal SET and the clear signal CLR are not enabled, that is, both are logic low, the functions of the NAND21 and NAND24 are equivalent to the inverter, and the pulse latch at this time The circuit of the 510 is of the same circuit architecture as the pulsed latch 410 of the previous embodiment.

It should be noted that the pulse latch 510 further includes inverters IBUF1 and IBUF2 as output buffers, and inverters IBUF1 and IBUF2 are connected in series with each other, and can be used to provide an output. The fan out capability of the data DOUT.

In addition, in the case where the setting signal SET is at a logic high level, the inverted signal SETB of the setting signal SET is at a logic low level, and the output data DOUT is set to a logic high level. When the clear signal CLR is at a logic high level, the inverted signal CLRB of the clear signal CLR is at a logic low level, and the output of the NAND gate NAND24 is at a logic high level. In this way, the output data DOUT will Cleared to equal the logic low level.

The pulse signal generator 520 includes a delay replica circuit 521 and a logic operation circuit 522. The delay replica circuit 521 includes an inverter IV23, a transfer gate TR22, and a reverse gate NAND22. The circuit structure of the delay replica circuit 521 is similar to the inverter IV21, the transfer gate TR21, and the inverse gate NAND21 in the pulse latch 510. The difference is that the control terminal of the transmission gate TR21 receives the pulse signal PULSE and the inverted signal PULSEB of the pulse signal PULSE, and the control terminal of the transmission gate TR22 is coupled to the input terminal of the inverter IV23. The inverted signal PULSEB is generated by the inverter IV2I according to the pulse signal PULSE.

The inverter IV23 and the transmission gate TR22 are connected in series with each other, and the transmission gate TR22 is coupled to an input terminal of the NAND gate NAND22, and the other input terminal of the gate NAND22 receives the reference voltage VDD. Please note that since the logic gate connected to the feedback latch circuit 510 at both ends of the feedback circuit 511 is the reverse gate NAND21, the data transfer delay in the replica pulse latch 510 corresponds to the late replica circuit 521. The location is constructed in anti-gate NAND22 to more accurately replicate data transmission delays to obtain replication delays.

The logic circuit 522 includes an inverter IV28, an inverse OR gate NOR25, an inverse gate NAND23, and an inverter IV29. The logic circuit 522 in this embodiment constructs the inverse OR gate NOR25 to receive the setting signal SET and the clear signal CLR. When at least one of the setting signal SET and the clear signal CLR is enabled (equal to the logic high level), the reverse Or gate NOR25 outputs a logic low level signal and masks the generation of pulse signal PULSE through NAND gate NAND23.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a pulse latch device 600 according to still another embodiment of the present disclosure. The pulse latch device 600 includes a pulse latch 610 and a pulse signal generator 620. The pulse latch 610 includes inverters IV31, IV32, IBUF1, and IBUF2, a transfer gate TR31, and a feedback circuit 611. The feedback circuit 611 includes transistors MP3, MN3 and an anti-gate NAND34. The pulse signal generator 620 includes a delay replica circuit 621 and a logic operation circuit 622. The delayed replica circuit 621 includes an inverter IV33, a transfer gate TR32, and an inverter IV34. The logic operation circuit 622 includes a reverse gate NAND33, inverters IV38, and IV39.

The inverter IV3I receives the pulse signal PULSE and generates the inverted signal PULSEB of the pulse signal PULSE.

The difference from the embodiment of FIG. 5 is that the embodiment of FIG. 6 only receives the clear signal CLR and does not accept the set signal SET, so the gate NAND 21 of FIG. 5 is replaced by the inverter IV32 of FIG. 6 and the delay of FIG. The replica circuit 621 thus uses the inverter IV34 to replicate the delay of the inverter IV32 and directly inputs the inverted signal CLRB of the clear signal CLR into the inverter NAND33 of FIG. 6 (cf. the inverter NAND23 of FIG. 5). Similarly, the pulse latching device of the present disclosure can also receive only the setting signal SET without receiving the clear signal CLR, for example, replacing the anti-gate NAND 24 with respect to the clear signal CLR in the embodiment of FIG. 5 into an inverter, and The inverted signal SETB of the set signal SET is input to the gate NAND23. Since the implementation configuration is similar to that of FIG. 5, its function will not be described here.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of a pulse latch device 700 according to still another embodiment of the present disclosure. The pulse latch device 700 includes a pulse latch 710 to And a pulse signal generator 720. The pulse latch 710 includes inverters IV41, IV42, IBUF1 and IBUF2, a transfer gate TR41, and a feedback circuit 711. The feedback circuit 711 includes an inverter IV43 and a transfer gate TR43. The pulse signal generator 720 then includes a delay replica circuit 721 and a logic operation circuit 722. The delayed replica circuit 721 includes an inverter IV44, a transfer gate TR42, and an inverter IV45. The logic operation circuit 722 includes an inverse gate NAND 43, an inverter IV46, and an IV48.

The feedback circuit 711 of the present embodiment is configured by an inverter IV43 and a transmission gate TR43, wherein an input end of the inverter IV43 is coupled to an output terminal of the inverter IV42, and an output terminal of the inverter IV43 The second end of the transmission gate TR43 is coupled to the input end of the inverter IV42. The control terminal of the transmission gate TR43 receives the pulse signal PULSE and the inverted signal PULSEB of the pulse signal PULSE. The transfer gate TR43 is turned on or off in accordance with the pulse signal PULSE and the inverted signal PULSEB. In the present embodiment, when the pulse signal PULSE is at a logic low level, the transfer gate TR43 is turned on. In contrast, when the pulse signal PULSE is at a logic high level, the transfer gate TR43 is turned off. And, when the transfer gate TR43 is turned on, the signal generated at the output of the inverter IV43 can be transmitted to the input terminal of the inverter IV42, and when the transfer gate TR43 is turned off, the output of the inverter IV43 The signal generated at the terminal is blocked by the transmission gate TR43 and is not transmitted to the input terminal of the inverter IV42.

The inverted signal PULSEB is generated by the inverter IV4I according to the pulse signal PULSE.

Please refer to FIG. 8. FIG. 8 illustrates a pulse latching device according to still another embodiment of the present disclosure. Set the schematic diagram of 800. The pulse latch device 800 includes a pulse latch 810 and a pulse signal generator 820. The pulse latch 810 includes an inverter formed by transistors MP53, MP54, MN53, MN54, inverters IV52, IV53, and a feedback circuit 811. Among them, the transistors MP53 and MP54 are P-type transistors, and the transistors MN53 and MN54 are N-type transistors. The first end of the transistor MP53 is coupled to the reference voltage VDD, and the second end of the transistor MP53 is coupled to the first end of the transistor MP54. The control terminal of the transistor MP53 is coupled to the inverted signal PULSEB of the inverter IV5I receiving the pulse signal PULSE. The second end of the transistor MP54 is coupled to the first end of the transistor MN53 and serves as the output terminal OT of the inverter formed by the transistors MP53, MP54, MN53, MN54. The control terminals of the transistors MP54 and MN53 collectively receive the input data DIN. The second end of the transistor MN53 is coupled to the first end of the transistor MN54, and the second end of the transistor MN54 is coupled to the reference voltage GND. The control terminal of transistor MN54 receives pulse signal PULSE.

The tri-state inverter formed by the transistors MP53, MP54, MN53, MN54 can decide whether to transmit the inversion of the input data DIN to the output terminal OT according to the pulse signal PULSE and its inverted signal PULSEB. In this embodiment, when the pulse signal PULSE is at a logic high level, the tristate inverter formed by the transistors MP53, MP54, MN53, MN54 can transmit the inversion of the input data DIN to the output terminal OT. In contrast, when the pulse signal PULSE is at a logic low level, the tristate inverter formed by the transistors MP53, MP54, MN53, and MN54 outputs a high impedance and does not affect the voltage value at which the output terminal OT is located.

The inputs of the inverters IV52 and IV53 are commonly coupled to the output terminal OT, The output of the phase comparator IV52 generates an output data DOUT, and the output of the inverter IV53 is coupled to the feedback circuit 811. The feedback circuit 811 is a three-state inverter including transistors MP56, MN56 and inverter IV56. The inverter IV56 is coupled to the reference voltage VDD through the transistor MP56, and the inverter IV56 is coupled to the reference voltage GND through the transistor MN56. The control terminal of the transistor MP56 receives the pulse signal PULSE, and the transistor MN56 receives the inverted signal PULSEB of the pulse signal PULSE.

The pulse signal generator 820 includes a delay replica circuit 821 and a logic operation circuit 822. The delayed replica circuit 821 includes an inverter composed of transistors MP51, MP52, MN51, and MN52, inverters IV54, IV55, and a feedback circuit 8211. Among them, the transistors MP51 and MP52 are P-type transistors, and the transistors MN51 and MN52 are N-type transistors. The first end of the transistor MP51 is coupled to the reference voltage VDD, and the second end of the transistor MP51 is coupled to the first end of the transistor MP52. The control terminal of the transistor MP51 is coupled to the inverter IV58. The second end of the transistor MP52 is coupled to the first end of the transistor MN51 and serves as an output terminal OTA of the inverter formed by the transistors MP51, MP52, MN51, MN52. The control terminals of the transistors MP51, MP52, MN51 and MN52 are coupled to each other. The second end of the transistor MN51 is coupled to the first end of the transistor MN52, and the second end of the transistor MN52 is coupled to the reference voltage GND.

The input of the inverter IV54 is coupled to the output terminal OTA, and the output of the inverter IV54 is coupled to the logic operation circuit 822. The input of the inverter IV55 is coupled to the output terminal OTA, and the output of the inverter IV55 is floated. In addition, the feedback circuit 8211 includes transistors MP55, MN55, and an inverter IV57. The input end of the inverter IV57 is coupled to the reference voltage GND, and the output end of the inverter IV57 is coupled. To the output OTA. The inverter IV57 is coupled to the reference voltage VDD through the transistor MP55, and coupled to the reference voltage GND through the transistor MN55. In addition, the control terminal of the transistor MP55 is coupled to the reference voltage VDD, and the control terminal of the transistor MN55 is coupled to the control terminal of the transistor MP55 to receive the reference voltage VDD. That is, the transistor MP55 is kept in the off state, and the transistor MN55 is kept in the on state. Also, since the input terminal of the inverter IV57 is coupled to the reference voltage GND, the output of the inverter IV57 is maintained in a high impedance state.

The feedback circuit 8211 in the delayed replica circuit 821 is a data transmission delay in the replica pulse latch 810 that provides a more complete replica replica circuit 821, including the effects of leakage current and parasitic capacitance on the transmission delay in data transmission. More accurate copy delay.

The logic operation circuit 822 includes an inverse gate NAND53 and inverters IV58 and IV59. The logic operation circuit 822 operates in the same manner as the logic operation circuit in the foregoing various embodiments, and will not be described here.

Please refer to FIG. 9 . FIG. 9 is a flowchart of a method for generating a pulse signal of a pulse latch according to an embodiment of the present disclosure. Wherein, the pulse latch has a data input end and a data output end, and the step of generating the pulse signal comprises: in step S910, copying the data transmission delay between the data input end of the pulse latch and the data output end to obtain The copy delay is followed; in step S920, the clock signal is received, and the clock signal is logically operated according to the copy delay to generate a pulse signal.

With regard to the implementation details of the steps of the pulse signal generating method described above, the foregoing embodiments of the pulse latching device and related embodiments are detailed in detail. Introduction, the following will not repeat.

In summary, the present disclosure provides for utilizing a pulse signal generator to replicate the data transmission delay between the data input and the data output of the pulse latch to obtain a copy delay. The clock signal is processed according to the copy delay to generate a pulse signal. In this way, the pulse width of the pulse signal can be adaptively adjusted according to the process conditions of the pulse latch device, the process parameters, and the magnitude of the operating voltage received by the pulse latch device. Therefore, the pulse latching device provided by the present disclosure can be applied to a wide range of operating voltages, and in the application of low operating voltage, the pulsed latching device of the present disclosure can effectively operate and effectively save energy consumption. .

100‧‧‧pulse latching device

110‧‧‧pulse latch

111‧‧‧ Data transmission delay

120‧‧‧ pulse signal generator

121‧‧‧Copy delay

DIT‧‧‧ data input

CKT‧‧‧ pulse signal receiving end

DQT‧‧‧ data output

DIN‧‧‧ input data

PULSE‧‧‧ pulse signal

DOUT‧‧‧Output data

CKIN‧‧‧ clock signal

Claims (18)

A pulse type latching device comprising: a pulse latching device having a data input end, a pulse signal receiving end and a data output end, the data input end receiving an input data, the pulse type latching device according to the a pulse signal received by the pulse signal receiving end latches the input data, and transmits the latched input data as an output data through the data output end; and a pulse signal generator coupled to the pulse latch The pulse signal receiving end of the locker, the pulse signal generator copies a data transmission delay between the data input end of the pulse latch and the data output end to obtain a copy delay, and the pulse signal generator receives The clock signal is processed according to the copy delay to generate the pulse signal. The pulse latching device of claim 1, wherein the pulse signal generator comprises: a delay replica circuit that receives the clock signal and provides the copy delay, delaying the clock signal according to the copy delay And generating a delayed clock signal; and a logic operation circuit coupled to the delay replica circuit to generate the pulse signal according to the delayed clock signal and the clock signal. The pulse latching device of claim 2, wherein the pulse latch comprises: a first inverter having an input end and an output end, the input end of the first inverter receiving the Input data; a first transmission gate having a first end, a second end, and a control end, the first end of the first transmission gate being coupled to the output end of the first inverter, the control end of the first transmission gate receiving the a pulse signal; and a second inverter having an input end and an output end, the input end of the second inverter is coupled to the second end of the first transfer gate, and the output end of the second inverter is coupled Connected to the data output end; and a feedback circuit serially connected between the data output end and the second end of the first transmission gate, the feedback circuit receives and determines whether to return the output data according to the pulse signal To the second end of the first transmission gate. The pulse latching device of claim 3, wherein the delay replica circuit comprises: a third inverter having an input end and an output end, the input end of the third inverter receiving the clock a second transmission gate having a first end, a second end, and a control end, the first end of the second transmission gate being coupled to the output end of the third inverter, the control end of the transmission gate receiving the signal a clock signal; and a fourth inverter having an input end and an output end, the input end of the fourth inverter being coupled to the second end of the second transfer gate, the output end of the fourth inverter It is coupled to the logic operation circuit. The pulsing latch device of claim 4, wherein the first transfer gate and the second transfer gate are formed by a transistor having a low threshold voltage. The pulse type latch device according to claim 3, wherein the back The circuit includes: a first tri-state inverter having an input end, an output end, and a control end, wherein the input end of the first tri-state inverter receives the output data, and the output end of the first tri-state inverter And being coupled to the input end of the second inverter, the control end of the first three-state inverter receives the pulse signal, and the first three-state inverter determines, according to the pulse signal, whether to output the inverse of the output data. Phase to the input of the second inverter. The pulse latching device of claim 3, wherein the feedback circuit comprises: a third inverter having an input end and an output end, the input end of the third inverter receiving the output data And a second transmission gate having a first end, a second end, and a control end, the first end of the second transmission gate is coupled to the output end of the third inverter, and the second transmission gate is second The terminal is coupled to the input end of the second inverter, and the control end of the second transmission gate receives the pulse signal. The pulse latching device of claim 2, wherein the logic operating circuit comprises: N inverters having an input end and an output end, the inverters being connected in series with each other, the inverters The first input terminal receives the delayed clock signal, wherein N is an odd number; and the first gate receives the clock signal, and the second input terminal of the gate is coupled to the inversion The last output of the device, the output of the gate generates the pulse signal. The pulse latching device of claim 2, wherein the logic operation circuit comprises: N inverters having an input end and an output end, the inverters being serially connected to each other at the delay replica circuit. Between the paths of the clock signals, wherein the input of the first one of the inverters receives the clock signal, and the output of the last one of the inverters is coupled to the delay replica circuit, where N is An odd number; and a first gate receiving the clock signal, the second input of the gate receiving the delayed clock signal, and the output of the gate generates the pulse signal. The pulsing latch device of claim 2, wherein the pulsing latch comprises: a tri-state inverter having an input end, an output end, and a control end, the control of the tri-state inverter Receiving the pulse signal, the input end of the tristate inverter receives the input data, and the tristate inverter determines, according to the pulse signal, whether to transmit the inverted input data to the output end of the tristate inverter a first inverter having an input end and an output end, wherein an input end of the first inverter is coupled to an output end of the tri-state inverter, and an output end of the second inverter generates the output data a second inverter having an input end and an output end, the input end of the second inverter being coupled to the output end of the tri-state inverter; and a first feedback circuit coupled in series Between the output of the inverter and the output of the second inverter, receiving and determining, according to the pulse signal, whether to return the inverted signal of the signal at the output of the second inverter to the tristate The output of the inverter. The pulsing latch device of claim 10, wherein the tri-state inverter comprises: a first transistor having a first end, a second end, and a control end, the first transistor One end is coupled to a first reference voltage, and the control end of the first transistor receives an inverted signal of the pulse signal; a second transistor has a first end, a second end, and a control end, the second electric The first end of the crystal is coupled to the second end of the first transistor, the control end of the second transistor receives the input data, and the second end of the second transistor is the output end of the tri-state inverter a third transistor having a first end, a second end, and a control end, the first end of the third transistor being coupled to the second end of the second transistor, the control end of the third transistor receiving The input data; and a fourth transistor having a first end, a second end, and a control end, the first end of the fourth transistor being coupled to the second end of the third transistor, the fourth transistor The control terminal receives the pulse signal, and the second end of the fourth transistor is connected to a second reference voltage Wherein the first and second electrical same crystal type, the same as the third and the fourth transistor type, and the first and the third transistor of complementary type. The pulse latching device of claim 10, wherein the first feedback circuit comprises: a third inverter having an input end, an output end, and a control end, the input of the third inverter The end is coupled to the output of the second inverter, and the output of the third inverter The terminal is coupled to the output end of the tristate inverter, and the control end of the tristate inverter receives the pulse signal, and the tristate inverter determines, according to the pulse signal, whether to output the output of the second inverter The signal of the terminal is inverted to the output of the tristate inverter. The pulse latching device of claim 10, wherein the delay replica circuit comprises: a third inverter having an input end, an output end, and a control end, the control end of the fourth inverter and The input terminal commonly receives the clock signal, the third inverter transmits the inverted clock signal to the output of the third inverter; a fourth inverter has an input end and an output end, the first An input end of the fourth inverter is coupled to an output end of the third inverter, an output of the fourth inverter generates the delayed clock signal; a fifth inverter has an input end and an output end, An input end of the fifth inverter is coupled to an output end of the third inverter, an output end of the fifth inverter is floating, and a second feedback circuit is coupled to the third inverting circuit The output of the device. The pulsing latch device of claim 13, wherein the third inverter comprises: a first transistor having a first end, a second end, and a control end, the first transistor One end is coupled to a first reference voltage, and the control end of the first transistor receives an inverted signal of the clock signal; a second transistor has a first end, a second end, and a control end, the second a first end of the transistor is coupled to the second end of the first transistor, and the second transistor is controlled The terminal is coupled to the control end of the first transistor, the second end of the second transistor is an output end of the third inverter; and a third transistor has a first end, a second end, and a control end The first end of the third transistor is coupled to the second end of the second transistor, the control end of the third transistor is coupled to the control end of the first transistor, and a fourth transistor has a first end, a second end, and a control end, the first end of the fourth transistor is coupled to the second end of the third transistor, and the control end of the fourth transistor is coupled to the control of the first transistor The second terminal of the fourth transistor is connected to a second reference voltage, wherein the first and second transistors have the same type, and the third and fourth transistors have the same type, and the first The types of the first and third transistors are complementary. The pulse latching device of claim 13, wherein the second feedback circuit comprises: a sixth inverter having an input end, an output end, and a control end, the input of the sixth inverter The terminal is coupled to a second reference voltage, the output of the sixth inverter is coupled to the output of the fourth inverter, and the control terminal of the sixth inverter is coupled to a first reference voltage. The output of the sixth inverter exhibits a high impedance state. The pulse latching device of claim 1, wherein the pulse signal generator further comprises receiving a clear signal and/or a set signal, and setting the pulse according to the clear signal and/or the set signal. a logic level of the signal, the pulse latch further includes receiving the clear signal and/or the setting signal, and the pulse latch is configured to clear the output data according to the clear signal or set according to the set signal Set the output data. A pulse signal generating method for a pulse latch, wherein the pulse latch has a data input end and a data output end, comprising: copying the data input end of the pulse type latch to the data output end And a data transmission delay to obtain a copy delay; and receiving a clock signal, the clock signal is processed according to the copy delay to generate the pulse signal. The method for generating a pulse signal according to claim 17, wherein the step of processing the clock signal according to the copy delay to generate the pulse signal comprises: delaying the clock signal according to the copy delay to generate a Delaying the clock signal; and performing a logic operation on the delayed clock signal and the clock signal to generate the pulse signal.