TWI518766B - Method of forming opening on semiconductor substrate - Google Patents

Description

Method of forming an opening on a semiconductor substrate

SUMMARY OF THE INVENTION The present invention relates to a method of forming an opening in a semiconductor substrate, and more particularly to a method of forming an opening by using boron nitride as a hard mask, which can effectively avoid line distortion in a conventional damascene process.

Inlaid interconnect technology is the main technology for forming metal interconnects in integrated circuits. It can also be said that the main manufacturing methods of copper wires in the semiconductor industry can be divided into single damascene. Process and dual damascene process. Among them, the dual damascene process is widely used in the inlaid interconnect technology because it can reduce the process steps, reduce the contact resistance between the wires and the plug, and improve the reliability. In addition, in order to reduce the resistance value of the metal interconnect and the RC delay to increase the signal transmission speed, the current dual damascene process is mostly in the dielectric layer composed of low-k materials. A double damascene pattern having a trench and a via is etched, and then copper metal is filled and planarized to complete the fabrication of the metal interconnect. According to the way of etching patterns in the dielectric layer, the dual damascene process can be further subdivided into a trench-first process, a via-first, and a partial-via-partial-via- First) process, and self-aligned process.

In a typical damascene process, the hard mask layer typically has a compressive stress that can be as high as -500 megapascals (MPa). When the compressive stress is directly applied to the dielectric layer having low mechanical strength and tensile stress, the dielectric layer will be subjected to line distortion, so that the original should be Straight ditches or via holes create wigling, which in turn affects the yield of subsequent metallization processes.

The present invention thus proposes a method of forming an opening in a semiconductor substrate, which can effectively avoid the deformation of the line, and is particularly suitable for the damascene process of the metal interconnect.

In accordance with an embodiment of the present invention, the present invention provides a method of forming an opening in a semiconductor substrate. This method first provides a substrate. A dielectric layer and a cap layer are then formed on the substrate, wherein the ratio of the thickness of the dielectric layer to the thickness of the cap layer is substantially between 15 and 1.5. A patterned boron nitride layer is then formed over the cap layer. Finally, an etching process is performed, using the patterned boron nitride layer as a mask, etching the cap layer and the dielectric layer, and forming an opening in the cap layer and the dielectric layer.

In accordance with another embodiment of the present invention, the present invention provides a method of forming an opening in a semiconductor substrate. The method first provides a substrate and then forms a dielectric layer on the substrate. A patterned composite hard mask layer is then formed over the dielectric layer, wherein the patterned composite hard mask layer comprises at least a metal nitride layer and a boron nitride layer. Finally, an etching process is performed, using the patterned composite hard mask layer as a mask, etching the dielectric layer, and forming an opening in the dielectric layer.

In accordance with yet another embodiment of the present invention, the present invention provides a method of forming an opening in a semiconductor substrate. The method first provides a substrate and then forms a dielectric layer on the substrate. Forming a patterned composite hard mask layer on the dielectric layer, wherein the patterned composite hard mask layer comprises at least a first boron nitride layer and a second boron nitride layer, wherein the second boron nitride layer The layer is disposed on the first boron nitride layer, and the concentration of boron in the second boron nitride layer is different from the concentration of boron in the first boron nitride layer. Finally, an etching process is performed, using the patterned composite hard mask layer as a mask, etching the dielectric layer and forming an opening in the dielectric layer.

The invention mainly utilizes a boron nitride layer as a hard mask layer, and is matched with boron atoms of different concentrations or with a metal nitride layer to form a composite hard mask layer. The composite hard mask layer can have a high etching selectivity ratio compared to the dielectric layer, and can effectively avoid the occurrence of line deformation.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Referring to FIGS. 1 to 3, there are shown schematic steps of a method of forming an opening on a semiconductor substrate in a first embodiment of the present invention. As shown in FIG. 1, a substrate 300 is first provided. The substrate 300 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, and a silicon-on insulator. -insulator, SOI) substrate, even glass substrate, quartz substrate or ceramic substrate, etc., but not limited thereto. At least one conductive element (not shown) is formed on the surface of the substrate 300, and the conductive element may be a drain/source and a gate of the metal oxide semiconductor transistor, a resistor, and a through-silicon via (Through-Silicon Via). TSV), doped regions, metal wire layers, and the like. Between the conductive element and the substrate 300, at least one interlayer dielectric layer (not shown) may be formed depending on product design and process requirements.

Next, a dielectric layer 302 is formed on the substrate 300 by using, for example, plasma enhanced chemical vapor deposition (PECVD) or high density plasma CVD. , but not limited to this. The dielectric layer 302 may comprise one or more layers of dielectric materials, and various dielectric materials may be used. In the preferred embodiment of the present invention, the dielectric layer 302 is preferably made of a material having a dielectric constant of less than 3.5, such as FSG (fluorine). -doped oxide), HSQ (hydrogen silsesquioxane) (SiO:H), MSQ (methyl silsesquioxane) (SiO:CH ₃ ), HOSP, H-PSSQ (hydrio polysilsesquioxane), M-PSSQ (methyl polysilsesquioxane), P-PSSQ ( Phenyl polysilsesquioxane) or porous sol-gel, etc., but not limited thereto. For example, the dielectric layer 302 may also be made of a material such as cerium oxide. In a preferred embodiment of the invention, a cap layer 304 is selectively formed over the dielectric layer 302. The cap layer 304 enhances the adhesion of the subsequently patterned hard mask layer 306 (not shown) on the dielectric layer 302. The material of the cap layer is, for example, tantalum nitride (SiN), yttrium oxide (SiO ₂ ), tantalum carbide (SiC), niobium oxynitride (SiCN) or bismuth oxynitride (SiON), but is not limited thereto. The ratio of the thickness of the dielectric layer 302 to the thickness of the cap layer 304 is substantially between 15 and 1.5. In one embodiment, the thickness of the dielectric layer 302 is substantially between 1000 angstroms and 3000 angstroms, and the thickness of the cap layer 304 is substantially between 200 angstroms and 600 angstroms.

Next, as shown in FIG. 2, a patterned hard mask layer 306 is formed over the cap layer 304. For example, a hard mask layer (not shown) is deposited on the surface of the cap layer 304, and then a photoresist layer (not shown) is coated on the surface of the hard mask layer, and a lithography and etching process is performed. To form a patterned hard mask layer 306 such that the patterned hard mask layer 306 has at least one opening 308 for defining a subsequent location in the dielectric layer 302, such as a trench in the damascene process or The location of the via. One of the features of this embodiment is that the patterned hard mask layer 306 is a boron nitride (BN) layer. The manner of forming the boron nitride layer can be formed by conventional in-situ deposition, for example, by introducing a boron atom together with a nitrogen atom to form a boron nitride layer in a deposition process, and the flow rate through the pass can be Controlling the concentration of boron atoms in the boron nitride layer. Of course, the boron nitride layer can also be formed in other ways, such as by a deposition process in conjunction with an ion implant.

As shown in FIG. 3, an etching process is then performed to etch the cap layer 304 and the dielectric layer 302 by using a patterned hard mask layer 306 (optionally with the patterned photoresist layer) as a mask. An opening 310 is formed in the cap layer 304 and the dielectric layer 304. The embodiment (shape, depth) of the opening 310 can be adjusted according to various processes or product requirements. For example, in the damascene process, the opening 310 can be used as a ditch in a single damascene process or at least one ditch or via hole in a dual damascene process. By.

Since the present invention uses boron nitride as the patterned hard mask layer 306, the conventional patterned hard mask layer can be avoided, which has excessive compressive stress and causes the opening 310 in the low-k dielectric layer 302. The inner wall creates a problem of line deformation. Please refer to FIG. 4 , which is a schematic diagram showing the relationship between stress and boron atom concentration when boron nitride is used as a patterned hard mask layer, wherein the horizontal axis is a boron atom in the patterned hard mask layer. The percentage of all atoms (unit: %), and the vertical axis is the stress value (unit: MPa). As can be seen from Fig. 4, as the concentration of boron atoms in the patterned hard mask layer 306 increases, the stress can be gradually changed from compressive stress (-500 MPa) to tensile stress (750 MPa). Therefore, if the boron atom concentration is appropriately adjusted, a patterned hard mask layer 306 having different stresses can be generated, so that the stress acting on the lower dielectric layer 302 can be tuned to avoid the opening 310. The inner wall causes a problem of line deformation after the etching process.

Please refer to FIG. 5, which is a schematic diagram showing the etching rate and boron atom concentration when boron nitride is used as a patterned hard mask layer, wherein the horizontal axis is boron atoms in the patterned hard mask layer. The percentage of all atoms (unit: %), and the vertical axis is the etching rate (unit: angstrom/minute, /min). As can be seen from Fig. 5, as the concentration of boron atoms in the patterned hard mask layer 306 increases, the etching rate gradually decreases. The value is substantially 920 angstroms/minute compared to the etch rate of the dielectric layer 302 (indicated by a square dot in Fig. 5). Therefore, if the concentration of boron atoms in the patterned hard mask layer 306 is larger, the etching selectivity ratio to the dielectric layer 302 will also increase relatively.

It can be seen from FIGS. 4 and 5 that the concentration of boron atoms in the patterned hard mask layer 306 affects the stress on the one hand, and affects the etching selectivity ratio of the dielectric layer 302 on the one hand, so that appropriate A boron atom concentration is required. In a preferred embodiment of the invention, in the patterned hard mask layer 306, the concentration of boron in the total atomic proportion is generally between 50% and 80%, preferably between 60% and 70%. , which is 65% best. In addition, the boron nitride in the patterned hard mask layer of the present embodiment may have a stress ranging substantially from -50 MPa to 400 MPa, preferably from 10 MPa to 100 MPa, wherein It is also best at 65 MPa.

Please refer to FIG. 6 and FIG. 7 , which are schematic diagrams showing the steps of a method for forming an opening on a semiconductor substrate in a second embodiment of the present invention. As shown in FIG. 6, a substrate 400 is first provided, followed by a dielectric layer 402 and an optional cap layer 404 formed on the substrate 400. The embodiment of the substrate 400, the dielectric layer 406, and the cap layer 404 are the same as those of the first embodiment, and are not described herein. A patterned hard mask layer 406 is then formed over the dielectric layer 406 (or the optional cap layer 404) having an opening 408. In the present embodiment, the patterned hard mask layer 406 is a composite layer comprising a boron nitride layer 407 and a metal nitride layer 409. The upper and lower positions of the boron nitride layer 407 and the metal nitride layer 409 and the number of stacked layers can be adjusted depending on the product. Preferably, the metal nitride layer 409 is disposed on the boron nitride layer 407. In a preferred embodiment of the invention, the metal nitride layer 409 is a titanium nitride (TiN). The manner of forming the boron nitride layer 407 is the same as that of the first embodiment, and will not be described herein. Finally, as shown in FIG. 7, an etching process is performed, using the patterned hard mask layer 406 as a mask, etching the cap layer 404 and the dielectric layer 402, and forming an opening in the cap layer 404 and the dielectric layer 404. 410. In the present embodiment, since the metal nitride layer 409 is disposed above the boron nitride layer 407, the metal nitride layer 409 such as titanium nitride can provide better contrast than the dielectric layer 402 during the etching process. The etching selectivity is selected, and the boron nitride layer 407 closer to the dielectric layer 402 adjusts the stress of the dielectric layer 402 to avoid the occurrence of conventional line deformation.

Please refer to FIGS. 8-9, which are schematic diagrams showing the steps of a method for forming an opening on a semiconductor substrate according to a third embodiment of the present invention. As shown in FIG. 9, a substrate 500 is first provided, followed by a dielectric layer 502 and an optional cap layer 504 formed on the substrate 500. The embodiment of the substrate 500, the dielectric layer 502, and the cap layer 504 is the same as that of the first embodiment, and will not be described herein. A patterned hard mask layer 506 is then formed over dielectric layer 502 (or optional cap layer 504) having an opening 508. In the present embodiment, the patterned hard mask layer 506 is a composite layer comprising a first boron nitride layer 507 and a second boron nitride layer 509. In a preferred embodiment of the invention, the concentration of boron in the first boron nitride 507 and the second boron nitride layer 509 is substantially between 50% and 80% of the total atomic ratio. In this embodiment, the concentration of boron atoms in the second boron nitride layer 509 may be different from the concentration of boron atoms in the first boron nitride layer 507. Preferably, the concentration of boron atoms in the second boron nitride layer 509 It will be greater than the concentration of boron atoms in the first boron nitride layer 507. Finally, as shown in FIG. 9, an etching process is performed, using the patterned hard mask layer 506 as a mask, etching the cap layer 504 and the dielectric layer 502, and forming a cap layer 504 and a dielectric layer 504. Opening 510. In the present embodiment, since the second boron nitride layer 509 having a higher boron atom concentration is disposed above the first boron nitride layer 507 having a lower boron atom concentration, the second boron nitride layer 509 is etched. During the process, a better etch selectivity ratio can be provided compared to the dielectric layer 502 (refer to FIG. 5), and the first boron nitride layer 507 closer to the dielectric layer 502 can adjust the stress of the dielectric layer 502. Situation (please refer to Figure 4) to avoid the occurrence of conventional line deformation.

It should be noted that the composite patterned hard mask layer 506 of the third embodiment is not limited to the first boron nitride layer 507 and the second boron nitride layer 509. In other related embodiments, the patterning is performed. The hard mask layer 506 may further include a third boron nitride layer (not shown) disposed on the second boron nitride layer 509, or a fourth boron nitride layer (not shown) disposed on the third nitride layer. Preferably, on the boron layer, the boron concentration in the upper boron nitride layer is higher, and the boron concentration in the lower boron nitride layer is lower. In other embodiments of the present invention, the third embodiment may also be combined with the second embodiment. For example, the patterned hard mask layer 507 may include a plurality of boron nitride layers, and the boron nitride layers may be disposed above There are one or more layers of metal nitride, such as a layer of titanium nitride.

Furthermore, the present invention provides a method of forming an opening in a semiconductor substrate that is particularly suitable for use in a single damascene process or a dual damascene process in a metal interconnect system. For example, when a conductive layer (for example, a metal wiring of a lower layer) is disposed on the substrate, the method of the present invention can be used to form an opening to expose the conductive layer, and after filling the conductive layer into the opening of the dielectric layer, After the planarization process, the lower conductive layer can be connected to form a metal interconnect system.

In summary, the present invention proposes a method of forming an opening on a semiconductor substrate, which mainly utilizes a boron nitride layer as a hard mask layer, and is combined with boron atoms of different concentrations or with a metal nitride layer to form a composite. Hard mask layer. The composite hard mask layer can have a high etching selectivity ratio and can simultaneously adjust the stress state of the dielectric layer to avoid deformation of the line. In addition, since the low dielectric constant dielectric layer and the boron nitride layer often have a problem of poor adhesion, it is also possible to selectively provide a cap layer between the dielectric layer and the boron nitride to increase The adhesion rate of the patterned hard mask layer. The invention is particularly applicable to single damascene or dual damascene processes in metal interconnect systems to avoid deformation of the trench or via.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300,400,500. . . Base

302,402,502. . . Dielectric layer

304,404,504. . . Cover

306,406,506. . . Patterned hard mask layer

308,408,508. . . Opening

310,410,510. . . Opening

407. . . Boron nitride layer

409. . . Metal nitride layer

507. . . First boron nitride layer

509. . . Second boron nitride layer

1 to 3 are schematic views showing the steps of a method of forming an opening on a semiconductor substrate in the first embodiment of the present invention.

Figure 4 is a schematic view showing the stress and boron atom concentration when boron nitride is used as a patterned hard mask layer according to the present invention.

FIG. 5 is a schematic view showing the etching rate and boron atom concentration when boron nitride is used as a patterned hard mask layer according to the present invention.

6 and 7 are schematic diagrams showing the steps of a method of forming an opening on a semiconductor substrate in a second embodiment of the present invention.

8 to 9 are schematic views showing the steps of a method of forming an opening on a semiconductor substrate in a third embodiment of the present invention.

Claims (19)

A method of forming an opening on a semiconductor substrate, comprising: providing a substrate; forming a dielectric layer and a cap layer on the substrate, wherein a ratio of a thickness of the dielectric layer to a thickness of the cap layer is substantially between 15 and 1.5; forming a patterned boron nitride layer on the cap layer; and performing an etching process, using the patterned boron nitride layer as a mask, etching the cap layer and the dielectric layer, and the cap An opening is formed in the layer and in the dielectric layer. A method of forming an opening on a semiconductor substrate as described in claim 1, wherein a ratio of boron atoms to all atoms in the patterned boron nitride layer is substantially between 50% and 80%. A method of forming an opening on a semiconductor substrate as described in claim 1, wherein a ratio of boron atoms to all atoms in the patterned boron nitride layer is substantially between 60% and 70%. A method of forming an opening on a semiconductor substrate as described in claim 1, wherein the patterned boron nitride layer has a stress of from -50 MPa to 400 MPa. A method of forming an opening on a semiconductor substrate as described in claim 1, wherein the patterned boron nitride layer has a stress of 10 MPa to 100 MPa. A method of forming an opening on a semiconductor substrate as described in claim 1, wherein the cap layer comprises tantalum nitride, hafnium oxide, tantalum carbide, niobium nitrite or hafnium oxynitride. A method of forming an opening on a semiconductor substrate as described in claim 1, wherein the dielectric layer has a dielectric constant substantially less than 3.5. A method of forming an opening on a semiconductor substrate, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a patterned composite hard mask layer on the dielectric layer, wherein the patterned composite hard layer The mask layer comprises at least: a metal nitride layer; and a boron nitride layer disposed on the boron nitride layer; and performing an etching process using the patterned composite hard mask layer A mask is formed to etch the dielectric layer and an opening is formed in the dielectric layer. The method for forming an opening on a semiconductor substrate according to claim 8 , further comprising forming a cap layer between the dielectric layer and the patterned composite hard mask layer, and in the etching process A cap layer forms the opening. A method of forming an opening on a semiconductor substrate as described in claim 8 wherein the ratio of boron atoms to all atoms in the boron nitride layer is substantially 50% to 80%. A method of forming an opening on a semiconductor substrate as described in claim 8 wherein the ratio of boron atoms to all atoms in the boron nitride layer is substantially between 60% and 70%. A method of forming an opening on a semiconductor substrate as described in claim 8 wherein the boron nitride layer has a stress of from -50 MPa to 400 MPa. A method of forming an opening on a semiconductor substrate as described in claim 8 wherein the boron nitride layer has a stress of 10 MPa to 100 MPa. A method of forming an opening on a semiconductor substrate as described in claim 8 wherein the cap layer comprises tantalum nitride, hafnium oxide, tantalum carbide, niobium nitrite or hafnium oxynitride. A method of forming an opening on a semiconductor substrate, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a patterned composite hard mask layer on the dielectric layer, wherein the patterned composite hard layer The mask layer includes at least: a first boron nitride layer; and a second boron nitride layer disposed on the first boron nitride layer, wherein the second nitrogen The concentration of boron in the boronized layer is different from the concentration of boron in the first boron nitride layer; and performing an etching process, using the patterned composite hard mask layer as a mask, etching the dielectric layer, and An opening is formed in the dielectric layer. A method of forming an opening on a semiconductor substrate as described in claim 15 wherein the concentration of boron in the second boron nitride layer is greater than the concentration of boron in the first boron nitride layer. The method for forming an opening on a semiconductor substrate as described in claim 15 , wherein a ratio of boron atoms to all atoms in the first boron nitride layer is substantially between 50% and 80%, and In the second boron nitride layer, the ratio of boron atoms to all atoms is substantially between 50% and 80%. The method of forming an opening on a semiconductor substrate as described in claim 15, wherein the first boron nitride layer has a stress of -50 MPa to 400 MPa, and the second boron nitride layer has a -50 MPa to 400 MPa. The stress. The method of forming an opening on a semiconductor substrate according to claim 15 , wherein the patterned composite hard mask layer further comprises a third boron nitride layer disposed on the second boron nitride layer, And the concentration of boron in the third boron nitride layer is greater than the concentration of boron in the second boron nitride layer.