TWI514764B - Hv multiplexer with hv switch - Google Patents

Description

High voltage multiplexer with high voltage switch

The invention relates to a high voltage multiplexer, in particular to a high voltage multiplexer with a high voltage switch.

The voltage detection system applied to the battery usually consists of a battery pack and a multiplexer for converting the high voltage of each battery in the battery pack to the required voltage to be tested. Since the voltage distortion generated by the multiplexer is not subjected to proper signal processing, the detection error of the terminal to be tested is too large, and the level of the battery voltage cannot be accurately detected.

It is a primary object of the present invention to provide a high voltage multiplexer having a high voltage switch.

A high voltage multiplexer having a high voltage switch, comprising a plurality of high voltage switches, a transconductance amplifier, a multiplexer and an arithmetic unit, each of the high voltage switches having a first gate voltage generator and a second gate a voltage generator, a current mirror and a MOS switch, the first gate voltage generator has a first voltage receiving end and a first voltage transmitting end, the second gate voltage generator has a second voltage receiving end and a a second voltage transmitting end, the current mirror is electrically connected to the first voltage receiving end and the second voltage receiving end, the MOS switch is electrically connected to the first voltage transmitting end and the second voltage transmitting end, the second voltage The voltage of the receiving end is smaller than the voltage of the first receiving end, and the gate voltage generators can control the gate voltage of the MOS switch to prevent the MOS switch from generating an overvoltage condition. The transconductance amplifier has a first operational circuit. And a second operation circuit, the first operation circuit and the second operation circuit are electrically connected to the high voltage switches, and the multiplexer is electrically connected to the first operation circuit of the transduction amplifier and the second operation Road, the computing unit electrically connected to the multiplexer. The gate voltage generator provided by each of the high voltage switches can precisely control the gate voltage of the MOS switch for a specific input voltage, so as to effectively avoid the problem that the MOS switch generates overvoltage and causes burnout. Since the overall voltage of the battery pack for the vehicle electronics is relatively high, the general process cannot be applied to the vehicle electronics, and the high-voltage switches of the present invention are manufactured by a high-voltage process, and the detection error can be less than 10 mV, so that the utility model can be effectively applied to the vehicle. Voltage detection using an electronic battery pack.

Please refer to FIG. 1 and FIG. 2 , a high voltage multiplexer 100 with a high voltage switch, which can accurately detect the voltage of a battery B, so that the detection error can be less than 10 mV, and includes a plurality of high voltage switches 110 and one. The transconductance amplifier 120 electrically connected to the high voltage switch 110, the multiplexer 130 electrically connected to the transconductance amplifier 120, the arithmetic unit 140 electrically connected to the multiplexer 130, and an electrical connection to the high voltage switch In the present embodiment, each of the high-voltage switches 110 has a power input terminal 110a and a transmission terminal 110b. The power input terminals 110a can be externally connected to a battery pack B. The transconductance amplifier 120 has a first An operation circuit 121 and a second operation circuit 122 are electrically connected to the first operation circuit 121 and the second operation circuit 122. The multiplexer 130 has a first input end 131 and a second end. The input terminal 132 and the output end 133 are electrically connected to the output end of the first operation circuit 121. The second input end 132 is electrically connected to the output end of the second operation circuit 122. The output end is electrically connected to the output end of the second operation circuit 122. 133 is electrically connected to the arithmetic unit 140, see 3, each of the high voltage switch 110 has a first gate voltage generator 111, a second gate voltage generator 112, a MOS switch 113 and a current mirror 116. The first gate voltage generator 111 has a The first voltage receiving end 111a and the first voltage transmitting end 111b, the second gate voltage generating unit 112 has a second voltage receiving end 112a and a second voltage transmitting end 112b. The current mirror 116 is electrically connected to the first a voltage receiving end 111a and the second voltage receiving end 111a, the MOS switch 113 is electrically connected to the first voltage transmitting end 111b and the second voltage transmitting end 112b, and the gate voltage generators 111, 112 can be precisely controlled The gate voltage of the MOS switch 113 prevents the MOS switch 113 from generating an overvoltage and causes burnout.

Referring to FIG. 4A, the first gate voltage generator 111 has a plurality of first diodes 111c, a first voltage dividing circuit 111d, a first MOS transistor T1, and a second MOS transistor T2. In this embodiment, the first voltage dividing circuit 111d has a first resistor 111e and a second resistor 111f. The first MOS transistor T1 has a source terminal s1 and the first voltage dividing circuit 111d. A resistor 111e and one of the first diodes 111c are electrically connected to the first voltage receiving end 111a. The gate terminal g1 of the first MOS transistor T1 is electrically connected to the first diodes 111c. One of the cathode ends, the first resistor 111e and the second resistor 111f, and one of the second MOS transistors T2 is electrically connected to the second resistor 111f of the first voltage dividing circuit 111d. The diode 111c is for protecting the gate-source voltage of the first MOS transistor T1 from being greater than 5 volts. When the first voltage receiving terminal 111a is operated at a high voltage (9.8 volts to 27 volts), the first MOS the gate transistor T1 - source across the plurality of pressure no greater than the oN voltage of the diode 111c, when V _a = V _x -4.9, In contrast, when the operation of the first voltage receiving terminal 111a At a low voltage (2 volts to 9.8 volts), the gate-source voltage across the first MOS transistor T1 is divided by the first resistor 111e and the second resistor 111f of the first voltage dividing circuit 111d. When V _a = V _x /2, when the first voltage receiving end 111a is lower than 2 volts, the voltage of V _a cannot turn on the first MOS transistor T1. Please refer to FIG. 2 and FIG. 4A. In this embodiment, the encoder 150 has a plurality of coded output terminals 151, and one of the code output terminals 151 is electrically connected to the second MOS transistor T2 of the first gate voltage generator 111. One of the gates is extreme g2.

Referring to FIG. 3 and FIG. 4B, the second gate voltage generator 112 has a plurality of second diodes 112c, a second voltage dividing circuit 112d, a third MOS transistor T3, and a fourth MOS. The transistor T4 and the third diode D3, and the high voltage switch 110 further has an inverter I. In the embodiment, the second voltage dividing circuit 112d has a third resistor 112e and a fourth resistor 112f. The anode terminal s3 of the third MOS transistor T3, the third resistor 112e of the second voltage dividing circuit 112d, and one of the second diodes 111c are electrically connected to the second voltage receiving end. 112a, a gate terminal g3 of the third MOS transistor T3 is electrically connected to one of the second diode 112c, the third resistor 112e and the fourth resistor 112f, and the fourth MOS transistor T4 One of the third resistors 112d is electrically connected to the fourth resistor 112f of the second voltage dividing circuit 112d. One anode terminal A of the third diode D3 is electrically connected to one of the third MOS transistors T3. The cathode end C of the third diode D3 is electrically connected to the MOS switch 113 and the first voltage transmitting end 111b. In this embodiment, the third MOS transistor T3 is The 汲 terminal d3 is the second voltage transmitting end 112b. Further, when the terminal voltage of the first voltage transmitting end 111b is greater than the terminal voltage of the first voltage receiving end 111a, the third diode D3 can prevent the flow. The current flowing through the first MOS transistor T1 is returned to the second gate voltage generator 112. Please refer to FIG. 2, FIG. 3 and FIG. 4B. In the embodiment, the codes of the encoder 150 are used. One of the output terminals of the output terminal 151 is electrically connected to one of the input terminals I1 of the inverter 1. The output terminal I2 of the inverter I is electrically connected to the fourth MOS of the second gate voltage generator 112. One of the gates of the transistor T4 is g4.

Referring to FIG. 3, the MOS switch 113 of each of the high voltage switches 110 has a fifth transistor 114 and a sixth transistor 115. The gate electrode 114a and the sixth transistor 115 of the fifth transistor 114 are A gate terminal 115a is electrically connected to the first voltage transmitting end 111b of the first gate voltage generator 111 and the second voltage transmitting end 112b of the second gate voltage generator 112. The power input end 110a is electrically One end of the fifth transistor 114 is connected to the anode 114b, and the transmitting end 110b is electrically connected to one of the sixth electrodes 115.

Referring to FIG. 3, the current mirror 116 of each of the high voltage switches 110 has a seventh transistor 117, an eighth transistor 118, and a fifth resistor 119. The gate electrode 117a of the seventh transistor 117 and the One terminal 117b of the seventh transistor 117 is electrically connected to one of the gate terminals 118a of the eighth transistor 118. One end of the fifth resistor 119 is electrically connected to the first voltage receiving of the first gate voltage generator 111. The other end of the fifth resistor 119 is electrically connected to the second voltage receiving end 112a of the second gate voltage generator 112 and the first terminal 118b of the eighth transistor 118. The second voltage receiving is performed. The voltage of the terminal 112a is obtained by subtracting the voltage across the fifth resistor 119 from the voltage of the first receiving terminal 111a, so that the voltage of the second voltage receiving terminal 112a is smaller than the voltage of the first receiving terminal 111a, in this embodiment. Since the current flowing through the eighth transistor 118 is nine times the current flowing through the seventh transistor 117, when the first voltage receiving end 111a is at a low voltage, the first gate voltage generator can be effectively prevented. The first voltage receiving end 111a of the 111 and the second gate voltage generator The voltage difference between the second voltage receiving terminals 112a of 112 is too small to turn on the fifth transistor 114 and the sixth transistor 115 of the MOS switch 113.

The operation of the present invention is as follows. When the high voltage switch 110 is in the off state, the code output end 151 corresponding to the encoder 150 is at a high potential, and the first gate voltage generator 111 of the high voltage switch 110 is at this time. Turning on to enable the voltage level of the first voltage receiving end 111a to be transmitted to the first voltage transmitting end 111b, so that the fifth transistor 114 of the MOS switch 113 and the gate-source span of the sixth transistor 115 When the voltage is zero, the fifth transistor 114 and the sixth transistor 115 are in a closed state. If the high voltage switch 110 is to be turned on, the code output terminal 151 corresponding to the encoder 150 exhibits a low high potential. The second gate voltage generator 112 of the high voltage switch 110 is turned on such that the level of the second voltage transmitting end 112b is equal to the level of the second voltage receiving end 112a, so the fifth transistor of the MOS switch 113 114 and the sixth transistor 115 assume an on state, such that a voltage connected to the power input terminal 110a of the battery pack B is transmitted to the transconductance amplifier 120 via the transmission end 110b, and the transduction amplifier 120 can be derived from the battery Group B's high voltage is converted to The voltage is output, and the battery voltage in the battery pack B to be measured is selected through the multiplexer 130, and finally the output voltage of the output end 133 of the multiplexer 130 is converted into a voltage to be tested via the operation unit 140. In this embodiment, the multiplexer 130 is a two-to-one multiplexer, and the computing unit 140 is a multiplier.

According to the present invention, the gate voltage generators 111 and 112 of the high voltage switch 110 can accurately control the gate voltage level of the MOS switch 113 for a specific input voltage, thereby effectively preventing the MOS switch 113 from generating an overvoltage. In addition, since the overall voltage of the battery pack for the vehicle electronics is relatively high, the general process cannot be applied to the vehicle electronics, and the high-voltage switches 110 of the present invention are manufactured by a high-voltage process, and the detection error can be low. At 10mV, it can be effectively applied to the voltage detection of battery packs for automotive electronics.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100. . . High voltage multiplexer with high voltage switch

110. . . High voltage switch

110a. . . Power input

110b. . . Transmitter

111. . . First gate voltage generator

111a. . . First voltage receiving end

111b. . . First voltage transmitting end

111c. . . First diode

111d. . . First voltage dividing circuit

111e. . . First resistance

111f. . . Second resistance

112. . . Second gate voltage generator

112a. . . Second voltage receiving end

112b. . . Second voltage transmitting end

112c. . . Second diode

112d. . . Second voltage dividing circuit

112e. . . Third resistance

112f. . . Fourth resistor

113. . . MOS switch

114. . . Fifth transistor

114a. . . Gate extreme

114b. . . Extreme

114c. . . Source extreme

115. . . Sixth transistor

115a. . . Gate extreme

115b. . . Extreme

115c. . . Source extreme

116. . . Current mirror

117. . . Seventh transistor

117a. . . Gate extreme

117b. . . Extreme

118. . . Eighth transistor

118a. . . Gate extreme

118b. . . Extreme

119. . . Fifth resistor

120. . . Transduction amplifier

121. . . First operational circuit

122. . . Second arithmetic circuit

130. . . Multiplexer

131. . . First input

132. . . Second input

133. . . Output

140. . . Arithmetic unit

150. . . Encoder

151. . . Coded output

T1. . . First MOS transistor

G1. . . Gate extreme

S1. . . Source extreme

D1. . . Extreme

T2. . . Second MOS transistor

G2. . . Gate extreme

D2. . . Extreme

T3. . . Third MOS transistor

G3. . . Gate extreme

S1. . . Source extreme

D1. . . Extreme

T4. . . Fourth MOS transistor

G4. . . Gate extreme

D4. . . Extreme

D3. . . Third diode

A. . . Anode end

C. . . Cathode end

I. . . inverter

I1. . . Input

I2. . . Output

B. . . Battery

Figure 1 is a circuit diagram of a high voltage multiplexer having a high voltage switch in accordance with an embodiment of the present invention. Figure 2 is a schematic illustration of an encoder of a high voltage multiplexer having a high voltage switch in accordance with an embodiment of the present invention. Figure 3 is a schematic illustration of a high voltage switch of a high voltage multiplexer having a high voltage switch in accordance with an embodiment of the present invention. 4A is a schematic diagram of a first gate voltage generator of the high voltage multiplexer having a high voltage switch, in accordance with an embodiment of the present invention. 4B is a schematic diagram of a second gate voltage generator of the high voltage multiplexer having a high voltage switch, in accordance with an embodiment of the present invention.

100. . . High voltage multiplexer with high voltage switch

110. . . High voltage switch

110a. . . Power input

110b. . . Transmitter

120. . . Transduction amplifier

121. . . First operational circuit

122. . . Second arithmetic circuit

130. . . Multiplexer

131. . . First input

132. . . Second input

133. . . Output

140. . . Arithmetic unit

B. . . Battery

Claims (10)

A high voltage multiplexer having a high voltage switch, comprising: a plurality of high voltage switches, each of the high voltage switches having a first gate voltage generator, a second gate voltage generator, a current mirror and a MOS switch The first gate voltage generator has a first voltage receiving end and a first voltage transmitting end. The second gate voltage generator has a second voltage receiving end and a second voltage transmitting end. The current mirror is electrically connected to the current The first voltage receiving end and the second voltage receiving end are electrically connected to the first voltage transmitting end and the second voltage transmitting end, and the voltage of the second voltage receiving end is smaller than the voltage of the first receiving end, The gate voltage generator can control the gate voltage of the MOS switch to prevent overvoltage of the MOS switch; a transconductance amplifier having a first operation circuit and a second operation circuit, the first operation The circuit and the second operational circuit are electrically connected to the high voltage switches; a multiplexer electrically connected to the first operational circuit and the second operational circuit; and an arithmetic unit Connected to the multiplexer. The high voltage multiplexer having a high voltage switch according to claim 1, wherein the first gate voltage generator has at least one first diode, a first voltage dividing circuit, and a first MOS power a first MOS transistor, the first divide circuit and the first MOS transistor are electrically connected to the first voltage receiving end, and the second MOS transistor is electrically connected to the first MOS transistor The first voltage divider circuit. The high voltage multiplexer having a high voltage switch according to claim 2, wherein the first voltage dividing circuit has a first resistor and a second resistor, and one of the first MOS transistors has a source terminal. The first resistor and one of the first diodes are electrically connected to the first voltage receiving end, and one of the first MOS transistors is electrically connected to one of the first diodes, the first The resistor and the second resistor, one of the second MOS transistors is electrically connected to the second resistor. The high voltage multiplexer having a high voltage switch according to claim 1, wherein the second gate voltage generator has at least one second diode, a second voltage dividing circuit, and a third MOS power a second MOS transistor, the second MOS transistor is electrically connected to the second MOS transistor, and the fourth MOS transistor is electrically connected to the second MOS transistor The second voltage dividing circuit. The high voltage multiplexer having a high voltage switch according to claim 4, wherein the second voltage dividing circuit has a third resistor and a fourth resistor, and one of the third MOS transistors has a source terminal. The third resistor and one of the anode ends of the second diode are electrically connected to the second voltage receiving end, and one of the third MOS transistors is electrically connected to one of the cathode ends of the second diode, and the third The resistor and the fourth resistor, one of the fourth MOS transistors is electrically connected to the fourth resistor. The high voltage multiplexer having a high voltage switch according to claim 4, wherein the second gate voltage generator further has a third diode, and the anode terminal of the third diode is electrically connected to the anode One of the third MOS transistors is electrically connected to the MOS switch and the first voltage transmitting end, and the second terminal of the third MOS transistor is the second voltage Transmitter. A high voltage multiplexer having a high voltage switch according to claim 2, further comprising an encoder having a plurality of code output terminals, wherein one of the code output terminals is electrically connected One of the gate terminals of the second MOS transistor of the first gate voltage generator. A high voltage multiplexer having a high voltage switch according to claim 4, further comprising an encoder, the high voltage switch further having an inverter, the encoder having a plurality of code outputs, the code outputs One of the output terminals of the inverter is electrically connected to one of the input terminals of the inverter, and one of the output terminals of the inverter is electrically connected to one of the gate terminals of the fourth MOS transistor of the second gate voltage generator. The high voltage multiplexer having a high voltage switch according to claim 1, wherein each of the high voltage switches has a power input end and a transmitting end, and the MOS switch has a fifth transistor and a sixth transistor. One gate terminal of the fifth transistor and one gate terminal of the sixth transistor are electrically connected to the first voltage transmitting end of the first gate voltage generator and the second terminal of the second gate voltage generator And a voltage transmitting end electrically connected to one of the fifth transistors of the fifth transistor, the transmitting end being electrically connected to one of the terminals of the sixth transistor. The high voltage multiplexer having a high voltage switch according to claim 1, wherein the current mirror has a seventh transistor, an eighth transistor, and a fifth resistor, and the seventh transistor is one of the terminals And one of the gates of the seventh transistor is electrically connected to one of the gate terminals of the eighth transistor, and one end of the fifth resistor is electrically connected to the first voltage receiving end of the first gate voltage generator, the first The other end of the fifth resistor is electrically connected to the second voltage receiving end of the second gate voltage generator and one of the eighth transistors.