TWI514764B - Hv multiplexer with hv switch - Google Patents
Hv multiplexer with hv switch Download PDFInfo
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- TWI514764B TWI514764B TW102113855A TW102113855A TWI514764B TW I514764 B TWI514764 B TW I514764B TW 102113855 A TW102113855 A TW 102113855A TW 102113855 A TW102113855 A TW 102113855A TW I514764 B TWI514764 B TW I514764B
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Description
本發明有關於一種高壓多工器,特別有關於一種具有高壓開關之高壓多工器。The invention relates to a high voltage multiplexer, in particular to a high voltage multiplexer with a high voltage switch.
應用於電池之電壓偵測系統通常由一電池組及一多工器所組成,該多工器用以將該電池組中的每一顆電池的高電壓轉換為所需之待測端電壓,惟,由於未經過適當之訊號處理,該多工器所產生之電壓失真(voltage distortion)將使得待測端之偵測誤差過大,而無法精確偵測電池電壓的準位。The voltage detection system applied to the battery usually consists of a battery pack and a multiplexer for converting the high voltage of each battery in the battery pack to the required voltage to be tested. Since the voltage distortion generated by the multiplexer is not subjected to proper signal processing, the detection error of the terminal to be tested is too large, and the level of the battery voltage cannot be accurately detected.
本發明之主要目的在於提供一種具有高壓開關之高壓多工器。It is a primary object of the present invention to provide a high voltage multiplexer having a high voltage switch.
一種具有高壓開關之高壓多工器,其包含複數個高壓開關、一轉導放大器、一多工器及一運算單元,各該高壓開關具有一第一閘極電壓產生器、一第二閘極電壓產生器、一電流鏡及一MOS開關,該第一閘極電壓產生器具有一第一電壓接收端及一第一電壓傳送端,該第二閘極電壓產生器具有一第二電壓接收端及一第二電壓傳送端,該電流鏡電性連接該第一電壓接收端及該第二電壓接收端,該MOS開關電性連接該第一電壓傳送端及該第二電壓傳送端,該第二電壓接收端之電壓小於該第一接收端之電壓,該些閘極電壓產生器可控制該MOS開關之閘極電壓以防止該MOS開關產生過壓之情形,該轉導放大器具有一第一運算電路及一第二運算電路,該第一運算電路及該第二運算電路電性連接該些高壓開關,該多工器電性連接該轉導放大器之該第一運算電路及該第二運算電路,該運算單元電性連接該多工器。本發明藉由各該高壓開關所具備之閘極電壓產生器,能針對特定的輸入電壓精確控制該MOS開關的閘極電壓,以有效避免該MOS開關產生過壓而導致燒毀的問題,此外,由於車用電子之電池組的整體電壓相當高,因此一般製程無法應用於車用電子,而本案之該些高壓開關以高壓製程製作,並且偵測誤差可低於10mV,因此可有效應用於車用電子之電池組的電壓偵測。A high voltage multiplexer having a high voltage switch, comprising a plurality of high voltage switches, a transconductance amplifier, a multiplexer and an arithmetic unit, each of the high voltage switches having a first gate voltage generator and a second gate a voltage generator, a current mirror and a MOS switch, the first gate voltage generator has a first voltage receiving end and a first voltage transmitting end, the second gate voltage generator has a second voltage receiving end and a a second voltage transmitting end, the current mirror is electrically connected to the first voltage receiving end and the second voltage receiving end, the MOS switch is electrically connected to the first voltage transmitting end and the second voltage transmitting end, the second voltage The voltage of the receiving end is smaller than the voltage of the first receiving end, and the gate voltage generators can control the gate voltage of the MOS switch to prevent the MOS switch from generating an overvoltage condition. The transconductance amplifier has a first operational circuit. And a second operation circuit, the first operation circuit and the second operation circuit are electrically connected to the high voltage switches, and the multiplexer is electrically connected to the first operation circuit of the transduction amplifier and the second operation Road, the computing unit electrically connected to the multiplexer. The gate voltage generator provided by each of the high voltage switches can precisely control the gate voltage of the MOS switch for a specific input voltage, so as to effectively avoid the problem that the MOS switch generates overvoltage and causes burnout. Since the overall voltage of the battery pack for the vehicle electronics is relatively high, the general process cannot be applied to the vehicle electronics, and the high-voltage switches of the present invention are manufactured by a high-voltage process, and the detection error can be less than 10 mV, so that the utility model can be effectively applied to the vehicle. Voltage detection using an electronic battery pack.
請參閱第1圖及第2圖,一種具有高壓開關之高壓多工器100,其可精確偵測一電池組B之電壓,使偵測誤差可小於10mV,其包含複數個高壓開關110、一電性連接該些高壓開關110之轉導放大器120、一電性連接該轉導放大器120之多工器130、一電性連接該多工器130之運算單元140及一電性連接該高壓開關110之編碼器150,在本實施例中,各該高壓開關110具有一電力輸入端110a及一傳送端110b,該些電力輸入端110a可外接一電池組B,該轉導放大器120具有一第一運算電路121及一第二運算電路122,各該傳送端110b電性連接該第一運算電路121及該第二運算電路122,該多工器130具有一第一輸入端131、一第二輸入端132及一輸出端133,該第一輸入端131電性連接該第一運算電路121之輸出端,該第二輸入端132電性連接該第二運算電路122之輸出端,該輸出端133電性連接該運算單元140,請參閱第3圖,各該高壓開關110具有一第一閘極電壓產生器111、一第二閘極電壓產生器112、一MOS開關113及一電流鏡116,該第一閘極電壓產生器111具有一第一電壓接收端111a及一第一電壓傳送端111b,該第二閘極電壓產生器112具有一第二電壓接收端112a及一第二電壓傳送端112b,該電流鏡116電性連接該第一電壓接收端111a及該第二電壓接收端111a,該MOS開關113電性連接該第一電壓傳送端111b及該第二電壓傳送端112b,該些閘極電壓產生器111、112可精確控制該MOS開關113之閘極電壓以防止該MOS開關113產生過壓而導致燒毀之情形。Please refer to FIG. 1 and FIG. 2 , a high voltage multiplexer 100 with a high voltage switch, which can accurately detect the voltage of a battery B, so that the detection error can be less than 10 mV, and includes a plurality of high voltage switches 110 and one. The transconductance amplifier 120 electrically connected to the high voltage switch 110, the multiplexer 130 electrically connected to the transconductance amplifier 120, the arithmetic unit 140 electrically connected to the multiplexer 130, and an electrical connection to the high voltage switch In the present embodiment, each of the high-voltage switches 110 has a power input terminal 110a and a transmission terminal 110b. The power input terminals 110a can be externally connected to a battery pack B. The transconductance amplifier 120 has a first An operation circuit 121 and a second operation circuit 122 are electrically connected to the first operation circuit 121 and the second operation circuit 122. The multiplexer 130 has a first input end 131 and a second end. The input terminal 132 and the output end 133 are electrically connected to the output end of the first operation circuit 121. The second input end 132 is electrically connected to the output end of the second operation circuit 122. The output end is electrically connected to the output end of the second operation circuit 122. 133 is electrically connected to the arithmetic unit 140, see 3, each of the high voltage switch 110 has a first gate voltage generator 111, a second gate voltage generator 112, a MOS switch 113 and a current mirror 116. The first gate voltage generator 111 has a The first voltage receiving end 111a and the first voltage transmitting end 111b, the second gate voltage generating unit 112 has a second voltage receiving end 112a and a second voltage transmitting end 112b. The current mirror 116 is electrically connected to the first a voltage receiving end 111a and the second voltage receiving end 111a, the MOS switch 113 is electrically connected to the first voltage transmitting end 111b and the second voltage transmitting end 112b, and the gate voltage generators 111, 112 can be precisely controlled The gate voltage of the MOS switch 113 prevents the MOS switch 113 from generating an overvoltage and causes burnout.
請參閱第4A圖,該第一閘極電壓產生器111具有複數個第一二極體111c、一第一分壓電路111d、一第一MOS電晶體T1及一第二MOS電晶體T2,在本實施例中,第一分壓電路111d具有一第一電阻111e及一第二電阻111f,該第一MOS電晶體T1之一源極端s1、該第一分壓電路111d之該第一電阻111e及該些第一二極體111c中之一陽極端電性連接該第一電壓接收端111a,該第一MOS電晶體T1之一閘極端g1電性連接該些第一二極體111c中之一陰極端、該第一電阻111e及該第二電阻111f,該第二MOS電晶體T2之一汲極端d2電性連接該第一分壓電路111d之該第二電阻111f,該些二極體111c用以保護該第一MOS電晶體T1之閘-源極跨壓不大於5伏,當該第一電壓接收端111a操作於高壓(9.8伏至27伏)時,該第一MOS電晶體T1之閘-源極跨壓不大於該些二極體111c之導通電壓,此時Va =Vx -4.9,相對地,當該第一電壓接收端111a操作於低壓(2伏至9.8伏)時,該第一MOS電晶體T1之閘-源極跨壓由該第一分壓電路111d之該第一電阻111e及該第二電阻111f的分壓所產生,此時Va =Vx /2,當該第一電壓接收端111a低於2伏時,Va 之電壓無法導通該第一MOS電晶體T1,請參閱第2圖及第4A圖,在本實施例中,該編碼器150具有複數個編碼輸出端151,該些編碼輸出端151之其中一編碼輸出端電性連接該第一閘極電壓產生器111之該第二MOS電晶體T2之一閘極端g2。Referring to FIG. 4A, the first gate voltage generator 111 has a plurality of first diodes 111c, a first voltage dividing circuit 111d, a first MOS transistor T1, and a second MOS transistor T2. In this embodiment, the first voltage dividing circuit 111d has a first resistor 111e and a second resistor 111f. The first MOS transistor T1 has a source terminal s1 and the first voltage dividing circuit 111d. A resistor 111e and one of the first diodes 111c are electrically connected to the first voltage receiving end 111a. The gate terminal g1 of the first MOS transistor T1 is electrically connected to the first diodes 111c. One of the cathode ends, the first resistor 111e and the second resistor 111f, and one of the second MOS transistors T2 is electrically connected to the second resistor 111f of the first voltage dividing circuit 111d. The diode 111c is for protecting the gate-source voltage of the first MOS transistor T1 from being greater than 5 volts. When the first voltage receiving terminal 111a is operated at a high voltage (9.8 volts to 27 volts), the first MOS the gate transistor T1 - source across the plurality of pressure no greater than the oN voltage of the diode 111c, when V a = V x -4.9, In contrast, when the operation of the first voltage receiving terminal 111a At a low voltage (2 volts to 9.8 volts), the gate-source voltage across the first MOS transistor T1 is divided by the first resistor 111e and the second resistor 111f of the first voltage dividing circuit 111d. When V a = V x /2, when the first voltage receiving end 111a is lower than 2 volts, the voltage of V a cannot turn on the first MOS transistor T1. Please refer to FIG. 2 and FIG. 4A. In this embodiment, the encoder 150 has a plurality of coded output terminals 151, and one of the code output terminals 151 is electrically connected to the second MOS transistor T2 of the first gate voltage generator 111. One of the gates is extreme g2.
請參閱第3圖及第4B圖,該第二閘極電壓產生器112具有複數個第二二極體112c、一第二分壓電路112d、一第三MOS電晶體T3、一第四MOS電晶體T4及一第三二極體D3,且該高壓開關110另具有一反相器I,在本實施例中,第二分壓電路112d具有一第三電阻112e及一第四電阻112f,該第三MOS電晶體T3之一源極端s3、該第二分壓電路112d之該第三電阻112e及該些第二二極體111c中之一陽極端電性連接該第二電壓接收端112a,該第三MOS電晶體T3之一閘極端g3電性連接該些第二二極體112c中之一陰極端、該第三電阻112e及該第四電阻112f,該第四MOS電晶體T4之一汲極端d4電性連接該第二分壓電路112d之該第四電阻112f,該第三二極體D3之一陽極端A電性連接該第三MOS電晶體T3之一汲極端d3,該第三二極體D3之一陰極端C電性連接該MOS開關113及該第一電壓傳送端111b,在本實施例中,該第三MOS電晶體T3之該汲極端d3即為該第二電壓傳送端112b,此外,當該第一電壓傳送端111b之端電壓大於該第一電壓接收端111a之端電壓時,該第三二極體D3可防止流經該第一MOS電晶體T1之電流回流至該第二閘極電壓產生器112,請參閱第2圖、第3圖及第4B圖,在本實施例中,該編碼器150之該些編碼輸出端151之其中一編碼輸出端電性連接該反相器I之一輸入端I1,該反相器I之一輸出端I2電性連接該第二閘極電壓產生器112之該第四MOS電晶體T4之一閘極端g4。Referring to FIG. 3 and FIG. 4B, the second gate voltage generator 112 has a plurality of second diodes 112c, a second voltage dividing circuit 112d, a third MOS transistor T3, and a fourth MOS. The transistor T4 and the third diode D3, and the high voltage switch 110 further has an inverter I. In the embodiment, the second voltage dividing circuit 112d has a third resistor 112e and a fourth resistor 112f. The anode terminal s3 of the third MOS transistor T3, the third resistor 112e of the second voltage dividing circuit 112d, and one of the second diodes 111c are electrically connected to the second voltage receiving end. 112a, a gate terminal g3 of the third MOS transistor T3 is electrically connected to one of the second diode 112c, the third resistor 112e and the fourth resistor 112f, and the fourth MOS transistor T4 One of the third resistors 112d is electrically connected to the fourth resistor 112f of the second voltage dividing circuit 112d. One anode terminal A of the third diode D3 is electrically connected to one of the third MOS transistors T3. The cathode end C of the third diode D3 is electrically connected to the MOS switch 113 and the first voltage transmitting end 111b. In this embodiment, the third MOS transistor T3 is The 汲 terminal d3 is the second voltage transmitting end 112b. Further, when the terminal voltage of the first voltage transmitting end 111b is greater than the terminal voltage of the first voltage receiving end 111a, the third diode D3 can prevent the flow. The current flowing through the first MOS transistor T1 is returned to the second gate voltage generator 112. Please refer to FIG. 2, FIG. 3 and FIG. 4B. In the embodiment, the codes of the encoder 150 are used. One of the output terminals of the output terminal 151 is electrically connected to one of the input terminals I1 of the inverter 1. The output terminal I2 of the inverter I is electrically connected to the fourth MOS of the second gate voltage generator 112. One of the gates of the transistor T4 is g4.
請參閱第3圖,各該高壓開關110之該MOS開關113具有一第五電晶體114及一第六電晶體115,該第五電晶體114之一閘極端114a及該第六電晶體115之一閘極端115a電性連接該第一閘極電壓產生器111之該第一電壓傳送端111b及該第二閘極電壓產生器112之該第二電壓傳送端112b,該電力輸入端110a電性連接該第五電晶體114之一汲極端114b,該傳送端110b電性連接該第六電晶體115之一汲極端115b。Referring to FIG. 3, the MOS switch 113 of each of the high voltage switches 110 has a fifth transistor 114 and a sixth transistor 115. The gate electrode 114a and the sixth transistor 115 of the fifth transistor 114 are A gate terminal 115a is electrically connected to the first voltage transmitting end 111b of the first gate voltage generator 111 and the second voltage transmitting end 112b of the second gate voltage generator 112. The power input end 110a is electrically One end of the fifth transistor 114 is connected to the anode 114b, and the transmitting end 110b is electrically connected to one of the sixth electrodes 115.
請參閱第3圖,各該高壓開關110之該電流鏡116具有一第七電晶體117、一第八電晶體118及一第五電阻119,該第七電晶體117之一閘極端117a及該第七電晶體117之一汲極端117b電性連接該第八電晶體118之一閘極端118a,該第五電阻119之一端電性連接該第一閘極電壓產生器111之該第一電壓接收端111a,且該第五電阻119之另一端電性連接該第二閘極電壓產生器112之該第二電壓接收端112a及該第八電晶體118之一汲極端118b,該第二電壓接收端112a之電壓為該第一接收端111a之電壓扣除該第五電阻119之跨壓而得,故該第二電壓接收端112a之電壓小於該第一接收端111a之電壓,在本實施例中,由於流經該第八電晶體118之電流為流經該第七電晶體117之電流的九倍,當該第一電壓接收端111a處於低壓時,可有效防止該第一閘極電壓產生器111之該第一電壓接收端111a與該第二閘極電壓產生器112之該第二電壓接收端112a之間的電壓差過小而無法開啟該MOS開關113之該第五電晶體114及該第六電晶體115。Referring to FIG. 3, the current mirror 116 of each of the high voltage switches 110 has a seventh transistor 117, an eighth transistor 118, and a fifth resistor 119. The gate electrode 117a of the seventh transistor 117 and the One terminal 117b of the seventh transistor 117 is electrically connected to one of the gate terminals 118a of the eighth transistor 118. One end of the fifth resistor 119 is electrically connected to the first voltage receiving of the first gate voltage generator 111. The other end of the fifth resistor 119 is electrically connected to the second voltage receiving end 112a of the second gate voltage generator 112 and the first terminal 118b of the eighth transistor 118. The second voltage receiving is performed. The voltage of the terminal 112a is obtained by subtracting the voltage across the fifth resistor 119 from the voltage of the first receiving terminal 111a, so that the voltage of the second voltage receiving terminal 112a is smaller than the voltage of the first receiving terminal 111a, in this embodiment. Since the current flowing through the eighth transistor 118 is nine times the current flowing through the seventh transistor 117, when the first voltage receiving end 111a is at a low voltage, the first gate voltage generator can be effectively prevented. The first voltage receiving end 111a of the 111 and the second gate voltage generator The voltage difference between the second voltage receiving terminals 112a of 112 is too small to turn on the fifth transistor 114 and the sixth transistor 115 of the MOS switch 113.
有關本發明之作動敘述如下,當該高壓開關110處於關閉狀態時,該編碼器150所對應之該編碼輸出端151為高電位,此時該高壓開關110之該第一閘極電壓產生器111開啟而使該第一電壓接收端111a的電壓準位能傳遞至該第一電壓傳送端111b,故該MOS開關113之該第五電晶體114及該第六電晶體115的閘-源極跨壓為零,處該第五電晶體114及該第六電晶體115於關閉狀態,若欲開啟該高壓開關110,該編碼器150所對應之該編碼輸出端151呈現為低高電位,此時該高壓開關110之該第二閘極電壓產生器112開啟而使得該第二電壓傳送端112b的準位等於該第二電壓接收端112a的準位,故該MOS開關113之該第五電晶體114及該第六電晶體115呈現導通狀態,使得連接至該電池組B之該電力輸入端110a的電壓經由該傳送端110b傳遞至該轉導放大器120,該轉導放大器120可將來自該電池組B的高電壓轉換為低電壓輸出,並經由該多工器130選擇欲量測之該電池組B中的電池電壓,最後經由該運算單元140將該多工器130之該輸出端133的輸出電壓轉換為一待測電壓,在本實施例中,該多工器130為二對一多工器,該運算單元140為一乘法器。The operation of the present invention is as follows. When the high voltage switch 110 is in the off state, the code output end 151 corresponding to the encoder 150 is at a high potential, and the first gate voltage generator 111 of the high voltage switch 110 is at this time. Turning on to enable the voltage level of the first voltage receiving end 111a to be transmitted to the first voltage transmitting end 111b, so that the fifth transistor 114 of the MOS switch 113 and the gate-source span of the sixth transistor 115 When the voltage is zero, the fifth transistor 114 and the sixth transistor 115 are in a closed state. If the high voltage switch 110 is to be turned on, the code output terminal 151 corresponding to the encoder 150 exhibits a low high potential. The second gate voltage generator 112 of the high voltage switch 110 is turned on such that the level of the second voltage transmitting end 112b is equal to the level of the second voltage receiving end 112a, so the fifth transistor of the MOS switch 113 114 and the sixth transistor 115 assume an on state, such that a voltage connected to the power input terminal 110a of the battery pack B is transmitted to the transconductance amplifier 120 via the transmission end 110b, and the transduction amplifier 120 can be derived from the battery Group B's high voltage is converted to The voltage is output, and the battery voltage in the battery pack B to be measured is selected through the multiplexer 130, and finally the output voltage of the output end 133 of the multiplexer 130 is converted into a voltage to be tested via the operation unit 140. In this embodiment, the multiplexer 130 is a two-to-one multiplexer, and the computing unit 140 is a multiplier.
本發明藉由各該高壓開關110所具備之閘極電壓產生器111、112,能針對特定的輸入電壓而精確控制該MOS開關113的閘極電壓準位,有效避免該MOS開關113產生過壓而導致燒毀的問題,此外,由於車用電子之電池組的整體電壓相當高,因此一般製程無法應用於車用電子,而本案之該些高壓開關110以高壓製程製作,並且偵測誤差可低於10mV,因此可有效應用於車用電子之電池組的電壓偵測。According to the present invention, the gate voltage generators 111 and 112 of the high voltage switch 110 can accurately control the gate voltage level of the MOS switch 113 for a specific input voltage, thereby effectively preventing the MOS switch 113 from generating an overvoltage. In addition, since the overall voltage of the battery pack for the vehicle electronics is relatively high, the general process cannot be applied to the vehicle electronics, and the high-voltage switches 110 of the present invention are manufactured by a high-voltage process, and the detection error can be low. At 10mV, it can be effectively applied to the voltage detection of battery packs for automotive electronics.
本發明之保護範圍當視後附之申請專利範圍所界定者為準,任何熟知此項技藝者,在不脫離本發明之精神和範圍內所作之任何變化與修改,均屬於本發明之保護範圍。The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
100...具有高壓開關之高壓多工器100. . . High voltage multiplexer with high voltage switch
110...高壓開關110. . . High voltage switch
110a...電力輸入端110a. . . Power input
110b...傳送端110b. . . Transmitter
111...第一閘極電壓產生器111. . . First gate voltage generator
111a...第一電壓接收端111a. . . First voltage receiving end
111b...第一電壓傳送端111b. . . First voltage transmitting end
111c...第一二極體111c. . . First diode
111d...第一分壓電路111d. . . First voltage dividing circuit
111e...第一電阻111e. . . First resistance
111f...第二電阻111f. . . Second resistance
112...第二閘極電壓產生器112. . . Second gate voltage generator
112a...第二電壓接收端112a. . . Second voltage receiving end
112b...第二電壓傳送端112b. . . Second voltage transmitting end
112c...第二二極體112c. . . Second diode
112d...第二分壓電路112d. . . Second voltage dividing circuit
112e...第三電阻112e. . . Third resistance
112f...第四電阻112f. . . Fourth resistor
113...MOS開關113. . . MOS switch
114...第五電晶體114. . . Fifth transistor
114a...閘極端114a. . . Gate extreme
114b...汲極端114b. . . Extreme
114c...源極端114c. . . Source extreme
115...第六電晶體115. . . Sixth transistor
115a...閘極端115a. . . Gate extreme
115b...汲極端115b. . . Extreme
115c...源極端115c. . . Source extreme
116...電流鏡116. . . Current mirror
117...第七電晶體117. . . Seventh transistor
117a...閘極端117a. . . Gate extreme
117b...汲極端117b. . . Extreme
118...第八電晶體118. . . Eighth transistor
118a...閘極端118a. . . Gate extreme
118b...汲極端118b. . . Extreme
119...第五電阻119. . . Fifth resistor
120...轉導放大器120. . . Transduction amplifier
121...第一運算電路121. . . First operational circuit
122...第二運算電路122. . . Second arithmetic circuit
130...多工器130. . . Multiplexer
131...第一輸入端131. . . First input
132...第二輸入端132. . . Second input
133...輸出端133. . . Output
140...運算單元140. . . Arithmetic unit
150...編碼器150. . . Encoder
151...編碼輸出端151. . . Coded output
T1...第一MOS電晶體T1. . . First MOS transistor
g1...閘極端G1. . . Gate extreme
s1...源極端S1. . . Source extreme
d1...汲極端D1. . . Extreme
T2...第二MOS電晶體T2. . . Second MOS transistor
g2...閘極端G2. . . Gate extreme
d2...汲極端D2. . . Extreme
T3...第三MOS電晶體T3. . . Third MOS transistor
g3...閘極端G3. . . Gate extreme
s1...源極端S1. . . Source extreme
d1...汲極端D1. . . Extreme
T4...第四MOS電晶體T4. . . Fourth MOS transistor
g4...閘極端G4. . . Gate extreme
d4...汲極端D4. . . Extreme
D3...第三二極體D3. . . Third diode
A...陽極端A. . . Anode end
C...陰極端C. . . Cathode end
I...反相器I. . . inverter
I1...輸入端I1. . . Input
I2...輸出端I2. . . Output
B...電池組B. . . Battery
第1圖:依據本發明之一實施例,一種具有高壓開關之高壓多工器之電路圖。第2圖:依據本發明之一實施例,該具有高壓開關之高壓多工器之編碼器的示意圖。第3圖:依據本發明之一實施例,該具有高壓開關之高壓多工器之高壓開關的示意圖。第4A圖:依據本發明之一實施例,該具有高壓開關之高壓多工器之第一閘極電壓產生器的示意圖。第4B圖:依據本發明之一實施例,該具有高壓開關之高壓多工器之第二閘極電壓產生器的示意圖。Figure 1 is a circuit diagram of a high voltage multiplexer having a high voltage switch in accordance with an embodiment of the present invention. Figure 2 is a schematic illustration of an encoder of a high voltage multiplexer having a high voltage switch in accordance with an embodiment of the present invention. Figure 3 is a schematic illustration of a high voltage switch of a high voltage multiplexer having a high voltage switch in accordance with an embodiment of the present invention. 4A is a schematic diagram of a first gate voltage generator of the high voltage multiplexer having a high voltage switch, in accordance with an embodiment of the present invention. 4B is a schematic diagram of a second gate voltage generator of the high voltage multiplexer having a high voltage switch, in accordance with an embodiment of the present invention.
100...具有高壓開關之高壓多工器100. . . High voltage multiplexer with high voltage switch
110...高壓開關110. . . High voltage switch
110a...電力輸入端110a. . . Power input
110b...傳送端110b. . . Transmitter
120...轉導放大器120. . . Transduction amplifier
121...第一運算電路121. . . First operational circuit
122...第二運算電路122. . . Second arithmetic circuit
130...多工器130. . . Multiplexer
131...第一輸入端131. . . First input
132...第二輸入端132. . . Second input
133...輸出端133. . . Output
140...運算單元140. . . Arithmetic unit
B...電池組B. . . Battery
Claims (10)
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5696459A (en) * | 1994-01-24 | 1997-12-09 | Arithmos, Inc. | High voltage electronic amplifiers |
TW200401240A (en) * | 2002-07-05 | 2004-01-16 | Toshiba Lighting & Technology | Image projection displaying apparatus in single plate design |
TW200832877A (en) * | 2007-01-23 | 2008-08-01 | Etron Technology Inc | A new charge pump circuit for high voltage generation |
US8063624B2 (en) * | 2009-03-12 | 2011-11-22 | Freescale Semiconductor, Inc. | High side high voltage switch with over current and over voltage protection |
CN102064678B (en) * | 2010-11-29 | 2013-01-23 | Bcd半导体制造有限公司 | Gate drive circuit of switch power supply |
-
2013
- 2013-04-18 TW TW102113855A patent/TWI514764B/en not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5696459A (en) * | 1994-01-24 | 1997-12-09 | Arithmos, Inc. | High voltage electronic amplifiers |
TW200401240A (en) * | 2002-07-05 | 2004-01-16 | Toshiba Lighting & Technology | Image projection displaying apparatus in single plate design |
TW200832877A (en) * | 2007-01-23 | 2008-08-01 | Etron Technology Inc | A new charge pump circuit for high voltage generation |
US8063624B2 (en) * | 2009-03-12 | 2011-11-22 | Freescale Semiconductor, Inc. | High side high voltage switch with over current and over voltage protection |
CN102064678B (en) * | 2010-11-29 | 2013-01-23 | Bcd半导体制造有限公司 | Gate drive circuit of switch power supply |
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