TWI514481B - Method for designing stressor pattern - Google Patents

Description

Design method of stress layer pattern

The present invention relates to a method of designing a pattern of a semiconductor element, and more particularly to a method of designing a pattern of a stress layer.

At present, the industry proposes a method for fabricating a source/drain region of a MOS transistor by using a stress layer of germanium (SiGe), which controls the stress applied to the channel region by a stress layer to increase electrons. And the mobility of the holes, thereby improving the performance of the semiconductor components.

However, when a SiGe pattern is designed by a computer-aided logic operation, if a SiGe pattern applied to a P-type MOS transistor and an active region pattern of an N-type NMOS transistor are used, The distance is too small. In the actual fabrication of a complementary CMOS transistor, the patterned photoresist layer that should cover the active region of the NMOS transistor cannot be completely covered due to process variation. The active region of the NMOS transistor is exposed, and the active region of a portion of the NMOS transistor is exposed.

1 is a cross-sectional view of a conventional CMOS transistor.

Referring to FIG. 1, the CMOS transistor includes a PMOS transistor 10 and an NMOS transistor 18. The patterned photoresist layer 16 that should otherwise cover the active region 20 of the NMOS transistor 18 does not completely cover the active region of the NMOS transistor, exposing the active region of a portion of the NMOS transistor. Therefore, in the deposition process for forming the SiGe layer 14, the photoresist layer 16 is patterned. An exposed defect 22 of SiGe is grown around the active region 20 where the NMOS transistor 18 is exposed, thereby reducing the electrical performance of the NMOS transistor 18. In addition, when a partial overlap occurs between the SiGe pattern and the dummy diffusion pattern, a protruding defect as described above is also generated around the dummy diffusion region.

The present invention provides a method of designing a stress layer pattern that prevents generation of protruding defects around the active region.

The present invention provides another method of designing a stress layer pattern that avoids the formation of protruding defects around the dummy diffusion region.

The present invention provides a method of designing a stress layer pattern in which a stress layer pattern is used to form a source/drain region of a second type of MOS transistor. The above method includes the following steps. First, a first distance between the boundary of the stress layer pattern and the first active region pattern of the first type MOS transistor is calculated. Then, when the first distance is less than the safety distance, the stress layer pattern is reduced such that the first distance is at least equal to the safety distance.

According to an embodiment of the present invention, in the method for designing a stress layer pattern, the stress layer pattern and the first active region pattern are separated from each other, for example.

According to an embodiment of the present invention, in the above method of designing the stress layer pattern, the safety distance is determined, for example, by the process capability of the applied process generation.

According to an embodiment of the present invention, in the stress layer pattern described above In the design method, the design rule of the above method includes causing the second distance between the boundary of the stress layer pattern and the second active region pattern of the second type MOS transistor to be at least equal to the safety distance.

According to an embodiment of the present invention, in the method for designing the stress layer pattern, the second active region pattern is, for example, located inside the stress layer pattern.

According to an embodiment of the present invention, in the above method for designing a stress layer pattern, the design rule of the above method includes making the width of the stress layer pattern at least equal to the minimum stress layer width that can be defined by the applied process generation.

According to an embodiment of the present invention, in the method for designing the stress layer pattern, the method further includes reducing the stress layer pattern when the first distance is equal to the safety distance, such that the first distance is greater than the safety distance.

The present invention proposes another method of designing a stress layer pattern in which a stress layer pattern is used to form a source/drain region of a MOS transistor. The above method includes the following steps. First, a dummy dummy pattern partially overlapping the initial stress layer pattern is found. Next, an auxiliary stress layer pattern that completely covers the virtual diffusion pattern is calculated. Then, the initial stress layer pattern and the auxiliary stress layer pattern are combined to obtain a stress layer pattern.

According to another embodiment of the present invention, in the above method for designing a stress layer pattern, when the initial stress layer pattern partially overlaps the plurality of dummy diffusion patterns, a plurality of auxiliary stress layer patterns covering the dummy diffusion pattern are calculated. The above method further includes merging adjacent auxiliary stress layer patterns.

According to another embodiment of the present invention, in the above method for designing a stress layer pattern, the step of merging adjacent auxiliary stress layer patterns is And the step of initial stress layer pattern and auxiliary stress layer pattern is performed.

Based on the above, in the design method of the stress layer pattern proposed by the present invention, since the first distance between the boundary of the stress layer pattern and the first active region pattern of the first type MOS transistor is at least equal to the safety distance, With a large process margin, it is possible to prevent the formation of a protruding defect around the first active region of the first type MOS transistor due to process variation.

Further, in the design method of the stress layer pattern proposed by the present invention, since the stress layer pattern completely covers the dummy diffusion pattern, it is possible to avoid formation of protruding defects around the dummy diffusion region.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 2A to FIG. 2B are schematic diagrams showing a design flow of a stress layer pattern according to an embodiment of the present invention.

First, referring to FIG. 2A, the semiconductor device pattern 100 includes a first active region pattern 102 of a first type of gold oxide semiconductor, a second active region pattern 104 of a second type of gold oxide semiconductor, and a stress layer pattern 106. The stress layer pattern 106 can be used to form a source/drain region of the second type of MOS transistor to control the stress applied to the channel region. Further, the stress layer pattern 106 and the first active region pattern 102 are, for example, separated from each other. The second active region pattern 104 is, for example, located inside the stress layer pattern 106.

When the first type of MOS transistor is an NMOS transistor and the second type MOS transistor is a PMOS transistor, the stress layer pattern 106 is formed. The material of the resulting stressor layer can be SiGe. When the first type of gold oxide semiconductor is a PMOS transistor and the second type of gold oxide half is an NMOS transistor, the material of the stress layer formed by the stress layer pattern 106 may be SiC.

The design method of the stress layer pattern proposed in this embodiment first calculates the first distances D11, D21, and D31 between the boundary of the stress layer pattern 106 and the first active region pattern 102 of the first type MOS transistor. The first distance D11, D21 is, for example, smaller than the safety distance Ds, and the first distance D31 is equal to the safety distance Ds, for example. The safety distance Ds is determined, for example, by the process capability of the applied process generation.

Then, referring to FIG. 2B, the broken line portion indicates the boundary of the initial stress layer pattern 106, and the solid line portion indicates the boundary of the adjusted stress layer pattern 106a. When the first distances D11, D21 are smaller than the safety distance Ds, the stress layer pattern 106 is reduced to the stress layer pattern 106a. Thereby, the first distances D11 and D21 can be respectively adjusted to be at least equal to the first distances D12 and D22 of the safety distance Ds. The first distance D12 is equal to, for example, the safety distance Ds, and the first distance D22 is, for example, greater than the safety distance Ds.

At this time, since the first distance D12, D22 between the boundary of the stress layer pattern 106a and the first active region pattern 102 of the first type MOS transistor is at least equal to the safety distance Ds, sufficient process margin can be provided (process Window) to cope with process variations that may occur during lithography, etching, etc. For example, in a case where the first distance D12, D22 between the boundary of the stress layer pattern 106a and the first active region pattern 102 of the first type MOS transistor is at least equal to the safety distance Ds, even if it covers the first The patterned photoresist layer on the active region pattern 102 is reduced due to process variation. The patterned photoresist layer on the first active region pattern 102 can still completely cover the first active region pattern 102. Therefore, in the subsequent deposition process of forming the stress layer, it is possible to avoid the formation of protruding defects around the first active region 102.

Next, although the first distance D31 is equal to the safety distance Ds, the stress layer pattern 106 here can be selectively reduced to the stress layer pattern 106a. Thereby, the first distance D31 can be adjusted to be greater than the first distance D32 of the safety distance Ds to further enhance the process margin here.

Further, in the step of reducing the stress layer pattern 106 to the stress layer pattern 106a, the design rule of the design method of the stress layer pattern 106a includes the boundary of the stress layer pattern 106a and the second active of the second type MOS transistor. The second distances D4, D5, D6 between the zone patterns 104 are at least equal to the safety distance Ds. The second distance D4, D5 is equal to, for example, the safety distance Ds, and the second distance D6 is, for example, greater than the safety distance Ds. In addition, the design rule of the design method of the stress layer pattern 106a described above also includes making the width of the stress layer pattern 106a at least equal to the minimum stress layer width that can be defined by the applied process generation to prevent the stress layer from being necking.

According to the above embodiment, since the first distance D12, D22, D32 between the boundary of the stress layer pattern 106a and the first active region pattern 102 of the first type MOS transistor is at least equal to the safety distance Ds, it has a larger The process margin can prevent the occurrence of protruding defects around the first active region 102 of the first type MOS transistor due to process variation, thereby effectively improving the electrical performance of the semiconductor device.

FIG. 3 is a schematic diagram of the embodiment of FIG. 2B applied to a 40 nm semiconductor process. In addition, the same reference numerals are used in FIG. 3 and FIG. 2B. Have the same configuration relationship, use and effect, so it will not be described here.

In the embodiment of FIG. 3, the first active region 102 is, for example, an active region of an NMOS transistor, and the second active region 104 is, for example, an active region of a PMOS transistor, and the stress layer pattern 106a can be used to form a stress layer of SiGe. And the stress layer can serve as the source/drain region of the PMOS transistor. The dotted line portion indicates the boundary of the initial stress layer pattern 106, and the solid line portion indicates the boundary of the adjusted stress layer pattern 106a.

Referring to FIG. 3, FIG. 2A and FIG. 2B simultaneously, it is calculated that the first distances D11 and D21 are 30 nm, and the first distance D31 is 36 nm. Further, the safety distance Ds was set to 36 nm. It can be seen that the first distance D11, D21 is smaller than the safety distance Ds, and the first distance D31 is equal to the safety distance Ds. Therefore, the stress layer pattern 106 needs to be reduced to the stress layer pattern 106a to adjust the first distances D11, D21 to at least the first distances D12 and D22 of the safety distance Ds. Wherein, the first distance D12 is 36 nm, and the first distance D12 is made equal to the safety distance Ds. The first distance D22 is 46 nm such that the first distance D22 is greater than the safety distance Ds. Furthermore, although the first distance D31 is already equal to the safety distance Ds, the first distance D31 can be selectively adjusted to be greater than the first distance D32 of the safety distance Ds to further enhance the process margin herein. Wherein, the first distance D32 is 56 nm.

In the step of reducing the stress layer pattern 106 to the stress layer pattern 106a, the design rule to be followed includes setting the second distances D4, D5, and D6 between the boundary of the stress layer pattern 106a and the second active region pattern 104, respectively. 36 nm, 36 nm, 41 nm. That is, the second distance D4, D5 is equal to the safety distance Ds, and the second distance D6 is greater than the safety distance Ds. However, in other In an embodiment, the second distance D4, D5 may also be greater than the safety distance Ds, and the second distance D6 may also be equal to the safety distance Ds. In addition, the design rule also includes that the width of the stress layer pattern 106a needs to be at least equal to 162 nm, such that the width of the stress layer pattern 106a is at least equal to the minimum stress layer width that can be defined by a semiconductor process of 40 nm.

Referring to FIG. 3, in the process of fabricating the trench for forming the stress layer by using the semiconductor device pattern 100 of FIG. 3, the stress layer patterns 106, 106a represent the trench range for the stress layer, the unstressed layer pattern. The area covered by 106, 106a represents the extent of the patterned photoresist layer covering the first active area 102.

In addition, before and after the adjustment of the stress layer pattern, the variation of the range of the patterned photoresist layer covering the first active region 102 is as shown in Table 1.

As can be seen from Table 1, at the position where the first distance D11 (30 nm) is adjusted to the first distance D12 (36 nm), the safety distance Ds is set to 36 nm. And under the design rule that the second distance D4 is 36 nm, the range of the patterned photoresist layer covering the first active region 102 can be expanded outward by at most 6 nm, and the additional processing margin with respect to the safety distance Ds (36 nm) is 0. .

At a position where the first distance D21 (30 nm) is adjusted to the first distance D22 (46 nm), the pattern covering the first active region 102 is covered under a design rule that the safety distance Ds is 36 nm and the second distance D5 is 36 nm. The photoresist layer can be expanded up to 16 nm outward, and the additional processing margin relative to the safe distance Ds (36 nm) is 10 nm.

At a position where the first distance D31 (36 nm) is adjusted to the first distance D32 (56 nm), the pattern covering the first active region 102 is covered under a design rule that the safety distance Ds is 36 nm and the second distance D6 is 41 nm. The photoresist layer can be expanded up to 20 nm outward, and the additional processing margin relative to the safe distance Ds (36 nm) is 20 nm.

Similarly, as can be seen from the above embodiment, since the first distance D12, D22, D32 between the boundary of the stress layer pattern 106a and the first active region pattern 102 of the NMOS transistor is at least equal to the safety distance Ds, the process has a larger process. The margin can prevent the occurrence of protruding defects around the first active region 102 due to process variations, thereby effectively improving the electrical performance of the semiconductor device.

4A to 4D are schematic views showing a design flow of a stress layer pattern according to another embodiment of the present invention.

Referring to FIG. 4A, the semiconductor element pattern 200 includes an element pattern 202 of a MOS transistor, a dummy diffusion pattern 204, and an initial stress layer pattern 206. The MOS transistor is, for example, an NMOS transistor or a PMOS transistor. body. The element pattern 202 is, for example, a word line pattern. The function of the virtual diffusion pattern 204 is to balance the pattern density.

First, a virtual diffusion pattern 204 partially overlapping the initial stress layer pattern 206 is found. In this embodiment, the number of the dummy diffusion patterns 204 partially overlapping the initial stress layer pattern 206 is illustrated by taking six examples, but is not intended to limit the present invention as long as the virtual diffusion partially overlaps with the initial stress layer pattern 206. The number of patterns 204 is at least one, which is within the scope of the claimed invention.

Next, referring to FIG. 4B, the auxiliary stress layer pattern 208 completely covering the dummy diffusion pattern 204 partially overlapping the initial stress layer pattern 206 is calculated to solve the problem that the initial stress layer pattern 206 partially overlaps the dummy diffusion pattern 204.

Then, referring to FIG. 4C, the initial stress layer pattern 206 and the auxiliary stress layer pattern 208 are combined to obtain the stress layer pattern 210. Wherein, the stress layer pattern 210 completely covers the dummy diffusion pattern 204 partially overlapping the initial stress layer pattern 206. The stress layer pattern 210 can be used to form a source/drain region of the MOS transistor to control the stress applied to the channel region.

Next, referring to FIG. 4D, when the initial stress layer pattern 206 partially overlaps the plurality of dummy diffusion patterns 204, and the plurality of auxiliary stress layer patterns 208 covering the dummy diffusion pattern 204 are calculated, the adjacent ones are more selectively merged. The auxiliary stress layer pattern 208 forms the auxiliary stress layer pattern 208a, thereby forming the stress layer pattern 210a. As a result, when the trench for providing the stress layer is formed, the phenomenon that the patterned photoresist layer formed between the adjacent auxiliary stress layer patterns 208 is too small and collapses can be avoided.

Based on the above embodiments, since the dummy diffusion pattern 204 is used to form a dummy diffusion region, and the dummy diffusion region does not affect electrical properties, the stress layer patterns 210, 210a may be designed to completely cover the dummy diffusion pattern 204. As such, by designing the stress layer patterns 210, 210a to completely cover the dummy diffusion pattern 204, the dummy diffusion regions can be removed in the step of forming the trenches for providing the stress layers. Therefore, in the deposition process for forming the stress layer, it is possible to prevent the formation of protruding defects around the dummy diffusion region, thereby effectively enhancing the electrical performance of the semiconductor element.

In summary, the above embodiment has at least the following advantages:

1. By the design method of the stress layer pattern proposed in the above embodiment, it is possible to prevent the occurrence of protruding defects around the active region.

2. By the design method of the stress layer pattern proposed in the above embodiment, it is possible to avoid forming a protruding defect around the virtual diffusion region.

3. The design method of the stress layer pattern proposed in the above embodiments can effectively improve the electrical performance of the semiconductor device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ PMOS transistor

14‧‧‧SiGe layer

16‧‧‧ patterned photoresist layer

18‧‧‧ NMOS transistor

20‧‧‧active area

22‧‧‧ Outstanding defects

100, 200‧‧‧ semiconductor component pattern

102‧‧‧First active area pattern

104‧‧‧Second active area pattern

106, 106a‧‧‧ stress layer pattern

202‧‧‧Component pattern

204‧‧‧Virtual diffusion pattern

206‧‧‧Initial stress layer pattern

208, 208a‧‧‧Auxiliary stress layer pattern

210, 210a‧‧‧ stress layer pattern

D11, D12, D21, D22, D31, D32‧‧‧ first distance

D4, D5, D6‧‧‧ second distance

Ds‧‧‧Safe distance

FIG. 1 is a cross-sectional view of a conventional CMOS.

FIG. 2A to FIG. 2B are schematic diagrams showing a design flow of a stress layer pattern according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of the embodiment of FIG. 2B applied to a 40 nm semiconductor process.

4A to 4D are schematic views showing a design flow of a stress layer pattern according to another embodiment of the present invention.

100‧‧‧Semiconductor component pattern

102‧‧‧First active area pattern

104‧‧‧Second active area pattern

106a‧‧‧stress layer pattern

D11, D12, D21, D22, D31, D32‧‧‧ first distance

D4, D5, D6‧‧‧ second distance

Ds‧‧‧Safe distance

Claims (10)

A method for designing a stress layer pattern, wherein the stress layer pattern is used to form a source/drain region of a second type of MOS transistor, the method comprising: calculating a boundary of the stress layer pattern and a first a first distance between a first active region pattern of the MOS transistor; and when the first distance is less than a safe distance, reducing the stress layer pattern such that the first distance is at least equal to the safe distance . The method for designing a stress layer pattern according to claim 1, wherein the stress layer pattern and the first active region pattern are separated from each other. The method for designing a stress layer pattern as described in claim 1, wherein the safety distance is determined by the process capability of the applied process generation. The design method of the stress layer pattern according to claim 1, wherein the design rule of the method comprises: an additional process margin added to the boundary of the stress layer pattern and the second type MOS transistor A second distance between the second active area patterns is at least equal to the safe distance. The method for designing a stress layer pattern according to claim 4, wherein the second active region pattern is located inside the stress layer pattern. The design method of the stress layer pattern according to claim 1, wherein the design rule of the method comprises: making the width of the stress layer pattern at least equal to a minimum stress layer width that can be defined by the applied process generation. The design method of the stress layer pattern according to claim 1, further comprising reducing the stress layer pattern when the first distance is equal to the safety distance, such that the first distance is greater than the safety distance. A method for designing a stress layer pattern, wherein the stress layer pattern is used to form a source/drain region of a MOS transistor, the method comprising: finding a dummy diffusion pattern partially overlapping an initial stress layer pattern Calculating an auxiliary stress layer pattern covering the dummy diffusion pattern; and combining the initial stress layer pattern and the auxiliary stress layer pattern to obtain the stress layer pattern. The method for designing a stress layer pattern according to claim 8, wherein when the initial stress layer pattern partially overlaps the plurality of dummy diffusion patterns, a plurality of auxiliary stress layers completely covering the dummy diffusion patterns are calculated. In the case of a pattern, the method further includes merging the adjacent auxiliary stress layer patterns. The method for designing a stress layer pattern according to claim 9, wherein the step of merging the adjacent auxiliary stress layer patterns is performed after the step of combining the initial stress layer pattern and the auxiliary stress layer patterns.