TWI514414B - Memory device and control method thereof - Google Patents

Description

Memory device and memory control method

The present invention relates to a memory device, and more particularly to a memory device having a column decoder, wherein the column decoder can be used to reduce capacitive coupling effects between adjacent memory cells.

Figure 1 is a schematic diagram showing a conventional memory device 100. As shown in FIG. 1, the memory device 100 includes at least one memory cell array 110 and a column decoder 120. To simplify the drawing, the remaining components of the memory device 100 are omitted and are not shown in FIG. The memory cell array 110 includes a plurality of memory cells. A plurality of word lines WL and a plurality of local bit lines BL can be used to select the memory cells. In addition, the column decoder 120 can be configured to selectively couple one of the local bit lines BL to a global bit line GBL.

Figure 2 is a schematic diagram showing the capacitive coupling effect of a conventional memory device 100. As shown in FIG. 2, the memory cell array 110 can be implemented by a plurality of memory transistors M1-1 through M3-3 (which may also be referred to as "memory cells"). As the semiconductor process progresses, the size of the memory device 100 becomes more compact, which will cause the memory transistors M1-1 to M3-3 therein to be closer to each other due to parasitic capacitance between adjacent cells. The impact, even more serious mutual coupling effect. For example, when one of the word lines WL2 and one of the status lines BL2 are selected, the memory transistors M1-2, M2-2, and M3-2 are simultaneously enabled, and one is The stream I2 flows through the selected local bit line BL2, the memory transistor M2-2, and a source line VL. In an ideal state, the two adjacent element lines BL1, BL3 should be kept in a floating state and no current flows. However, under actual conditions, due to the capacitive coupling effect between the memory transistors M1-2, M2-2, and M3-2, there are still unexpected coupling currents I1 and I3 generated and flowing through the memory transistor. M1-2, M3-2 and the unselected local status lines BL1, BL3. Such mutual coupling effects may cause some operational errors and further reduce the reliability of the memory device 100.

In a preferred embodiment, the present invention provides a memory device comprising: a memory cell array including a complex even number of local bit lines and a plurality of odd local bit lines; and a column decoder comprising: a complex even channel transistor One of the control channels of each of the even channel transistors is coupled to an individual one of the plurality of even selection lines, and the first end of each of the even channel transistors is coupled to the even numbers One of the status lines, and each of the even-numbered channel transistors has a second end coupled to an even-numbered overall bit line; and a plurality of odd-numbered channel transistors, wherein each of the odd-numbered channel transistors A control terminal is coupled to each of the plurality of odd-numbered selection lines, and a first end of each of the odd-numbered channel transistors is coupled to each of the odd-numbered local element lines, and each The second ends of the odd-numbered channel transistors are all coupled to an odd-numbered overall bit line; wherein the even-numbered overall bit lines are different from the odd-numbered overall bit lines.

In another preferred embodiment, the present invention provides a memory control method including the steps of: providing a memory cell array, wherein the memory sheet The meta-array includes a complex even-numbered positional element line and a complex odd-numbered positional element line; a column decoder is provided, wherein the column decoder comprises a plurality of even-numbered channel transistors and a plurality of odd-numbered channel transistors, wherein the even-numbered channel electro-crystal system selection Optionally coupling the even-numbered local element lines to an even-numbered overall bit line, the odd-numbered channel electro-crystal systems selectively coupling the odd-numbered local bit lines to an odd-numbered overall bit line, and the even-numbered total The bit line is different from the odd overall bit line; one of the even channel transistors or one of the odd channel transistors is selected and enabled; when one of the even channel transistors is When selected and enabled, the remaining unselected even channel transistors are disabled, and all of the odd channel transistors are enabled, and all of the odd local bit lines are pulled down to one by the odd overall bit line a ground potential; and when one of the odd channel transistors is selected and enabled, disabling the remaining unselected odd channel transistors and enabling all of the even channel transistors, and by the Overall all such even-numbered bit line pull down the local bit lines to the ground potential.

100, 300‧‧‧ memory devices

110, 310‧‧‧ memory cell array

120, 320‧‧‧ column decoder

330‧‧‧Overall bit line decoder

BL‧‧‧ Status Line

BL0, BL2, BL4, BL6‧‧‧ even number of status lines

BL1, BL3, BL5, BL7‧‧‧ odd number of status lines

GBL‧‧‧ overall bit line

GBL0‧‧‧ even overall bit line

GBL1‧‧‧ odd overall bit line

GND‧‧‧ Ground potential

I1, I2, I3, I4, I5, I6‧‧‧ current

M0, M2, M4, M6‧‧‧ even channel transistors

M1, M3, M5, M7‧‧‧ odd channel transistors

M1-1, M1-2, M1-3, M2-1, M2-2, M2-3, M3-1, M3-2, M3-3‧‧‧ memory transistors

S710, S720, S730, S740, S750‧‧ steps

VL‧‧‧ source line

WL, WL1, WL2, WL3‧‧‧ character line

YSA<0>, YSA<2>, YSA<4>, YSA<6>‧‧‧ even choice line

YSA<1>, YSA<3>, YSA<5>, YSA<7>‧‧‧ odd selection lines

1 is a schematic view showing a conventional memory device; FIG. 2 is a schematic view showing a capacitive coupling effect of a conventional memory device; and FIG. 3 is a schematic view showing a memory device according to an embodiment of the present invention; 4 is a schematic diagram showing the operation of a memory device according to an embodiment of the present invention when any even number of bit lines are selected; FIG. 5 is a view showing a memory device according to an embodiment of the invention. Ren FIG. 6 is a schematic diagram showing the operational advantages of a memory device according to an embodiment of the present invention; and FIG. 7 is a view showing an operation of the memory device according to an embodiment of the present invention; A flow chart of the memory control method.

In order to make the objects, features and advantages of the present invention more comprehensible, the specific embodiments of the invention are set forth in the accompanying drawings.

FIG. 3 is a schematic diagram showing a memory device 300 according to an embodiment of the invention. The memory device 300 can be a flash memory, such as a NOR flash memory. As shown in FIG. 3, the memory device 300 includes at least one memory cell array 310 and a column decoder 320. It must be understood that the memory device 300 may further include other components such as a driver, a column of decoders, and a sense amplifier. To simplify the drawing, some of the components of the memory device 300 are omitted and are not shown in FIG. The memory cell array 310 can include a plurality of memory cells. In some embodiments, memory cell array 310 can be an electronic erasable rewritable read only memory (EEPROM). The memory cell array 310 may further include a plurality of word line lines WL and a plurality of bit position lines BL0 to BL7 to operate the memory cells.

The local bit lines BL0 to BL7 may be divided into a plurality of even-numbered local bit lines BL0, BL2, BL4, and BL6, and a plurality of odd-numbered local bit lines BL1, BL3, BL5, and BL7. Each even number of status lines or each odd number of status lines can be coupled to some memory units disposed in an individual column. in In some embodiments, the even-numbered local element lines BL0, BL2, BL4, and BL6 are interleaved with the odd-numbered local element lines BL1, BL3, BL5, and BL7, respectively. The column decoder 320 is selectively coupled to one of the even-numbered local bit lines BL0, BL2, BL4, BL6 or a plurality of bits to an even-numbered overall bit line GBL0, or (and) selectively coupled to the odd-numbered lines One or more of the status elements BL1, BL3, BL5, BL7 to an odd overall bit line GBL1. The even overall bit line GBL0 is different from the odd overall bit line GBL1, and the two are separated from each other. In some embodiments, the memory device 300 further includes a Global Bit Line Decoder 330, wherein the even total bit line GBL0 and the odd overall bit line GBL1 are coupled to the overall bit line decoder. The devices 330 are both controlled by the overall bit line decoder 330. For example, the overall bit line decoder 330 may select one of the even total bit line GBL0 and the odd overall bit line GBL1 as an input or output, and adjust the even total bit line GBL0 and the odd overall bit line GBL1. The potential of the other one. In some embodiments, the column decoder 320 and the overall bit line decoder 330 can be collectively controlled by a control signal from a driver or a processor (not shown).

In more detail, the column decoder 320 includes an upper portion and a lower portion. Half part. The upper half includes a plurality of even channel transistors M0, M2, M4, M6, and the lower half includes a plurality of odd channel transistors M1, M3, M5, M7. It must be understood that although only eight sets of component branches are shown in FIG. 3, in practice memory device 300 may include more or fewer sets of status lines, overall bit lines, or channel transistors. That is, the number of the present element line, the overall bit line, or the channel transistor is not particularly limited in the present invention. In some embodiments, memory cell array 310 and column decoder 320 may be replicated multiple times and periodically Columns, while Figure 3 shows only a portion of this periodic structure.

Control of one of each even channel transistor M0, M2, M4, M6 The end systems are respectively coupled to the individual ones of the plurality of even selection lines YSA<0>, YSA<2>, YSA<4>, and YSA<6>. For example, one of the gates of the even channel transistor M0 is coupled to an even selection line YSA<0>. The first end of each of the even-numbered channel transistors M0, M2, M4, and M6 is coupled to one of the even-numbered local bit lines BL0, BL2, BL4, and BL6, respectively. For example, one source (or drain) of the even channel transistor M0 is coupled to an even number of local bit lines BL0. The second end of each of the even-numbered channel transistors M0, M2, M4, M6 is coupled to the even-numbered overall bit line GBL0. For example, the other source (or drain) of the even channel transistor M0 is coupled to the even overall bit line GBL0. One of the control channels of each of the odd-numbered channel transistors M1, M3, M5, and M7 is coupled to one of a plurality of odd-numbered selection lines YSA<1>, YSA<3>, YSA<5>, and YSA<7>, respectively. . For example, one of the gates of the odd channel transistor M1 is coupled to an odd selection line YSA<1>. The first end of each of the odd-numbered channel transistors M1, M3, M5, and M7 is coupled to one of the odd-numbered local element lines BL1, BL3, BL5, and BL7, respectively. For example, one source (or drain) of the odd channel transistor M1 is coupled to an odd number of local bit lines BL1. The second end of each of the odd channel transistors M1, M3, M5, M7 is coupled to the odd overall bit line GBL1. For example, the other source (or drain) of the odd channel transistor M1 is coupled to the odd overall bit line GBL1. In some embodiments, the even-numbered channel transistors M0, M2, M4, M6 and the odd-numbered channel transistors M1, M3, M5, and M7 are all N-type metal oxide semiconductor field effect transistors (N-type Metal -Oxide-Semiconductor Field-Effect Transistor).

The column decoder 320 controls the even selection lines YSA<0>, YSA<2>, YSA<4>, and YSA<6> select one of the even-numbered local element lines BL0, BL2, BL4, and BL6. For example, when the even local bit line BL2 and the corresponding even channel transistor M2 are selected, the even selection line YSA<2> is pulled up to a high potential (for example: 1V or 4.5V), and the remaining even numbers The selection lines YSA<0>, YSA<4>, and YSA<6> are pulled down to a ground potential (for example, 0V). Therefore, the even channel transistor M2 is enabled, and the even local bit line BL2 is also coupled to the even overall bit line GBL0. Similarly, the column decoder 320 selects the odd-numbered local element lines BL1, BL3, and BL5 by controlling the odd-numbered selection lines YSA<1>, YSA<3>, YSA<5>, and YSA<7>. One of the BL7. For example, when the odd local bit line BL3 and the corresponding odd channel transistor M3 are selected, the odd selection line YSA<3> is pulled up to a high potential (for example: 1V or 4.5V), and the remaining odd numbers The selection lines YSA<1>, YSA<5>, and YSA<7> are pulled down to a ground potential (for example, 0V). Therefore, the odd channel transistor M3 is enabled, and the odd local bit line BL3 is also coupled to the odd overall bit line GBL1. The selection process of other odd and even local status lines can be performed in a manner similar to the foregoing. The memory device 300 and its column decoder 320 are designed to reduce the mutual coupling effects between adjacent memory cells, the operational details of which will be as described in the following embodiments.

Figure 4 is a diagram showing a memory according to an embodiment of the present invention. A schematic diagram of the operation of device 300 when any even number of positional elements are selected. When any of the even channel transistors M0, M2, M4, M6 is selected and enabled, its corresponding even number of bit lines are selected and coupled to the even overall bit line GBL0. At this point, the remaining unselected even channel transistors are disabled, and All of these odd channel transistors M1, M3, M5, M7 are enabled. In addition, the odd overall bit line GBL1 is coupled to a ground potential by the overall bit line decoder 330. Since all of the odd channel transistors M1, M3, M5, and M7 are enabled, all of the odd local bit lines BL1, BL3, BL5, and BL7 are coupled to the odd overall bit line GBL1 and are pulled down. To the ground potential. For example, when the even channel transistor M6 is selected and enabled, its corresponding even number of bit lines BL6 are selected and coupled to the even overall bit line GBL0 (a current I4 can flow through the even channel transistor) M6). At this time, the remaining unselected even channel transistors M0, M2, M4 are disabled, and all of the odd channel transistors M1, M3, M5, M7 are enabled. In addition, the odd overall bit line GBL1 is coupled to a ground potential by the overall bit line decoder 330, and all of the odd local bit lines BL1, BL3, BL5, BL7 are pulled down by the odd overall bit line GBL1. The ground potential. In short, during some operations of the memory device 300 (eg, read or program operations), any even number of local bit lines selected are always adjacent to the two odd-numbered local bit lines that have been grounded.

Figure 5 is a diagram showing a memory according to an embodiment of the present invention. A schematic diagram of the operation of device 300 when any odd number of status lines are selected. When any of the odd channel transistors M1, M3, M5, M7 is selected and enabled, its corresponding odd positional element line is selected and coupled to the odd overall bit line GBL1. At this time, the remaining unselected odd channel transistors are disabled, and all of the even channel transistors M0, M2, M4, M6 are enabled. In addition, the even overall bit line GBL0 is coupled to a ground potential by the overall bit line decoder 330. Since all of the even-numbered channel transistors M0, M2, M4, and M6 are enabled, all of the even-numbered local element lines BL0, BL2, BL4, and BL6 are It is coupled to the even overall bit line GBL0 and pulled down to the ground potential. For example, when the odd channel transistor M5 is selected and enabled, its corresponding odd bit line BL5 is selected and coupled to the odd overall bit line GBL1 (a current I5 can flow through the odd channel transistor) M5). At this time, the remaining unselected odd channel transistors M1, M3, M7 are disabled, and all of the even channel transistors M0, M2, M4, M6 are enabled. In addition, the even-numbered bit line GBL0 is coupled to a ground potential by the overall bit line decoder 330, and all of the even-numbered bit lines BL0, BL2, BL4, and BL6 are pulled down by the even-numbered bit line GBL0. The ground potential. In short, during some operations of the memory device 300 (eg, read or program operations), any odd-numbered local element lines selected are always adjacent to the two even-numbered local bit lines that have been grounded.

Figure 6 is a diagram showing a memory according to an embodiment of the present invention. A schematic diagram of the operational advantages of device 300. As shown in FIG. 6, the memory cell array 310 may include a plurality of memory transistors M1-1 to M3-3 (which may also be referred to as "memory cells"). It must be understood that some of the components of the memory device 300 are omitted for simplicity of the drawing and are not shown in FIG. Please compare the traditional design of the embodiment of Fig. 6 with the first figure. When a word line WL2 and a status element line BL2 are selected, the memory transistors M1-2, M2-2, and M3-2 are simultaneously enabled, and a current I6 flows through the selected local element. Line BL2, memory transistor M2-2, and a source line VL. Since the present invention adds separate odd-numbered and even-numbered bit lines to control these local bit lines, during operation of the memory device 300, adjacent local bit lines BL1, BL3 are both pulled down to a ground potential GND without In the floating state, under this design, no unexpected coupling current is generated and flows through the memory transistors M1-2, M3-2 and their position lines BL1, BL3. therefore, The invention can effectively eliminate the capacitive coupling effect between adjacent memory cells, and the memory device and the column decoder provided by the invention can have higher reliability and lower error rate than the conventional design.

Figure 7 is a diagram showing a memory according to an embodiment of the present invention. Flow chart of the control method. In step S710, a memory cell array is provided, wherein the memory cell array includes a complex even number of local bit lines and a plurality of odd local bit lines. In step S720, a column decoder is provided, wherein the column decoder comprises a plurality of even channel transistors and a plurality of odd channel transistors, wherein the even channel cell systems selectively couple the even number of bit lines to one Even-numbered bit line lines, the odd-numbered channel cell systems selectively coupling the odd-numbered bit lines to an odd-numbered bit line, and the even-numbered bit lines are different from the odd-numbered bit lines . In step S730, one of the even channel transistors or one of the odd channel transistors is selected and enabled. When one of the even channel transistors is selected and enabled, in step S740, the remaining unselected even channel transistors are disabled, and all of the odd channel transistors are enabled, and by the odd total The bit line pulls all of the odd local bit lines down to a ground potential. When one of the odd channel transistors is selected and enabled, in step S750, the remaining unselected odd channel transistors are disabled, and all of the even channel transistors are enabled, and by the even total The bit line pulls all of the even local bit lines down to the ground potential. In some embodiments, the even overall bit line and the odd overall bit line are both controlled by a global bit line decoder. It must be understood that any or a plurality of features of the embodiments of Figures 3-6 can be applied to the memory control method illustrated in Figure 7.

The ordinal number in this specification and the scope of the patent application, for example, One, "second", "third", etc., have no sequential relationship with each other, and are only used to indicate that two different elements having the same name are distinguished.

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

300‧‧‧ memory device

310‧‧‧Memory Cell Array

320‧‧‧ column decoder

330‧‧‧Overall bit line decoder

BL0, BL2, BL4, BL6‧‧‧ even number of status lines

BL1, BL3, BL5, BL7‧‧‧ odd number of status lines

GBL0‧‧‧ even overall bit line

GBL1‧‧‧ odd overall bit line

M0, M2, M4, M6‧‧‧ even channel transistors

M1, M3, M5, M7‧‧‧ odd channel transistors

WL‧‧‧ character line

YSA<0>, YSA<2>, YSA<4>, YSA<6>‧‧‧ even choice line

YSA<1>, YSA<3>, YSA<5>, YSA<7>‧‧‧ odd selection lines

Claims (11)

A memory device comprising: a memory cell array comprising a complex even number of local bit lines and a plurality of odd local bit lines; and a column decoder comprising: a complex even channel transistor, wherein each of the even channel transistors One of the control terminals is coupled to each of the plurality of even-numbered selection lines, and the first end of each of the even-numbered channel transistors is coupled to an individual one of the even-numbered positional lines, and each One of the even-numbered channel transistors has a second end coupled to an even-numbered overall bit line; and a plurality of odd-numbered channel transistors, wherein each of the odd-numbered channel transistors is coupled to a plurality of odd-numbered transistors One of the selected ones of the odd-numbered channel transistors is coupled to each of the odd-numbered bit lines, and each of the odd-numbered channel transistors is second The terminals are all coupled to an odd overall bit line; wherein the even total bit line is different from the odd overall bit line; wherein when one of the even channel transistors is selected and enabled, the remaining Is selected The even channel transistor are disabled, and all such are odd-channel transistor is enabled. The memory device of claim 1, wherein when one of the even channel transistors is selected and enabled, all of the odd local bit lines are pulled down by the odd overall bit line A ground potential. The memory device of claim 1, wherein when one of the odd channel transistors is selected and enabled, the remaining unselected odd numbers The channel transistors are disabled and all of the even channel transistors are enabled. The memory device of claim 3, wherein when one of the odd channel transistors is selected and enabled, all of the even local bit lines are pulled down by the even total bit line to A ground potential. The memory device of claim 1, further comprising: an overall bit line decoder, wherein the even total bit line and the odd overall bit line are coupled to the overall bit line decoder And are controlled by the overall bit line decoder. The memory device of claim 1, wherein the even-numbered positional lines are interlaced with the odd-numbered element lines. The memory device of claim 1, wherein the even channel transistors and the odd channel transistors are all N-type metal oxide semiconductor field effect transistors. A memory control method comprising the steps of: providing a memory cell array, wherein the memory cell array comprises a complex even number of positional elements and a plurality of odd locality element lines; providing a column decoder, wherein the column decoder comprises a complex even number a channel transistor and a plurality of odd channel transistors, wherein the even channel cell systems selectively couple the even number of bit lines to an even number of bit lines, the odd channel cell systems being selectively coupled The odd-numbered local element lines are connected to an odd-numbered overall bit line, and the even-numbered overall bit line is different from the odd-numbered overall bit line; Selecting and enabling one of the even channel transistors or one of the odd channel transistors; when one of the even channel transistors is selected and enabled, disabling the remaining unselected even numbers Channel transistors, and enabling all of the odd channel transistors, and pulling all of the odd local bit lines to a ground potential by the odd overall bit line; and when one of the odd channel transistors When selected and enabled, the remaining unselected odd channel transistors are disabled, and all of the even channel transistors are enabled, and all of the even local bit lines are pulled down by the even total bit line The ground potential. The memory control method of claim 8, further comprising: controlling the even total bit line and the odd overall bit line by an overall bit line decoder. The memory control method according to claim 8, wherein the even-numbered positional line systems are alternately arranged with the odd-numbered positional element lines. The memory control method of claim 8, wherein the even channel transistors and the odd channel transistors belong to an N-type metal oxide semiconductor field effect transistor.