TWI514382B - Operationmethod of multi-level memory - Google Patents
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本發明是有關於一種記憶體的操作方法，且特別是有關於一種多階記憶體的操作方法。The present invention relates to a method of operating a memory, and more particularly to a method of operating a multi-level memory.
隨著電腦的應用軟體逐漸龐大，所需的記憶體容量也就愈來愈大，因此用於儲存1位元或是2位元之記憶體元件已無法滿足現今的需求。近年來，可儲存多位元資料的多階記憶體（Multi-Level Memory）已成為最具發展潛力的記憶體元件。As the application software of computers becomes larger and larger, the required memory capacity becomes larger and larger, so the memory components for storing 1-bit or 2-bit are no longer able to meet the needs of today. In recent years, multi-level memory, which can store multi-bit data, has become the most promising memory component.
一般而言，在多階記憶體具有兩個儲存位置的情況下，當要判斷一儲存位置的位準時，通常會對鄰近另一儲存位置的摻雜區施加一標準讀取電壓。然而，當鄰近施加有電壓之摻雜區的儲存位置未儲存電荷時，亦即該儲存位置的位準為最低位準時，施加標準讀取電壓後所產生的電流會導致嚴重的讀取干擾（read disturbance），進而影響讀取位準的準確性。此外，在兩個儲存位置都未儲存電荷時，亦即兩個儲存位置的位準皆為最低位準時，上述讀取干擾的現象尤其嚴重。In general, where the multi-level memory has two storage locations, when a level of a storage location is to be determined, a standard read voltage is typically applied to the doped region adjacent to the other storage location. However, when the storage location adjacent to the doped region to which the voltage is applied does not store charge, that is, the level of the storage location is the lowest level, the current generated after applying the standard read voltage may cause severe read disturb ( Read disturbance), which in turn affects the accuracy of the read level. In addition, when the charge is not stored in the two storage locations, that is, when the levels of the two storage locations are all at the lowest level, the above-mentioned reading interference phenomenon is particularly serious.
本發明提供一種多階記憶體的操作方法，其可避免因讀取干擾而對讀取操作造成影響。The present invention provides a method of operating a multi-level memory that avoids impact on read operations due to read disturb.
本發明的多階記憶體的操作方法適用於具有第一儲存位置與第二儲存位置的多階記憶體，其中該多階記憶體的多個位準對應到不同的電流值，且該多階記憶體包括基底、控制閘極、位於基底與控制閘極之間的電荷儲存層，以及位於控制閘極二側的基底中的多個摻雜區。此多階記憶體的操作方法包括以下步驟。對控制閘極任一側的摻雜區施加低於標準讀取電壓的較低讀取電壓，以判斷第一儲存位置與第二儲存位置的位準是否皆為最低位準。The method for operating a multi-level memory of the present invention is applicable to a multi-level memory having a first storage location and a second storage location, wherein a plurality of levels of the multi-level memory correspond to different current values, and the multi-level The memory includes a substrate, a control gate, a charge storage layer between the substrate and the control gate, and a plurality of doped regions in the substrate on both sides of the control gate. The method of operation of this multi-level memory includes the following steps. A lower read voltage lower than the standard read voltage is applied to the doped region on either side of the control gate to determine whether the levels of the first storage location and the second storage location are all at the lowest level.
在本發明的一實施例中，當第一儲存位置與第二儲存位置的位準皆非最低位準時，對鄰近於第一儲存位置的摻雜區施加一低於標準讀取電壓之第二讀取電壓，以判斷第二儲存位置的位準。In an embodiment of the invention, when the levels of the first storage location and the second storage location are not the lowest level, applying a second lower than the standard read voltage to the doped region adjacent to the first storage location The voltage is read to determine the level of the second storage location.
在本發明的一實施例中，若上述第二儲存位置的位準為最低位準，則對鄰近於第二儲存位置的摻雜區施加低於標準讀取電壓的第三讀取電壓，以判斷第一儲存位置的位準。In an embodiment of the invention, if the level of the second storage location is the lowest level, applying a third read voltage lower than the standard read voltage to the doped region adjacent to the second storage location, Determine the level of the first storage location.
在本發明的一實施例中，若上述第二儲存位置的位準不為最低位準，則對鄰近於第二儲存位置的摻雜區施加標準讀取電壓，以判斷第一儲存位置的位準。In an embodiment of the invention, if the level of the second storage location is not the lowest level, a standard read voltage is applied to the doped region adjacent to the second storage location to determine the bit of the first storage location. quasi.
在本發明的一實施例中，當對控制閘極任一側的摻雜區施加較低讀取電壓且所讀取到的電流值為最大時，判斷第一儲存位置與第二儲存位置的位準皆為最低位準。In an embodiment of the invention, when a lower read voltage is applied to the doped region on either side of the control gate and the read current value is maximum, determining the first storage location and the second storage location The level is the lowest level.
在本發明的一實施例中，上述的第一讀取電壓為標準讀取電壓的1/2至2/3。In an embodiment of the invention, the first read voltage is 1/2 to 2/3 of the standard read voltage.
在本發明的一實施例中，上述的第二讀取電壓為標準讀取電壓的1/2至2/3。In an embodiment of the invention, the second read voltage is 1/2 to 2/3 of the standard read voltage.
在本發明的一實施例中，上述的第三讀取電壓為標準讀取電壓的1/2至2/3。In an embodiment of the invention, the third read voltage is 1/2 to 2/3 of the standard read voltage.
在本發明的一實施例中，上述的標準讀取電壓為1.1 V至1.8 V。In an embodiment of the invention, the standard read voltage is 1.1 V to 1.8 V.
在本發明的一實施例中，上述的第一讀取電壓為0.5 V至1.1 V。In an embodiment of the invention, the first read voltage is 0.5 V to 1.1 V.
在本發明的一實施例中，上述的第二讀取電壓為0.5 V至1.1 V。In an embodiment of the invention, the second read voltage is 0.5 V to 1.1 V.
在本發明的一實施例中，上述的第三讀取電壓為0.5 V至1.1 V。In an embodiment of the invention, the third read voltage is 0.5 V to 1.1 V.
基於上述，在本發明所提出之多階記憶體的操作方法中，先以低於一般常用的標準讀取電壓的讀取電壓來進行讀取操作以排除第一儲存位置與第二儲存位置的位準皆為最低位準的情況，然後再同樣以低於一般常用的標準讀取電壓的讀取電壓判斷第二儲存位置的位準，並針對該位準調整第一儲存位置的讀取電壓，以在可避免讀取干擾對讀取操作造成影響的情況下讀取第一儲存位置的位準。Based on the above, in the operation method of the multi-level memory proposed by the present invention, the reading operation is performed at a reading voltage lower than a commonly used standard reading voltage to exclude the first storage location and the second storage location. The level is the lowest level, and then the level of the second storage position is judged by the reading voltage lower than the commonly used standard reading voltage, and the reading voltage of the first storage position is adjusted for the level. The level of the first storage location is read with the effect of avoiding read disturbs affecting the read operation.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
本發明提出一種多階記憶體的操作方法，可以避免因讀取干擾而對讀取操作造成影響。所述操作方法適用於具有兩個儲存位置的多階記憶體，其詳細說明如下。The invention provides a method for operating a multi-level memory, which can avoid the influence of read interference on the read operation. The method of operation is applicable to multi-level memory having two storage locations, which are described in detail below.
圖1是本發明之一實施例的多階記憶體的示意圖。1 is a schematic diagram of a multi-level memory of an embodiment of the present invention.
請參照圖1，多階記憶體100包括基底102、位於基底102上的底氧化層104、位於底氧化層104上的作為電荷補陷層的氮化矽層106、位於氮化矽層106上的頂氧化層108、位於頂氧化層108上的控制閘極110以及位在控制閘極110二側的基底102中的摻雜區112、114。摻雜區112、114可分別作為多階記憶體100的源極區或汲極區。Referring to FIG. 1, the multi-level memory 100 includes a substrate 102, a bottom oxide layer 104 on the substrate 102, a tantalum nitride layer 106 as a charge compensation layer on the bottom oxide layer 104, and a tantalum nitride layer 106. The top oxide layer 108, the control gate 110 on the top oxide layer 108, and the doped regions 112, 114 in the substrate 102 on both sides of the control gate 110. The doped regions 112, 114 may serve as source regions or drain regions of the multi-level memory 100, respectively.
在本實施例中，多階記憶體100的底氧化層104、氮化矽層106以及頂氧化層108組成電荷儲存層120。另外，多階記憶體100具有位在電荷儲存層120中的第一儲存位置P1及第二儲存位置P2。此外，多階記憶體100的多個位準對應到不同的電流值。In the present embodiment, the bottom oxide layer 104, the tantalum nitride layer 106, and the top oxide layer 108 of the multi-level memory 100 constitute the charge storage layer 120. In addition, the multi-level memory 100 has a first storage location P1 and a second storage location P2 located in the charge storage layer 120. In addition, multiple levels of multi-level memory 100 correspond to different current values.
以下，根據實施例詳細說明本發明之多階記憶體的操作方法。Hereinafter, the operation method of the multi-level memory of the present invention will be described in detail based on the embodiments.
圖2是本發明一實施例之多階記憶體的操作流程圖。圖3A至圖3D分別是於圖2之不同操作步驟中之多階記憶體的示意圖。特別一提的是，本實施例的操作方法是用以讀取第一儲存位置P1的位準。但是，本發明並不限於此。在其他實施例中，本發明的操作方法也可用以讀取第二儲存位置P2的位準。2 is a flow chart showing the operation of the multi-level memory according to an embodiment of the present invention. 3A-3D are schematic views of multi-level memory in different operational steps of FIG. 2, respectively. In particular, the method of operation of this embodiment is to read the level of the first storage location P1. However, the invention is not limited thereto. In other embodiments, the method of operation of the present invention can also be used to read the level of the second storage location P2.
在本文中，術語「最低位準」定義為儲存位置中未儲存電荷時的位準。術語「標準讀取電壓」定義為在二個儲存位置的位準皆為最低位準的情況下，所產生的電流會導致讀取干擾的電壓。As used herein, the term "lowest level" is defined as the level at which no charge is stored in the storage location. The term "standard read voltage" is defined as the voltage at which the generated current causes the read disturb to be the lowest level of the two storage locations.
首先，請同時參照圖2及圖3A，進行步驟S200，以判斷第一儲存位置P1與第二儲存位置P2的位準是否皆為最低位準。此步驟S200包括對基底102施加0 V，對控制閘極110施加閘極電壓Vg ，對摻雜區112施加低於標準讀取電壓Vd1 的第一讀取電壓Vd2 以及對摻雜區114施加0 V。如此一來，即可藉由讀取到的電流值判斷第一儲存位置P1與第二儲存位置P2的位準是否皆為最低位準。詳細而言，由於當第一儲存位置P1與第二儲存位置P2皆未儲存電荷時，在施加讀取電壓之後可得到最大的電流值。因此，在步驟S200中，當讀取到的電流值為最大時，則可判斷第一儲存位置P1與第二儲存位置P2皆未儲存電荷，即第一儲存位置P1與第二儲存位置P2的位準皆為最低位準。相反地，若讀取到的電流值不是最大時，可判斷第一儲存位置P1與第二儲存位置P2的位準不同時為最低位準，則繼續進行步驟S300。First, please refer to FIG. 2 and FIG. 3A simultaneously, and step S200 is performed to determine whether the levels of the first storage location P1 and the second storage location P2 are all at the lowest level. This step S200 includes applying 0 V to the substrate 102, applying a gate voltage V g to the control gate 110, applying a first read voltage V d2 lower than the standard read voltage V d1 to the doping region 112, and doping the doping region. 114 applies 0 V. In this way, whether the levels of the first storage location P1 and the second storage location P2 are all at the lowest level can be determined by the read current value. In detail, since no charge is stored when both the first storage location P1 and the second storage location P2 are stored, the maximum current value can be obtained after the application of the read voltage. Therefore, in step S200, when the read current value is the maximum, it can be determined that neither the first storage location P1 nor the second storage location P2 stores the charge, that is, the first storage location P1 and the second storage location P2. The level is the lowest level. Conversely, if the read current value is not the maximum, it can be determined that the level of the first storage location P1 and the second storage location P2 are different, and the process proceeds to step S300.
另外，在步驟S200中，透過對摻雜區112施加低於標準讀取電壓Vd1 的第一讀取電壓Vd2 ，可以避免當第一儲存位置P1與第二儲存位置P2的位準皆為最低位準時所產生的電流（具有最大電流值）導致讀取干擾。換言之，在步驟S200中，可在避免發生讀取干擾的情況下，判斷出第一儲存位置P1的位準為最低位準。In addition, in step S200, by applying a first read voltage V d2 lower than the standard read voltage V d1 to the doping region 112 , the levels of the first storage location P1 and the second storage location P2 can be avoided. The current generated at the lowest level (with the maximum current value) causes read disturb. In other words, in step S200, it is possible to determine that the level of the first storage location P1 is the lowest level in the case where reading interference is avoided.
在一實施例中，第一讀取電壓Vd2 為標準讀取電壓Vd1 的1/2至2/3。此外，在一實施例中，閘極電壓Vg 例如是3.5至4.5 V，標準讀取電壓Vd1 例如是1.1 V至1.8 V以及第一讀取電壓Vd2 例如是0.5 V至1.1 V。然而，本發明並不以所揭露的為限。前述各電壓值可根據實際上所使用之多階記憶體的類型及架構等而有所調整，只要當第一儲存位置P1與第二儲存位置P2的位準皆為最低位準時，所產生的電流不會導致讀取干擾即可。In an embodiment, the first read voltage V d2 is 1/2 to 2/3 of the standard read voltage V d1 . Further, in an embodiment, the gate voltage V g is, for example, 3.5 to 4.5 V, the standard read voltage V d1 is, for example, 1.1 V to 1.8 V, and the first read voltage V d2 is, for example, 0.5 V to 1.1 V. However, the invention is not limited to the disclosed. The foregoing voltage values may be adjusted according to the type and architecture of the multi-level memory actually used, as long as the levels of the first storage location P1 and the second storage location P2 are the lowest level, the generated The current does not cause read disturb.
另外，雖然本實施例的步驟S200包括對摻雜區112施加第一讀取電壓Vd2 ，但是本發明並不限於此。在其他實施例中，步驟S200也可以是對摻雜區114施加第一讀取電壓Vd2 ，以判斷第一儲存位置P1與第二儲存位置P2的位準是否皆為最低位準。Further, although the step S200 of the present embodiment includes applying a first read voltage V d2 doped region 112, but the present invention is not limited thereto. In other embodiments, step S200 may also apply a first read voltage V d2 to the doped region 114 to determine whether the levels of the first storage location P1 and the second storage location P2 are all at the lowest level.
接著，請同時參照圖2及圖3B，在步驟S300中，對鄰近於第一儲存位置P1的摻雜區112施加低於標準讀取電壓Vd1 的第二讀取電壓Vd3 ，以判斷第二儲存位置P2的位準。此步驟S300包括對基底102施加0 V，對控制閘極110施加閘極電壓Vg ，對摻雜區114施加0 V以及對摻雜區112施加第二讀取電壓Vd3 。如此一來，即可藉由讀取到的電流值來判斷第二儲存位置P2的位準。Next, referring to FIG. 2 and FIG. 3B simultaneously, in step S300, a second read voltage V d3 lower than the standard read voltage V d1 is applied to the doping region 112 adjacent to the first storage location P1 to determine the first The level of the second storage location P2. This step S300 includes applying 0 V to the substrate 102, applying a gate voltage V g to the control gate 110, applying 0 V to the doped region 114, and applying a second read voltage V d3 to the doped region 112. In this way, the level of the second storage location P2 can be determined by the read current value.
詳細而言，由於本實施例的操作方法是用以讀取第一儲存位置P1的位準，因此在步驟S300中，若根據讀取到的電流值判斷第二儲存位置P2的位準為最低位準時，則繼續進行步驟S400。相反地，若根據讀取到的電流值判斷第二儲存位置P2的位準不為最低位準時，則繼續進行步驟S500。In detail, since the operation method of the embodiment is to read the level of the first storage location P1, in step S300, if the read current value is used, the level of the second storage location P2 is determined to be the lowest. When the level is correct, step S400 is continued. Conversely, if it is determined that the level of the second storage position P2 is not the lowest level based on the read current value, then step S500 is continued.
另外，在步驟S300中，雖然已確定第一儲存位置P1與第二儲存位置P2的位準不同時為最低位準，但第一儲存位置P1的位準仍可能為最低位準。鑒於此，透過對摻雜區112施加低於標準讀取電壓Vd1 的第二讀取電壓Vd3 ，可以避免當第一儲存位置P1的位準為最低位準時所產生的電流導致讀取干擾。換言之，在步驟S300中，可在避免發生讀取干擾的情況下，判斷出第二儲存位置P2的位準。In addition, in step S300, although it is determined that the levels of the first storage location P1 and the second storage location P2 are different, the level of the first storage location P1 may still be the lowest level. In view of this, by applying a second read voltage V d3 lower than the standard read voltage V d1 to the doping region 112 , it is possible to avoid the read current caused by the current generated when the level of the first storage position P1 is the lowest level. . In other words, in step S300, the level of the second storage location P2 can be determined without avoiding occurrence of read disturb.
在一實施例中，第二讀取電壓Vd3 為標準讀取電壓Vd1 的1/2至2/3。此外，在一實施例中，閘極電壓Vg 例如是3.5至4.5 V，標準讀取電壓Vd1 例如是1.1 V至1.8 V以及第二讀取電壓Vd3 例如是0.5 V至1.1 V。然而，本發明並不以所揭露的為限。前述各電壓值可根據實際上所使用之多階記憶體的類型及架構等而有所調整，只要可準確判斷第二儲存位置P2的位準即可。In an embodiment, the second read voltage V d3 is 1/2 to 2/3 of the standard read voltage V d1 . Further, in an embodiment, the gate voltage V g is, for example, 3.5 to 4.5 V, the standard read voltage V d1 is, for example, 1.1 V to 1.8 V, and the second read voltage V d3 is, for example, 0.5 V to 1.1 V. However, the invention is not limited to the disclosed. The foregoing voltage values may be adjusted according to the type and architecture of the multi-level memory actually used, as long as the level of the second storage location P2 can be accurately determined.
接著，請同時參照圖2及圖3C，在步驟S400中，對鄰近於第二儲存位置P2的摻雜區114施加低於標準讀取電壓Vd1 的第三讀取電壓Vd4 ，以判斷第一儲存位置P1的位準。此步驟S400包括對基底102施加0 V，對控制閘極110施加閘極電壓Vg ，對摻雜區114施加第三讀取電壓Vd4 以及對摻雜區112施加0 V。如此一來，即可藉由讀取到的電流值來判斷第一儲存位置P1的位準。Next, referring to FIG. 2 and FIG. 3C simultaneously, in step S400, a third read voltage V d4 lower than the standard read voltage V d1 is applied to the doping region 114 adjacent to the second storage location P2 to determine the first The level of a storage location P1. This step S400 includes applying 0 V to the substrate 102, applying a gate voltage V g to the control gate 110, applying a third read voltage V d4 to the doped region 114, and applying 0 V to the doped region 112. In this way, the level of the first storage location P1 can be determined by the read current value.
詳細而言，在已知第二儲存位置P2的位準為最低位準的情況下，透過對摻雜區114施加低於標準讀取電壓Vd1 的第三讀取電壓Vd4 ，即可避免讀取干擾對讀取操作造成影響，進而準確判斷出第一儲存位置P1的位準。In detail, in the case where the level of the second storage location P2 is known to be the lowest level, by applying a third read voltage V d4 lower than the standard read voltage V d1 to the doping region 114, it can be avoided. The read interference affects the read operation, and the level of the first storage location P1 is accurately determined.
在一實施例中，第三讀取電壓Vd4 為標準讀取電壓Vd1 的1/2至2/3。此外，在一實施例中，閘極電壓Vg 例如是3.5至4.5 V，標準讀取電壓Vd1 例如是1.1 V至1.8 V以及第三讀取電壓Vd4 例如是0.5 V至1.1 V。然而，本發明並不以所揭露的為限。前述各電壓值可根據實際上所使用之多階記憶體的類型及架構等而有所調整，只要可準確判斷第一儲存位置P1的位準即可。In an embodiment, the third read voltage V d4 is 1/2 to 2/3 of the standard read voltage V d1 . Further, in an embodiment, the gate voltage V g is, for example, 3.5 to 4.5 V, the standard read voltage V d1 is, for example, 1.1 V to 1.8 V, and the third read voltage V d4 is, for example, 0.5 V to 1.1 V. However, the invention is not limited to the disclosed. The foregoing voltage values may be adjusted according to the type and architecture of the multi-level memory actually used, as long as the level of the first storage location P1 can be accurately determined.
接著，請同時參照圖2及圖3D，在步驟S500中，對鄰近於第二儲存位置P2的摻雜區114施加標準讀取電壓Vd1 ，以判斷第一儲存位置P1的位準。此步驟S500包括對基底102施加0 V，對控制閘極110施加閘極電壓Vg ，對摻雜區114施加標準讀取電壓Vd1 以及對摻雜區112施加0 V。如此一來，即可藉由讀取到的電流值來判斷第一儲存位置P1的位準。Next, referring to FIG. 2 and FIG. 3D simultaneously, in step S500, a standard read voltage V d1 is applied to the doping region 114 adjacent to the second storage location P2 to determine the level of the first storage location P1. This step S500 includes applying 0 V to the substrate 102, applying a gate voltage V g to the control gate 110, applying a standard read voltage V d1 to the doped region 114, and applying 0 V to the doped region 112. In this way, the level of the first storage location P1 can be determined by the read current value.
詳細而言，在已知第二儲存位置P2的位準不是最低位準的情況下，施加標準讀取電壓Vd1 後所產生的電流會低於第二儲存位置P2的位準為最低位準時的電流，因此可有效地減少讀取干擾的發生，進而可避免讀取干擾對讀取操作造成影響。In detail, in the case where the level of the second storage position P2 is known not to be the lowest level, the current generated after the application of the standard read voltage V d1 is lower than the level of the second storage position P2 is the lowest level. The current is therefore effective in reducing the occurrence of read disturbances, thereby preventing read disturbs from affecting the read operation.
在一實施例中，步驟S500中的閘極電壓Vg 例如是3.5至4.5 V，以及標準讀取電壓Vd1 例如是1.1 V至1.8 V。然而，本發明並不以所揭露的為限。前述電壓值可根據實際上所使用之多階記憶體的類型及架構等而有所調整，只要可準確判斷第一儲存位置P1的位準即可。In an embodiment, the gate voltage V g in step S500 is, for example, 3.5 to 4.5 V, and the standard read voltage V d1 is, for example, 1.1 V to 1.8 V. However, the invention is not limited to the disclosed. The voltage value may be adjusted according to the type and architecture of the multi-level memory actually used, as long as the level of the first storage location P1 can be accurately determined.
綜上所述，在上述實施例所提出之多階記憶體的操作方法中，透過先以第一讀取電壓Vd2 進行讀取操作來排除第一儲存位置P1與第二儲存位置P2的位準皆為最低位準的情況後，再以第二讀取電壓Vd3 判斷第二儲存位置P2的位準，並針對第二儲存位置P2的位準調整所施加的電壓，使得可在有效避免讀取干擾對讀取操作造成影響的情況下讀取第一儲存位置P1的位準。In summary, in the operation method of the multi-level memory provided in the above embodiment, the bits of the first storage location P1 and the second storage location P2 are excluded by performing a read operation with the first read voltage V d2 first. After the condition of being the lowest level, the level of the second storage position P2 is determined by the second read voltage Vd3 , and the applied voltage is adjusted for the level of the second storage position P2, so that the effective avoidance can be effectively avoided. The level of the first storage location P1 is read in the case where the read disturb affects the read operation.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧多階記憶體100‧‧‧Multi-level memory
102‧‧‧基底
104‧‧‧底氧化層
106‧‧‧氮化矽層
108‧‧‧頂氧化層
110‧‧‧控制閘極
112、114‧‧‧摻雜區
120‧‧‧電荷儲存層
P1、P2‧‧‧儲存位置
S200、S300、S400、S500‧‧‧步驟102‧‧‧Base
104‧‧‧ bottom oxide layer
106‧‧‧layer of tantalum nitride
108‧‧‧Top oxide layer
110‧‧‧Control gate
112, 114‧‧‧Doped area
120‧‧‧Charge storage layer
P1, P2‧‧‧ storage location
S200, S300, S400, S500‧‧‧ steps
圖1是本發明之一實施例的多階記憶體的示意圖。圖2是本發明一實施例之多階記憶體的操作流程圖。圖3A及圖3D分別是於圖2之不同操作步驟中之多階記憶體的示意圖。1 is a schematic diagram of a multi-level memory of an embodiment of the present invention. 2 is a flow chart showing the operation of the multi-level memory according to an embodiment of the present invention. 3A and 3D are schematic views of multi-level memory in different operation steps of FIG. 2, respectively.
S200、S300、S400、S500‧‧‧步驟S200, S300, S400, S500‧‧‧ steps
Claims (11)
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| TW200620312A (en) * | 2004-12-15 | 2006-06-16 | Samsung Electronics Co Ltd | Multi-level cell memory device and associated read method |
| US7471568B2 (en) * | 2006-06-21 | 2008-12-30 | Macronix International Co., Ltd. | Multi-level cell memory structures with enlarged second bit operation window |
| TW201118876A (en) * | 2009-11-20 | 2011-06-01 | Ind Tech Res Inst | Voltage compensation circuit, multi-level memory device with the same, and voltage compensation method for reading the multi-level memory device |
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| TW200620312A (en) * | 2004-12-15 | 2006-06-16 | Samsung Electronics Co Ltd | Multi-level cell memory device and associated read method |
| TWI267088B (en) * | 2004-12-15 | 2006-11-21 | Samsung Electronics Co Ltd | Multi-level cell memory device and associated read method |
| US7471568B2 (en) * | 2006-06-21 | 2008-12-30 | Macronix International Co., Ltd. | Multi-level cell memory structures with enlarged second bit operation window |
| TW201118876A (en) * | 2009-11-20 | 2011-06-01 | Ind Tech Res Inst | Voltage compensation circuit, multi-level memory device with the same, and voltage compensation method for reading the multi-level memory device |
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