TWI511453B - Power controlling integrated circuit and retention switching circuit - Google Patents

Description

Power control integrated circuit and hold switching circuit

The present invention relates to the field of integrated circuits. More particularly, the present invention relates to a power control integrated circuit, a hold integrated circuit, and a corresponding standard circuit unit.

It is currently known to provide a voltage switching device for integrating a voltage supply input to a voltage supply output in response to a power control signal. This voltage switching device is an element that is useful for all kinds of integrated circuits.

Modern integrated circuits include: a system-on-a-chip (SoC) design with approximately millions of transistor gates. The design and manufacture of this complex on-wafer system circuit is typically accomplished using the use of Computer Aided Design tools and the use of standard cell libraries that include: providing representations of different types of logic gates (eg Standard sub-components of AND, NAND, XOR), or interconnection structures of storage functions (such as flip-flops and latches) and transistors. Thus, the standard cell approach helps circuit designers adjust application-specific integrated circuits (ASICs) from relatively simple single-function integrated circuits containing thousands of gates to complex multi-million gate on-system devices.

As the complexity of system design on a wafer increases, circuit performance characteristics (such as dynamic and leakage power protection) are becoming increasingly important to drive extended battery life and also reduce system manufacturing costs.

Thus, dynamic and leakage power reduction is a key focus for circuit designers. The dynamic power is reduced by reducing the operating voltage of a particular block or section of the entire wafer or a wafer, and the voltage portions of the respective wafers can be implemented by using a potential quasi-positioner. However, the reduction in the actual size of semiconductor components in modern integrated circuits has led to the trend of using lower threshold voltage circuit components, as this operation allows voltage switching to be performed more quickly. The decrease in the threshold voltage has a marginal effect of increasing the power consumption of the integrated circuit due to the increase in leakage current.

It is known to reduce the leakage power in the integrated circuit by, for example, turning off the circuit block of the integrated circuit, which uses the power gate on the chip to switch the circuit blocks to the power supply or Grounding, and the isolation gate between components within the circuit, avoids floating input or output increases when portions of the integrated circuit are turned off, and otherwise cause other unpredictable or incorrect operations. However, maintaining the state of some of the wafer components is necessary when closing portions of the wafer. This can be done by using a hold flipper and a hold latch. This state retention mechanism sometimes uses what is referred to as "balloon latches."

While previously known techniques have been quite effective in reducing leakage current, it is necessary to support additional functional circuit components (such as balloon latches or retention latches) and circuit complexity and control routing. Typically there is a high associated burden. These factors generally result in the need to increase the circuit die area. Thus, previously known power control mechanisms can reduce leakage currents, which at the same time leads to new complications and burdens when manufacturing circuits incorporating this mechanism. Accordingly, there is a need for a power control integrated circuit that provides a reduction in leakage current when the integrated circuit is turned off or when operating in the data holding mode, and reduces the load associated with the leakage current reducing circuit.

According to a first aspect, the present invention provides a power control integrated circuit comprising: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output is switched Is coupled to the voltage supply input in response to a power control input signal such that in a power swing configuration of the voltage switching device, the voltage supply output is coupled to the voltage supply input; a hold switching device (120, 220) And coupled to the voltage switching device and configured to switchably couple the voltage supply output to the voltage supply input in response to a hold enable signal to cause a hold enable group in the hold switching device In the state, the voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input; wherein the hold switching device (120, 220) has an additional voltage input from an overdrive voltage supply (Vod, Vssod) such that In the hold enable configuration, the hold switching device is driven relative to the voltage supply input signal and the voltage supply input signal. Powered on, and in a power-off configuration of the voltage switching device, the voltage supply output is determined by the hold switching device.

The present invention recognizes that a voltage switching device can be provided with reduced leakage by arranging the holding switching device to be coupled to the voltage supply input and also coupled to an overdrive voltage supply in response to a hold enable signal A hold-for switching device for current. In a hold-enabled configuration, the hold switching device is enabled to be relatively powerful with respect to being coupled to a separate voltage input supply signal and driven by a separate voltage input supply signal. When the voltage switching device is in a power-off configuration, the voltage supply output of the voltage switching device can be determined by the state of the holding switching device, thereby providing a reduction and sufficient maintenance compared to the voltage supply input. A holding voltage connected to the logic state of the voltage supply output.

The supply of the overdrive hold switching device allows for the implementation of a low latency and low leakage hold mode that does not require software to store the logic connected to the voltage output, as well as reduced power and previous known retention mechanisms (eg, balloon latching) ()) associated circuit area requirements. Furthermore, in addition to the balloon latch for reducing the leakage of the circuit components of the balloon latch itself, an overdrive holding switching device in accordance with the teachings of the present invention can be used. By overdriving the hold switching device, the switching device can be turned on more powerfully than being coupled to only one voltage supply input. This allows the switching device to be kept downsized (area) while still supplying the logic demand holding voltage connected to the voltage supply output. The size reduction of the overdrive from the holding switching device reduces the leakage current when the power control integrated circuit operates in a power off configuration. It also reduces the current demand relative to a holding switching device that has not been driven. The circuit area burden of the holding switching device is small when compared with the circuit area of the voltage switching device itself, so the area burden associated with providing the holding function is reduced.

It should be understood that the voltage switching device of the power control integrated circuit can take several different forms. However, in one embodiment, the voltage switching device is a header switching device, wherein the voltage supply input corresponds to a positive supply voltage and the overdrive voltage supply is greater than the voltage supply input.

In an alternative embodiment, the voltage switching device is a footer switching device, wherein the voltage supply input corresponds to a ground voltage level and the overdrive voltage supply is lower than the voltage supply input. Such configurations motivate consideration of the characteristics of the transistor (e.g., Field Effect Transistor (FET)) whereby the NFETs perform voltage pull-downs more efficiently, while the PFETs perform voltage level pull-ups more efficiently.

It will be appreciated that the voltage switching device can be provided as a conventional voltage switching device that is only connected to the power supply input and the power supply output rather than the overdrive voltage supply. However, in some embodiments, the voltage switching device and the holding switching device are coupled to the overdrive voltage supply. In particular, in such embodiments, when one of the following occurs: (i) the voltage switching device is in the power-off configuration, and the holding switching device is configured such that the voltage supply output is from the The voltage supply input is decoupled; and (ii) the voltage switching device is in a power off configuration, and the hold switching device is configured such that the voltage supply output is coupled to the voltage supply input by the hold switching device, the voltage switching The device has an overdrive input for coupling the voltage switching device to the overdrive voltage supply. In these embodiments, overdrive of the voltage switching device (except for overdriving of the hold switching device) causes a power shutdown configuration at the power control integrated circuit to reduce leakage power by using the voltage A portion of the switching device is driven to be turned off by an input signal having a level of the voltage supply input level, and at least a portion of the voltage switching device is over-driven to a reduced state to reduce leakage current with respect to its presence.

It will be appreciated that the voltage switching device is coupled to the overdrive voltage supply by any of a number of different circuits, for example by using a half latch circuit or an inverter circuit. However, in some embodiments, the switching device is coupled to the overdrive voltage supply by a first voltage quasi-displacer, and the first voltage quasi-displacer is controlled by the power control input signal. . The power control input signal provides convenient digital control of the connection of the voltage switching device to an overdrive voltage. By contrast, previously known super cut-off circuits that provide voltage switching devices typically operate by an analog mechanism, such as analog adjustment of the transistor gate voltage of a voltage switch.

In some embodiments, the first voltage quasi-bit shifter that couples the overdrive voltage to the voltage switching device comprises: a first inverter. In other embodiments, the first voltage level shifter comprises: a half latch circuit. Both the inverter and the half latch are easy to implement and are manufactured at low cost.

In some embodiments, the first voltage quasi-bit shifter comprises: a first inverter, the first inverter comprising: a pair of stacked transistors biased by the input supply voltage. The use of a stacked transistor can utilize a "stack effect" called a transistor to eliminate the forward bias of the pull-up and the smoothness of the transistor well due to the connection of the switching device to the overdrive voltage supply. Any increased leakage caused by bias. Using a common well bias allows for a reduced area by avoiding well separation of actual design criteria.

Although the voltage supply input can be configured to be variable, and the overdrive voltage supply can be configured to have a predetermined value, in some embodiments, the voltage supply input is substantially a fixed input voltage, but can be grouped The drive voltage supply is oversized such that it can be selected from a range comprising a plurality of overdrive voltages. The step of causing the overdrive voltage to be selected from a range of different voltages provides flexibility in circuit performance characteristics to cause the user of the circuit to accurately adjust its performance to suit the particular desired performance characteristics.

It should be appreciated that the hold switching device can be coupled to the overdrive voltage supply in a variety of different manners by a number of different circuit arrangements, but in some embodiments, the hold switching device is biased by a second voltage A bit shifter is coupled to the overdrive voltage supply, and the second voltage quasi-displacer is controlled by a hold enable signal. The control of the second voltage quasi-positioner that implements the same hold enable signal of the hold enable mode of the power control integrated circuit provides for convenient digital control of both the hold mechanism and the leakage characteristic of the hold switching device. By buffering the control of the holding switching device by using the hold enable signal, the number of circuit elements that must be connected to the overdrive voltage supply can be reduced, and thus the adverse effects of the hold switching device on the circuit area can be reduced.

In some embodiments, the overdrive voltage is coupled to the hold switching device by the second voltage quasi-bit shifter, the second voltage quasi-bit shifter comprising: a second inverter. In a further alternative embodiment, the second voltage level shifter comprises: a half latch circuit. Such circuits are simple to implement and easy to manufacture.

In some embodiments, the second voltage quasi-bit shifter includes: a second inverter comprising: a pair of stacked transistors biased using an input supply voltage. The stacked transistor used in the second inverter eliminates any increased leakage effects that occur due to the inverter being connected to the overdrive voltage supply.

It will be appreciated that the voltage switching device and the holding switching device can be implemented as any type of switching device, such as any type of transistor. However, in some embodiments, at least one of the hold switching device and the voltage switching device comprises: a field effect transistor. The fabrication of such field effect transistors is relatively low cost and their characteristics are well understood.

In some embodiments of power control integrated circuits, an intrusion protection switching device is provided. This is controlled by the hold enable signal and is configured to block the "inrush" of the current when the power control integrated circuit is switched from a hold mode to a full power on mode. An intrusion protection switching device (e.g., a potential divider) can be used in this manner to eliminate effects due to sudden changes in current caused by the power control circuit transitioning from a hold mode to a full power on mode. The intrusion of current has the potential to drop the voltage at the voltage supply input. This voltage drop can in turn cause the logic elements connected to the voltage supply output to be lost in the data content maintained by the hold latches, which are in a hold mode prior to transitioning to the full power on mode. The step of providing an intrusion protection switching device to block the inrush current reduces the likelihood that the data held by the switching device will be abrupt due to a transition current associated with the hold enable signal and the power control input signal. Increase and lose.

In some embodiments, an intrusion protection switching device is provided to block intrusion of current when the power control integrated circuit switches from a hold mode to a full power on mode, the intrusion protection device being coupled to the voltage supply input and Between the inputs of the voltage switching device. This causes the intrusion protection switching device to act as a potential distributor that immediately drives the inrush current to be controlled. In some embodiments, the voltage switching device includes: a field effect transistor, and the input of the voltage switching device coupled to the intrusion protection switching device includes: a gate of the voltage switching device. Therefore, the voltage on the gate of the voltage switching device can be appropriately selected by adjusting the intrusion protection switching device so that the amount of current from the transistor of the voltage switching device can be reduced by the circuit designer to ensure Current intrusion does not cause hazard behavior such as loss of data maintained in the retention latch.

It should be appreciated that the intrusion protection switching device can include any one of a number of different circuit configurations, but in some embodiments, the intrusion protection switching device includes: the field effect power used in the voltage switching device One of the types of crystal matching, field effect transistor, which is one of PFET (Positive-channel field effect transistor and NFET (Negative-channel field effect transistor). This is Low cost implementation and easy control.

In some embodiments, an intrusion protection switching device is provided to the power control integrated circuit, the electrical characteristics of the intrusion protection switching device being balanced with respect to electrical characteristics of the voltage switching device to be based on the hold mode and the full power on mode The transition between the blocks prevents the intrusion of current.

In some embodiments, the power control integrated circuit coupled between the holding switching device and the overdrive voltage supply affects operation through a first voltage quasi-positioner controlled by the power control input signal, the circuit further The method includes: a first buffer circuit component coupled to an output of the first voltage quasi-bit shifter, and configured to: buffer the power control input signal. The step of buffering the power control input signal in this manner causes the first buffer circuit to be conveniently controlled by the same control input as the voltage switching device itself. This would cause the buffer to be an always-on buffer, and thus reduce the leakage current when the power gate is in the super cut-off mode. Furthermore, the first buffer circuit component is provided adjacent to the entity of the first voltage quasi-displacer to cause the first buffer circuit component to be driven from a voltage rail of the voltage quasi-displacer itself Its power supply. By arranging the snubber circuit component to respond to the voltage supply output (due to its control by the power control input signal) to allow the power control input signal to drive the voltage switching device to turn on and to transmit the power control input signal as a buffer The power controls the delay between the snubber circuit elements of the input signal. This reduces peak current and thus power surge.

In some embodiments, the first buffer circuit component is powered by the electrical supply input. This convenient mechanism is provided in this way to power the buffer.

In a specific embodiment of the power control integrated circuit, the hold switching device is coupled to the overdrive voltage supply through a second voltage level shifter controlled by the hold enable signal, the circuit further comprising: A second buffer circuit component coupled to an output of the second voltage level shifter and configured to buffer the hold enable signal. This reduces the leakage that would increase (for example, if an always-on buffer is provided for buffering the hold enable signal), and the power supply of the second buffer circuit component is conveniently shifted from the second voltage. A voltage rail of the device itself is guided out. It also provides a similar reduction in current surge to the reduction provided by the buffering of the first buffer circuit component with respect to the power control input signal. In these embodiments, the second buffer circuit component is powered by the voltage supply input of the voltage switching device.

According to a second aspect, the present invention provides a power control integrated circuit for forming a portion of an integrated circuit, the power control integrated circuit unit comprising: a voltage switching device having a voltage supply input (Vin) And a voltage supply output (Vout), wherein the power supply output is switchably coupled to the voltage supply input in response to a power control input signal such that in a power swing configuration of the voltage switching device, the voltage a supply output coupled to the voltage supply input; wherein the voltage switching device has an additional voltage input from an overdrive voltage supply such that when the voltage switching device is in a power off configuration, wherein the voltage supply is output from the voltage The supply input is decoupled, and the voltage switching device is coupled to the voltage supply input signal and driven by the voltage supply input signal, and is more effectively turned off.

According to an aspect of the invention, it is possible to identify a supply of a power control integrated circuit having a standard unit form, the power control integrated circuit comprising: a voltage supply input and a voltage supply output in the standard unit itself In conjunction with the connection of the voltage switching device to the overdrive voltage supply, providing a convenient circuit building block and supplying a reduced leakage due to the fact that the voltage switching device is more effectively closed due to its connection to the overdrive voltage supply Current.

According to a third aspect, the present invention provides a power control integrated circuit comprising: a hold switching device having: a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output Switchingly coupled to the voltage supply input in response to a hold enable signal such that when the coupling is caused, the voltage supply output corresponds to a reduced hold voltage relative to the voltage supply input; wherein the hold switching device has: An input from an overdrive voltage supply is enabled to enable a more powerful turn-on with respect to coupling to the voltage supply input signal and from the voltage supply input signal when the hold switching device is enabled.

In accordance with this aspect, the present invention recognizes that a hold switching device coupled to an overdrive voltage supply can be provided that enables the hold switching device to be coupled to the separate voltage supply input signal relative to the hold switching device and by a separate The voltage is supplied by the input signal and is turned on more powerfully. This causes a reduction in leakage current in a hold mode. Although it has been conventionally known to use "super cut-off" and "boosted-gate" to voltage switching devices, the overdrive of a hold switching device in accordance with the teachings of the present invention has not previously been shown and has not previously been identified. The advantage of reducing the leakage current.

According to a fourth aspect, the present invention provides a computer readable storage medium storing a data structure, the data structure comprising: a standard unit circuit definition for controlling a computer to generate and verify a circuit of an integrated circuit a circuit configuration of the unit, the circuit unit comprising: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), wherein the voltage supply output is switchably coupled to the voltage supply input in response The power input signal is controlled such that in a power swing configuration of the voltage switching device, the voltage supply output is coupled to the voltage supply input; a hold switching device coupled to the voltage switching device, and a state Switching the voltage supply output to the voltage supply input in response to a hold enable signal such that in the hold enable configuration of the hold enable device, the voltage supply output corresponds to the voltage supply input a reduced holding voltage; wherein the holding switching device (120, 220) has an additional from an overdrive voltage supply (Vod, Vssod) Voltage input, such that in the hold enable configuration, the hold switching device is relatively powerfully enabled with respect to being coupled to the voltage supply input signal and driven by the voltage supply input signal, and the power at the voltage switching device In the off configuration, the voltage supply output is determined by the hold switching device.

According to a fifth aspect, the present invention provides a computer readable storage medium storing a data structure, the data structure comprising: a standard unit circuit definition for controlling a computer to generate and verify a circuit of an integrated circuit a circuit configuration of the unit, the circuit unit comprising: a hold switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output is switchably coupled to the voltage supply input in response The enable signal is maintained such that when the coupling is caused, the output voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input; wherein the hold switching device has: a supply from an overdrive voltage supply The input is such that when the switching device is enabled, it is more powerfully turned on relative to the voltage supply input signal and from the voltage supply input signal.

Implementing the power control integrated circuit as a standard circuit unit including both a voltage switching device and an overdrive maintaining switching device, and also supplying a standard unit including an overdrive holding switching device without the voltage switching device The advantage of having only digital control without the need for an external quasi-positioner is revealed, thus reducing the burden of both deployment and verification of existing electronic design automation tools.

According to a sixth aspect, the present invention provides a computer implementable method of designing an integrated circuit comprising the steps of: selecting at least one standard cell from a standard cell database, and incorporating the at least one standard in the integrated circuit Unit, the at least one standard unit comprising: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output is switchably coupled to the voltage supply input in response to a power control input signal such that in a power swing configuration of the voltage switching device, the voltage supply output is coupled to the voltage supply input; a hold switching device (120, 220) coupled to the voltage switching device, and Configuring to switchably couple the voltage supply output to the voltage supply input in response to a hold enable signal such that in a hold enabled configuration of the hold switching device, the voltage supply output corresponds to the voltage The supply input is a reduced hold voltage; wherein the hold switching device (120, 220) has an additional from an overdrive voltage supply (Vod, Vssod) Voltage input such that in the hold enable configuration, the hold switching device is relatively powerfully activated relative to the voltage supply input signal coupled to and output by the voltage supply, and wherein the voltage switching device is In a power-off configuration, the voltage supply output is determined by the hold switching device.

According to a seventh aspect, the present invention provides a computer implementable method of designing an integrated circuit, comprising the steps of: selecting at least one standard cell from a standard cell database, and incorporating the at least one in the integrated circuit a standard unit, the at least one standard unit comprising: a hold switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output is switchably coupled to the voltage supply input in response Maintaining the enable signal such that when the coupling is caused, the voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input; wherein the hold switching device has an input from an overdrive voltage supply to When the switching device is enabled, it is more powerfully turned on with respect to being coupled to the voltage supply input signal and driving from the voltage supply input signal.

According to an eighth aspect, the present invention provides a computer implementable method of designing an integrated circuit, comprising the steps of: selecting at least one standard cell from a standard cell database, and incorporating the at least one in the integrated circuit a standard unit, the at least one standard unit comprising: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the power supply output is switchably coupled to the voltage supply input in response The input signal is controlled by a power such that in the power-up configuration of the voltage switching device, the voltage supply output is coupled to the voltage supply input; wherein the voltage switching device has an additional voltage input from an overdrive voltage supply So that when the voltage switching device is in a power-off configuration, wherein the voltage supply output is decoupled from the voltage supply input, the voltage switching device is coupled to the voltage supply input signal and by the voltage relative to the voltage switching device Supply input signal drive, more powerfully shut down.

According to a ninth aspect, the present invention provides a method of providing power control in an integrated circuit, the method comprising the steps of: switchably coupling a voltage supply input of a voltage switching device in response to a power control Inputting a signal such that in a power-on configuration of the voltage switching device, a voltage supply output of the switching device is coupled to the voltage supply input; switching the coupling using a holding switching device coupled to the voltage switching device And outputting a voltage supply to the voltage supply input in response to a hold enable signal such that in the hold enable configuration of the hold switching device, the voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input Wherein the hold switching device (120, 220) has an additional voltage input from an overdrive voltage supply (Vod, Vssod) such that in the hold enable configuration, the hold switching device is coupled to the voltage supply input The signal and the input signal driven by the voltage supply are relatively powerfully turned on, and the work in the voltage switching device Closed configuration, the output of the voltage supply lines is determined by the holding switching means.

According to a tenth aspect, the present invention provides a method of providing power control in an integrated circuit, the method comprising the steps of: switchingly coupling a voltage supply output of a switching device to a voltage of the voltage switching device Supplying an input in response to a hold enable signal such that when the coupling is caused, the voltage supply output corresponds to a reduced hold voltage relative to the voltage supply input; wherein the hold switching device has: from an overdrive voltage An input is provided such that when the switching device is enabled, it is more energized to be turned on relative to the voltage supply input signal and from the voltage supply input signal.

The foregoing and other objects, features, and advantages of the invention will be apparent from the embodiments of the invention.

Fig. 1A schematically illustrates a power control integrated circuit unit which forms part of an integrated circuit in accordance with a first embodiment of the present invention. The integrated circuit can be implemented, for example, as a standard unit in a standard cell library for controlling a computer to generate and verify a circuit configuration of at least a portion of an integrated circuit. The standard cell entity, which defines the characteristics of a corresponding solid volume circuit unit, can be provided as a single or a decentralized data structure stored on a computer readable storage medium.

The circuit of Figure 1A includes: a voltage switching device comprising: a PFET transistor 130 coupled to a voltage supply input Vin and a voltage supply output Vout. This type of voltage switching device is a conventional "header" switching device in which the input supply voltage Vin corresponds to a positive supply voltage. As will be described hereinafter, a different type of power switching device conventionally known as a "footer" switching device will be illustrated in Figures 2A-2C. The voltage switching device 130 is coupled to a holding device 120 that includes an NFET transistor 120. In addition to the voltage switching device 130 and the holding device 120, the circuit of FIG. 1A includes: a first inverter 132 comprising: a pair of stacked PFET transistors 140, 145, The body-biased is used to supply the voltage Vin, and is also an NFET transistor 135.

The first inverter 132 is a specific implementation of a voltage quasi-displacer for coupling the header voltage switching device 130 with an overdrive supply voltage from an overdrive voltage rail 152. Vod. The first inverter 132 is controlled by a power control input signal nSLEEP that controls the state of the inverter 132 and whether the voltage switching device 130 is coupled to the overdrive voltage rail 152. The power control integrated circuit of Figure 1A further includes a second inverter 102, which is a particular implementation of a voltage shifting device. In alternative embodiments, other types of voltage shifting devices are used. The second inverter 102 is controlled by a hold control input signal nRET, which controls the following: the state of the inverter 102 and whether the hold switching device 120 is coupled to the overdrive voltage power rail 152 to The voltage supply output Vout is switchably coupled to the voltage supply input Vin in response to the hold enable signal "nRET".

In a hold enable configuration of the hold switching device 120, the voltage supply output Vout corresponds to a hold voltage that is reduced relative to the voltage supply input Vin.

The hold switching device 120 is coupled to the overdrive voltage rail 152 (and to Vin) such that in a hold enable configuration, the hold switching device 120 is coupled to the voltage supply input signal Vin and This voltage supply is more powerful when the input signal Vin is driven to the extent that it is strongly turned on. As shown in FIGS. 1B and 1C, which will be described later, in the power-off configuration of the switching device 130, the voltage supply output Vout is determined by the state of the holding switching device 120.

In the header power control integrated circuit of FIG. 1A, it can be observed that the pair of PFET transistors 140, 145 of the first inverter 132 are spliced such that they can be biased by the voltage supply input Vin body. . Similarly, the pair of PFET transistors 105, 110 of the second inverter 102 are spliced such that they can be biased by the Vin body. The step of biasing the PFET transistors with Vin reduces the cell area of the integrated circuit of Figure 1A, and stacks the two PFET transistors to eliminate the leakage current when the device is turned off.

The second inverter 102 is identical to the first inverter 132, but is provided to the holding device 120 rather than to the header voltage switching device 130.

The hold switching device 120 provides a reduced voltage suitable for: when the nSLEEP and the nRET signal have a value displayed, for example, in the circuit of FIG. 1C (eg, when the power control input signal nSLEEP is When the logic 0 potential and the hold enable signal nRET are at a logic 0 potential, the memory device coupled to Vout is maintained in a hold state. It should be appreciated that the polarity of the logic signal that needs to be derived from the power-on state, the power-off state, and the hold state depends on the particular circuit configuration, and therefore a particular one of the three states is required to be derived. The polarity of the logic signal can be different than that described in the specific embodiment.

The specific embodiment of FIG. 1A shows the header switching 130 and the holding switching device 120 in a power-on configuration, wherein the power control input signal nSLEEP is a logic 1 potential and the sustain enable signal nRET is a logic 1 Potential. In this case, the PFETs 140, 145 of the first inverter 132 are all turned off, and the NFET transistor 135 of the first inverter 132 is turned on. As a result, the PFET 130 of the header voltage switching device is connected to the ground voltage rail 150 and turned on. Because the hold enable signal is a logic one potential, when the NFET 115 of the second inverter 102 is turned on, the PFETs 105, 110 of the second inverter 102 are turned off. Thus, the holding device NFET 120 is coupled to the ground voltage rail 150 and is turned off. Thus, the overall configuration of the circuit of Figure 1A: Vout is coupled to Vin, and in this mode, any logic device (not shown) powered by the Vout signal operates in a full power on mode. Although in the embodiment of FIG. 1A, the first voltage level switch 132 and the second voltage level shifter 102 are implemented as inverters, in alternative embodiments, other types may be implemented. The voltage quasi-positioner has the same effect. For example, a stacked inverter or a cross-coupled quasi-positioner or half-lock can be used, and other alternatives are also possible.

The circuit of Fig. 1A (and all the circuits of Figs. 1B to 5 described later in the example) are implemented as "standard cells". In semiconductor design, it is known to use a so-called "standard cell" approach to design specific application integrated circuits (ASICs) that contain digital logic features. A standard cell represents an extraction of a low level very large integrated (VLSI) configuration that is enclosed in an extracted logic gate representation such as a logic gate (eg, AND gate, OR gate). The package of detailed circuit configurations in a standard cell hides the details of a transistor level, but makes them available to circuit designers at both a logic and a functional level. This allows the circuit to be designed such that when another engineer who builds the standard cell focuses on the physical level of the transistor level implementation and circuit design, an engineer concentrates by combining a plurality of standard cells to form a monolithic circuit. The logical functional level of digital design. This has led to the function of a system on a wafer containing millions of transistor gates.

The standard cell definition may specify characteristics of the standard cell circuit itself, including at least one of: timing characteristics, logic functions, physical interface characteristics of the circuit, and electrical interface characteristics. The data structure representing the standard unit may be a single data structure or a decentralized data structure, the data structure(s) representing a set of transistors and interconnect structures providing Boolean logic functions, such as AND, OR, XOR gates Or an inverter or a storage function (such as a flip-flop or a latch). In accordance with the teachings of the present invention, a power control integrated circuit and/or a holding circuit can be provided as a standard unit. The storage medium on which the standard unit is located may be non-transitory, and it should be understood that the storage medium may include: multiple storage media in the case of a distributed data structure.

A further standard cell can be initially created at a transistor level in the form of a transistor "netlist", which is a mode description by means of transistors and connections to each other and their endpoints to the external environment. One mode. In order to obtain an extracted version of the standard unit, a design program such as SPICE (Simulation Program with Integrated Circuit Emphasis) is described in SPICE (Simulation Program with Integrated Circuit Emphasis) Memorandum No. ERL-M 382, University of California, Berkeley, In April 1973, Nagel and Pederson used to simulate the electronic behavior of the standard cell netlist by declaring an input stimulus (such as voltage) and then calculating the response of the circuit. This SPICE simulation verifies that the netlist implementation and the requested functionality meet the power consumption or signal propagation delay requirements.

An entity representation of the standard unit is generated for the purpose of device manufacture. The standard cell configuration view is close to the manufacturing blueprint from the standard cell and the base layer organized as interconnecting lines corresponding to different structures of the transistor device and end points formed in conjunction with the transistor. Engineers have the task of efficiently manufacturing a standard cell configuration by considering manufacturing costs, and this can be accomplished by minimizing circuit deadband and ensuring compliance with standard cell speed and power efficiency requirements.

A "standard cell library", as is known in the prior art, is a collection of low-level logic functions, flip-flops, latches, and buffers. These standard units are available as fixed height, variable width units. The fixed height allows the standard cells to be arranged in rows to facilitate automatic digital configuration. Standard cells within a standard database are typically designed to reduce the configuration view of the standard cells of the delay and circuit area. The key components of the standard cell database are (i) providing functional definition of each standard cell, timing, and timing extraction of noise information, and (ii) configuration extraction, which includes: placement and winding by the circuit used Reduced information on standard cell configurations used by computer-aided design tools. An example of a standard cell database is the ARM Standard Cell Database, which provides a platform for designing all types of on-wafer system designs. Circuit designers can choose between different standard cell library types and optimize their design for their speed, power, and/or region. The ARM standard cell library can be used, for example, from a 28 nm node to a 250 nm node.

Several SPICE simulations can be performed on the circuit, such as the circuit illustrated in Figure 1A. In the circuit of FIG. 1A, an inverter 132 (which may be powered by a higher (overdrive) voltage supply Vod) may be used to drive the gate of the PFET 130 of the header voltage switching device to be one compared to Vin. Higher voltage and reduced width required by 130. The SPICE simulation in a low-power 32nm process shows that the reduction in width and thus the leakage current can reach 50 with respect to a header voltage switch that is not connected (via a quasi-positioner) to an overdrive voltage supply. Times.

One complexity of using a voltage quasi-positioner to connect the voltage switching device to an overdrive voltage supply is that the N-well or buffer of any inverter powered by the overdrive voltage (Vod) should be connected to A high supply voltage, which in turn requires hot N-well separation to be observed, and thus results in a larger germanium area and increased manufacturing costs. Alternatively, the left side forward biased inverter or retarder may result in an increase in leakage. However, in the arrangement of Figure 1A, by providing control from the regular power supply Vin to the overvoltage Vod, the number of inverters supplied in overdrive can be reduced by: reducing the forward bias Press to eliminate the cost of any effect that increases the dead zone of the circuit.

With regard to the holding device 120 of Figure 1A, the NFET can be configured to provide a diode drop across the physical rail to provide a zero delay leakage hold mode that does not require software to store any state. This is more regionally efficient than, for example, the previously known balloon latches for storing circuit states in a hold mode. The hold enable signal "nRET" of Figure 1A can be used to control whether the gate of NFET 120 is overdriven. The gate of NFET 120 is overdriven only in the hold mode as shown in Figure 1C. When NFET 120 is connected to overdrive voltage rail 152, it opens more forcefully, meaning that it can supply more current. This in turn means that it can be reduced in size and still supply the required holding voltage to maintain the circuit state.

Unless attention is paid to the design of the quasi-displacer, the leakage caused by the forward bias is exacerbated by the gate-to-overdrive voltage of the drive circuit. For example, conventional techniques for a semi-bolt lock displacement device help to eliminate this effect.

FIG. 1B schematically illustrates a power control integrated circuit including a header voltage switching device in accordance with an embodiment of the present invention. The circuit component of FIG. 1B is identical to the circuit component of FIG. 1A, and in this case, the power control input signal NSLEEP and the hold enable signal nRET have values that cause the integrated circuit to be in a power-off configuration. In this particular implementation, the power-off configuration corresponds to the power control signal nSLEEP having a value of a logic zero potential and a hold enable signal nRET having a logic value of one potential. With such input signal values, the PFET transistors 140, 145 of the first inverter are both turned on, and the NFET 135 of the first inverter is turned off. The effect of the opening of the two PFETs 140, 145 is that the voltage supply input rail Vin is coupled to the overdrive voltage rail 152. Therefore, the PFET 130 of the header voltage switching device is turned off and overdriven in the off state so that it is in a "super cut-off" state.

Overdriving the PFET device 130 in this off state can reduce leakage current that would exist if the PFET device 130 was driven off by an input signal only at the Vin voltage level and not at the overdrive voltage level Vod. Since the hold enable signal nRET is a logic one potential, when the NFET 115 of the second inverter is turned on, both of the PFETs 105, 110 are turned off. This means that the hold switching device 120 is turned off. Because in this configuration, both the holding device NFET 120 and the PFET 130 header voltage switching device are turned off, the output signal Vout is no longer coupled to the voltage supply input Vin. In this configuration, the output on the Vout signal effectively floats and does not draw any current other than the leakage current, and this means that the logic powered by the Vout signal is in a power-off mode. In this configuration, an improvement in the reduced leakage current relative to prior conventional voltage switching devices is achieved by coupling the header voltage switching device PFET 130 to the overdrive voltage rail 152.

Noting the circuit of Figure 1A, PFET 130 is used to transfer a logic value of one. It is well known in the prior art that PFETs are more efficient at transmitting a logic value of one and less efficient at transmitting a logic value of zero. It is also known in the prior art that the NFET (e.g., NFET 120) of the holding device of Figures 1A through 1C is less efficient at transmitting a logic value of one and more efficient at transmitting a logic value of zero. This is used here to carefully generate a voltage drop in the hold mode.

1C is a schematic diagram of a power control integrated circuit header unit in accordance with an embodiment of the present invention, wherein the power control input signal nSLEEP and the hold enable signal nRET are configured such that the circuit is in a hold enable state configuration. As shown in FIG. 1C, the hold enable configuration corresponds to the power control signal nSLEEP having a value of a logic zero potential and the hold enable signal nRET having a value of a logic zero potential. In this configuration, when the NFET 135 of the first inverter is turned off, the PFETs 140, 145 of the first inverter are both turned on. This causes the PFET 130 of the header voltage switching device to be coupled to the overdrive voltage Vod, and thus is overdriven in a closed state similar to the configuration of Figure 1B. As a result of the hold enable signal being a logic zero potential, when the NFET 115 of the second inverter is turned off, both PFET devices 105, 110 of the second inverter are turned on. This causes the holding device NFET 120 to be turned on and coupled to the overdrive voltage rail 152, for example, the NFET of the header voltage switching device is overdriven to a "booster gate" in the on state. Thus, Vout is coupled to Vin through NFET 120. Because NFET 120 is less efficient at transmitting logic value 1 than transmitting logic value 0, coupling Vin to Vout in this configuration is sufficient to maintain the logic device powered by Vout signal in a hold mode instead of a full power switch. The level of the mode.

Since each of the power control input signal and the hold enable signal of the circuits of FIGS. 1A-1C has a value of a logic 0 potential or a logic 1 potential, there are four distinct states that the circuit can assume. However, a state that has not been exemplified is nSLEEP being a logic one potential and a state in which the nRET signal is a logic zero potential. In this configuration, the PFET device 130 that couples the Vin input voltage source to Vout is turned on, the NFET device 120 that couples the Vin voltage source to the Vout signal is turned on, and the Vin voltage source is coupled to Vout by both the PFET device 130 and the NFET device 130. Signal. However, this mode is not efficient and is generally not used. Therefore, no further explanation will be given here.

In an alternative embodiment of the specific embodiment of FIG. 1A, the hold switching device corresponding to the inverter 102 and the holding device 120 can be implemented as its own self-contained standard unit, or Implemented as a self-contained circuit that is provided independently of the power control switch (excluding the header switching device 130 and the first inverter 132). This can then be connected to a different power control integrated circuit without the need for a built-in data retention functionality.

In a further alternative embodiment, a different circuit or separate standard unit can be provided, comprising: the voltage switching device 130, and the first inverter 132 providing a connection to the overdrive voltage rail 152, and the second inverter 102 and the holding device 120 are excluded. In other words, it provides a circuit or standard unit that includes an overdrive voltage switch to exclude a hold switching device.

2A is a diagram illustrating a power control integrated circuit unit in accordance with a second embodiment of the present invention. The voltage switching device 230 in this embodiment is a bottom switching device, wherein the input supply voltage "Vssin" corresponds to a substantially ground voltage level, and wherein the overdrive supply voltage supply "Vssod" is lower than the voltage The supply input, for example, the overdrive voltage supply rail Vssod is at a negative voltage. As shown in FIG. 2A, the bottom voltage switching device includes an NFET 230 and a holding device PFET 220 coupled to the ground voltage supply Vssin and to an output voltage Vssout. The bottom voltage switching device 230 and the holding device 220 are both coupled to an overdrive voltage supply rail Vssod 250 and to an additional voltage supply rail 252, which in this embodiment is Each of an inverter 232 and a second inverter 202 can be approximately -100 mV (although this voltage level is configurable and specifically processed).

In the configuration of FIG. 2A, the bottom voltage switching unit 230 is controlled by a power control signal labeled "SLEEP" and by a negative overdrive supply voltage Vssod 250(-ve) below the ground supply Vssin. The first inverter 232 is powered to amplify. The circuit further includes a second inverter 202 controlled by a hold enable signal labeled RET and powered by the lower voltage Vssin, which provides when the circuit is configured to provide a voltage of approximately Vssin One of the voltage levels of the level is grounded to maintain a connected logic circuit in a hold mode. A hold mode is illustrated in more detail in Figure 2C.

It should be understood that in an alternative embodiment, only the holding voltage of the second inverter 202 is connected to when the voltage switching device itself has a standard connection only to the voltage supply input and the voltage supply output. This overdrive voltage. In other words, in some implementations, the hold switch is overdriven (rather than the voltage switching device), however in other embodiments, the voltage switch is overdriven (rather than the hold switch). The same applies to the specific embodiments of FIGS. 1A to 1C.

In still other embodiments, the hold switching device 220 and the second quasi-bit shift inverter 202 can be provided with a standard unit connected to the connection of the overdrive voltage Vssod without being included in the The voltage switching device of the standard unit itself.

In the header power control integrated circuit of FIG. 1A, the PFET pairs 140, 145 of the first inverter, and the PFET pairs 105, 110 of the second inverter 102 are stacked PFET devices. Similarly, in the particular embodiment of FIG. 2A, the pair of NFET devices 240, 245 of the first inverter 232 can be stacked as the pair of NFET devices 210, 115 of the second inverter 202. The four NFET devices 210, 215, 240, 245 are all body biased using a ground supply voltage Vssin that is higher than the overdrive voltage provided on the voltage supply rail 250. The forward bias increases the leakage and reduces the area. The transistors are stacked to provide reduced current leakage relative to the NFET device using the ground supply voltage Vssin instead of the leakage of the device that is biased to forward bias.

In the arrangement of FIGS. 2B and 2C, when SLEEP=1, the negative overdrive voltage Vssod is applied to the gate of the NFET device 230. This causes the NFET device 230 to couple the Vssin ground supply voltage to Vssout to be overdriven to a closed state that is the same as the voltage level Vssin that is driven and coupled to the voltage source by the voltage level Vssin of the voltage source. The reduced leakage of the device is characterized.

Fig. 2A schematically illustrates the state of the bottom power control integrated circuit unit in a full power on mode. In this configuration, the power control input signal SLEEP has a logic 0 potential value, and the hold enable signal RET also has a logic 0 potential value. Therefore, as shown in FIG. 2A, when SLEEP=0, the PFET 230 of the first inverter 232 is turned on, and the two NFETS 240, 245 of the first inverter 232 are turned off. This causes the NFET 230 of the bottom voltage switching device to be coupled to the voltage supply rail 252 by the PFET 235 and thus turned on. At present, attention is paid to driving the second inverter 232 of the hold switching device 220. When the hold enable signal RET=0, the PFET 205 of the second inverter 202 is turned on, and the pair of the second inverter is turned on. NFETs 210, 215 are turned off.

This means that the PFET holding device 220 is coupled to the positive voltage rail 252 and is therefore closed. Because the NFET 230 of the bottom voltage switching device is turned on when the PFET 220 is turned off, the voltage supply input Vssin is coupled to Vssout by the NFET 230, which is more efficient than transmitting a logic one value. In this mode, the logic coupled to the Vssout signal is effectively coupled to ground Vssin and operates in a full power on mode. In this full power on mode of Figure 2A, no transistor is overdriven.

FIG. 2B schematically illustrates a power control integrated circuit of the bottom voltage switching device, wherein the power control input signal and the logic value of the hold enable signal cause the device to be in a power off configuration. In particular, the power control input signal SLEEP is equal to 1 and the hold enable signal RET is equal to zero. When SLEEP is equal to 1, the pair of NFET transistors 240, 245 of the first inverter 232 are both turned on, and the PFET transistor of the first inverter 232 is turned off. Thus, the NFET 230 of the bottom voltage switching device is coupled to the overdrive voltage rail 250 having a negative voltage below ground potential, which causes the NFET 230 to overdrive to a closed state. When RET is equal to zero, the stacked NFET transistors 210, 215 of the second inverter 202 are in a closed configuration, and the PFET 205 of the second inverter 202 is in an open configuration. Thus, the input to PFET 220 corresponding to the holding device is from a positive voltage supply that switches PFET 220 off. Because both NFET 230 and PFET 220 are off in this configuration, Vssout is decoupled from Vssin, and thus all logic (not shown) powered by the Vssout signal is in a power off mode.

In the case where SLEEP=1 is configured, the gate of the NFET device 230 of the bottom voltage switching device is driven to an input voltage lower than the voltage of Vssin that drives it to a closed state. This is sequentially reduced relative to if the NFET device is driven to an off state by one of the voltage levels having Vssin (eg, if it is not coupled to the overdrive voltage by the first inverter 232) Leakage current. Because the NFET transistor 230 of the bottom voltage switching device and the PFET transistor of the holding device are both turned off, the Vssout signal effectively floats and does not transmit current other than the leakage current.

FIG. 2C schematically illustrates the power control integrated circuit of FIG. 2A and FIG. 2B having a bottom voltage switching device, and in this case, the power control input signal and the logic input of the hold enable signal cause the The device is in a hold enabled configuration. In particular, the power control input signal (SLEEP) is equal to one and the hold enable signal (RET) is equal to one.

Because SLEEP=1, the NFET pair 240, 245 of the first inverter 232 is turned on, and the PFET 235 of the first inverter 232 is turned off. This causes the NFET 230 of the bottom switching device to be coupled to the negative overdrive voltage rail 250 by the stacked NFET pairs 240, 245, and thus overdriven to a closed state. Because the enable signal RET=1, the pair of stacked NFETs 210, 215 of the second inverter 202 are turned off, and the PFET 205 of the second inverter 202 is turned off. Thus, the PFET holding device is coupled to the negative overdrive voltage rail 250 by the stacked NFETs 210, 215, and by an overdrive voltage having a voltage level that supports any of the logic connected to Vssout in a hold mode. To open.

Another mode of the circuit of Figure 2A is not typically used, and corresponds to SLEEP = 0 and RET = 1. In this case, the NFET device 230 that couples the Vssin input voltage source to the Vssout signal is turned on, and the PFET device 220 that couples the Vssin voltage source to the Vssout signal is turned on, such that the Vssin voltage source is passed through the NFET device 230 and the PFET. Both devices are coupled to the Vssout signal. Because it is not efficient, it does not use this mode.

Figure 3 is a schematic illustration of a third embodiment of the present invention in which a header voltage switching device is provided comprising: a coupling to a voltage supply input Vin and a switchably coupled to a voltage supply output Vout PFET transistor 330 and an NFET transistor 320. In this third embodiment, an inverter is not provided as a voltage level switching device to couple the voltage switching devices 320, 330 to an overdrive voltage Vod and a voltage supply input Vin, which provides a first half latch The circuit 332 and a second half latch 302. Under the control of the power control input signal (SLEEPN), the first latch circuit 332 couples the voltage switching device to the overdrive voltage, and the second half latch 302 is provided to replace the first portion of FIG. The two inverters 102 connect the holding switching device 320 to the overdrive voltage Vod under the control of the hold enable signal (RETN).

It will be appreciated that a similar arrangement can be provided that is comparable to one of the bottom voltage switching devices of Figure 2A, which is similar to the arrangement of Figure 3, which locks the first inverter 232 by a first half. Instead of and replacing a second inverter 202 with a second half latch circuit. In the case of quasi-displacement inverters, an additional leakage term is introduced by under-driving its input relative to their supply Vod, thus avoiding the pull-up PFETs from being fully turned off. The feedback and transfer transistors in the half latch (the top two PFETs and the outermost NFETs N3 & N5 labeled P4 & P5 in the diagram) ensure that the input to the pull-up PFET is connected to Vod And thus completely shut down.

Figure 4A schematically illustrates a power control integrated circuit including: a header voltage switching device, and an intrusion current limiting circuit. Figure 4A shows this intrusion limited power control circuit in a hold mode, while Figure 4B shows this same circuit in a full power on configuration. The arrangement of the circuits in Figure 4A is very similar to the arrangement of the circuits in Figure 1A, while in the case of Figure 4A an additional PFET 350 is provided at the input voltage supply rail Vin and the header voltage switching Between the gates of the PFET 330 of the device. The PFET device 350 functions as an inrush current limiting circuit and is controlled by the hold enable signal nRET, which also controls the second inverter 402.

The second inverter 402 is a hold enable switching device and includes: PFET transistors 305, 310 and NFET transistors 315, and operates with the inrush current limiting PFET 350 to provide for maintaining coupling to the Vout signal The storage device is in a hold state with a reduced voltage. Similar to the circuit of FIG. 1A, the stacked PFET devices 305, 310, 340, 345 of the circuit of FIG. 4A are biased using the voltage supply input voltage Vin, which is lower than the overdrive voltage. The doubling of the transistors provides reduced leakage characteristics when the device is turned off.

In the configuration of Figure 4A, nSLEEP = 0, nRET = 0 and the header circuit is in a hold mode. In this state, the two transistor PFETs 340, 345 of the first inverter 432 are turned on, and the NFET 335 of the first inverter is turned off. This causes the PFET 330 of the header voltage switching device to be coupled to the overdrive voltage, and thus overdrive to the off state. In the second inverter, since nRET=0, the stacked PFETs 305, 310 are both turned on, and the NFET 315 of the second inverter 402 is turned off. This causes the NFET 320 of the header voltage switching device to be coupled to the overdrive voltage Vod, and thus turned on. Since the PFET 350 for limiting the inrush current is controlled by the hold enable signal nRET having a logic 0 potential value, the transistor is turned on. The state of the circuit elements other than the intrusion limiting PFET 350 is the same as the circuit element corresponding to the 1Cth picture (hold mode).

Figure 4C schematically illustrates how the circuit of Figure 4A operates when it is in a full power on configuration (where nSLEEP = 1 and nRET = 1). The transistor of the first inverter 432 switches with respect to the polarity of the corresponding transistor of FIG. 4A such that both PFETs 340, 345 are turned off, and the NFET 335 is turned on. In the second inverter 402, the pair of stacked PFETs 305, 310 are both turned off and the NFET 315 is turned on. This causes the NFET 320 of the header voltage switching device to be coupled to ground through the NFET 315, and thus turned off. The PFET 330 of the header voltage switching device is coupled to ground by the NFET 335 of the first inverter 432, and thus in an open configuration. The state of the circuit elements other than the intrusion limiting PFET 350 in Fig. 4C is the same as that of the corresponding circuit element of Fig. 1A (power on).

However, for FIGS. 4A to 4C, an additional mode is provided in addition to the power on mode, the power off mode, and the hold mode of FIGS. 1A to 1C. In particular, an intrusion limiting mode is provided and the circuit is in this intrusion limiting mode as the hold mode (nSLEEP=0, NRET=0) in FIG. 4A and the full power on mode in n° 4C (nSLEEP=1) , intermediate mode between nRET=1). This intrusion restriction mode is schematically illustrated in Fig. 4B. In this intrusion limit mode, nSLEEP=1, nRET=1. This input signal combination corresponds to a mode that is not used in the circuits of FIGS. 1A to 1C. In this inrush current limiting mode, NFET 335 is turned on, PFETs 340, 345 are turned off, so the intrusion limit PFET 350 is turned on, and the header switching device 330 is only partially turned on. Since nRET = 0, the holding device is still on, the PFETs 302, 310 of the second inverter 402 are still turned on, and the NFET 315 of the second inverter is turned off as in Figure 4A. However, when the circuit transitions from the inrush current limiting mode of FIG. 4B to the full power on mode of FIG. 4C, nRET transitions from 0 to 1 to cause the intrusion limiting PFET 350 to turn off.

When there is no PFET 350 and when there is no intrusion limiting mode, when switching from the hold mode of FIG. 4A directly to the power on mode of FIG. 4C, and when the PFET device 330 of the header voltage switching device is turned off to on, There is an inrush current, for example, it begins to conduct a larger current. The intrusion of this current has the potential to cause a voltage drop across the voltage supply input Vin.

In the absence of PFET 350, this voltage drop potentially causes a logic element (not shown) to be coupled to the Vout signal, which is in a hold mode before converting nSLEEP and nRET to lose the data content maintained in the hold latch.

However, the supply of the PFET device 350 reduces the chance of data loss in the hold latch due to the provision of an additional mode between the hold mode and the power on mode (eg, the intrusion mode of FIG. 4B). In order to delay the conversion of the nRET signal (from 0 to 1) until after the conversion of the nSLEEP signal (from 0 to 1), so that the gate voltage observed by the PFET device 330 of the header voltage switching device is high. The gate voltage of the NFET device 335 of only the first inverter 432. This causes the PFET device 330 to be only partially turned on (in the intrusion limited mode) and draws a smaller amount of current to the Vout pin. The voltage on the gate of the PFET device 330 of the voltage switching device can be selected by appropriately adjusting the size of the inrush current limiting PFET 350, and thus the amount of current drawn by the PFET device 330 can be reduced to be required by the circuit designer. And arranging to ensure that the inrush current does not result in loss of data in the holding state of the device.

The nRET hold enable signal is maintained at a logic zero potential value until any drop in the voltage source Vin is restored after reducing the intrusion circuit and the circuit is stable (eg, the circuit is maintained in the intrusion mode of FIG. 4B). After this point in time, the nRET signal transitions to a logic 1 potential value corresponding to the full power on configuration, and causes the PFET device 350 to turn off as shown in FIG. 4C, and causes the PFET device 330 to enter a full turn-on. status.

It should be understood that an NFET device coupled to the Vssin signal and controlled by the RET hold enable signal can be added to provide similar adjustments to the circuits in FIGS. 1A-1C to provide The manner of the circuits of FIGS. 4A to 4C is adjusted for the bottom voltage switching device of FIGS. 2A to 2C.

Figure 5 schematically illustrates an additional embodiment of a particular embodiment of the header voltage switching device similar to Figure 1A, but with a pair of inverters 460, 470 incorporated into the circuit. The inverter 470 is configured to buffer the output of the nSLEEP signal (for example, to buffer the control output signal), and the inverter 460 is configured to buffer nRET (eg, the hold enable signal). The inverter 470 buffering the nSLEEP signal is coupled to the output of the nSLEEP inverter, the nSLEEP inverter comprising: the NFET device 435 and the pair of stacked PFET devices 440, 445. This buffer is used for the nRET signal, for example, the inverter 460 is coupled to the output of the nRET inverter, the nRET inverter comprising: the pair of stacked PFETs 405, 410 and NFET 415.

The first inverter generates an output signal "nSLEEPOUT" which is a buffered version of nSLEEP, and the inverter 460 provides an output of "nRETOUT" corresponding to the buffered version of the hold enable signal nRET. Both of these inverters 460, 470 are powered by the voltage supply input Vin. When each of the inverters 460, 470 is driven by a logic 1 potential input, then it will be overdriven in the same manner as follows: (i) the PFET device 430 of the inverter 470; and (ii) The NFET device 420 of the inverter 460. This results in a reduced leakage current. The output of the inverter 470 can be supplied as nSLEEP input to another power control integrated unit (not shown), and the output of the inverter 460 can be supplied as input to the displays shown in FIGS. 1A and 4 Similar types of power control integrated circuit unit nSLEEP inputs, and others that drive the same circuit type.

It will be appreciated that similar adjustments can be made to the enhanced bottom voltage switching device of FIG. 2A by adding a buffered inverter, and can also be described above with respect to FIG. 3 having the inrush current limiting PFET 350. The header unit of the specific embodiment makes adjustments.

In the circuit of Figure 5, the buffer 470 controlled by the nSLEEP power control input signal is responsive to the power supply output Vout, the value of which is determined by the state of the PFET device 430 and the NFET 420 of the voltage switching device (header) Device). Similarly, the buffer 460 coupled to the nRET hold enable signal is responsive to the power supply output Vout of the voltage switching device 420, 430. The inverters 460, 470 of FIG. 5 perform the functions of the power control signal buffering circuits 16, 18 similar to the third drawing of the earlier U.S. Patent Application Serial No. 11/920,364, the entire disclosure of which is hereby incorporated by reference. . In the terminology of the earlier application, the voltage rail in the fifth diagram of the present application can be regarded as the correspondence of "unswitched power supply input", and the Vout of the present application. It can be regarded as the correspondence of "switched power supply input". The power control input signal nSLEEP of Figure 5 of the present application is analogous to the power control signal input NStartIn of Figure 3 of US 11/920,364. In a manner similar to the earlier application described above, the buffered inverter 470 executing the power control input signal nSLEEP in FIG. 5 of the present application is at least partially input from the non-switching power supply Vin. Powering, and responding to the switched power supply output Vout to drive a power control output signal nSLEEPOUT from a power control signal output. In a similar manner, the inverter 460 of the present application is powered at least in part from the non-switched power supply Vin, and in response to the switched power supply output Vout to drive a power control output signal from a power control signal output. nRETOUT.

Vin, Vout, and Vod supplied in an integrated circuit unit and two inverters 460, 470 of FIG. 5 of the present application are located in a non-switching power supply line around both inverters 460, 470 Near the entity of Vin, the inverters 460, 470 perform a buffering function to direct their permanently stored supply power from Vin as required. In response to the switched power supply output Vout by the inverters 460, 470 to direct the buffered output signals nSLEEPOUT and nRETOUT from the corresponding power control symbol output, the power control input signal nSLEEP and the A significant delay is introduced between the enable input signal nRET. The power switching circuit connects the switched power supply output to the non-switching power supply input and the power control signal buffer circuit 470, and the hold enable signal buffer circuit 460 transmits the relevant control signal as the output power control signal. . Therefore, when the individual standard cells including the circuit elements of Fig. 5 are connected to other power control integrated circuit units, this can significantly reduce the peak current and thus the power surge.

Figure 6 is a diagram schematically illustrating the standby power versus Watts voltage in Watts for three different variations of a power control integrated circuit. The results presented in the diagram of Figure 6 were obtained by computer simulation of circuit operation. The simulated temperature corresponds to 25 degrees for the purpose of the simulation. In the diagram of FIG. 6, a first line 610 having a diamond shaped data point corresponds to a header or bottom voltage switching device that does not provide a holding device, and provides an inverter 132 similar to FIG. 1A. The inverter connects the voltage switching device to an overdrive voltage in addition to connecting it to the standard voltage input supply Vin. In other words, the line 610 corresponds to a circuit having a super cut-off at the power gate, such as the voltage switching device rather than the hold mode.

A second line 620 having a cross shape as a data point corresponds to a circuit having a holding device and a voltage switching device connected to the overdrive supply voltage, similar to the circuit of FIG.

A third line 630 is similar to the line 610 and corresponds to a circuit that overdrives the voltage switching device, rather than having no holding device at all, and the overdrive holding device corresponding to the inverter 102 of FIG. 1A has the same driving strength. The large general NFET is replaced. This does not fully correspond to any of the circuits of Figures 1A through 5 corresponding to the prior art techniques compared to the prior art described above.

The diagram of Fig. 6 shows that the improvement in the consumption reduced by the standby power is excellent for the gate voltage of the line 610 to about 1.1 Volts, and the pattern line becomes due to the additional leakage through the input inverter. flat. A comparison of lines 610 and 620 shows that increasing the power burden of the holding device (included in the circuit corresponding to line 620) is negligible below 1.1 Volts, while the leakage of the forward bias becomes more pronounced thereafter.

Although the exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it is understood that the invention Various changes and modifications are made herein in the scope and spirit of the invention as defined by the scope of the invention. For example, various features of the individual items can be combined with the features of the subsequent claims without departing from the scope of the invention.

Other exemplary aspects and features of the present technology are described below: The disclosed is a first circuit of enhanced power gating with reduced leakage when in a low power mode and a hold mode. In the disclosed circuit, a header power unit adds an input inverter controlled by a uniform power signal and powered by a higher supply voltage, and the power supply is coupled to control the coupling of the Vin supply voltage to the inversion of the Vout signal. The gate of the device is input to a higher voltage, providing a reduction in leakage current when the circuit is driven into a low power mode. In a similar manner, the disclosed circuit can include: a second inverter controlled by a second enable signal and powered by a higher voltage, wherein the circuit is configured to draw a decrease in the Vout signal The voltage provides a reduced leakage current while maintaining the connected logic in a hold mode.

Figure 1A shows that the disclosed circuit adds the second inverter, the second inverter comprising: NFET device 115 and PFET devices 105 and 110 coupled to the nRET signal enable. The inverter and NFET 120 operate to provide a reduced voltage suitable for maintaining a storage device coupled to the Vout signal in a hold mode.

In the disclosed circuit, the stacked PFET devices 105, 110, 140, and 145 are biased using a lower Vin voltage to reduce the cell area. The use of spliced PFETs (145 and 140, and 105 and 110) eliminates the associated leakage characteristics when the device is turned off.

When the nSLEEP input signal is at a logic 1 potential and the nRET input signal is at a logic 1 potential, the PFET device 130 that couples the Vin input voltage source to Vout will turn "on" and the output Vout will effectively be the Vin voltage. The NFET device 120 that couples the Vin input voltage source to the Vout output is turned off. In this mode, the logic devices powered by the Vout signal are in a full power on mode.

When the nSLEEP input signal is at a logic 0 potential and the nRET input signal is at a logic 1 potential, the PFET device 130 coupling the Vin input voltage to the Vout signal is turned off, and the NFET device 120 coupling the Vin voltage to the Vout signal. When turned off, the output signal Vout is no longer coupled to the Vin input voltage to the Vout signal. The first inverter (which includes PFET devices 140 and 145, and NFET device 135) driven by the nSLEEP signal drives the gate of the PFET device 130 to an input voltage higher than Vin, which effectively overdrives the PFET device 130 to a closed state, and significantly reduces the leakage current from the leakage current present if the PFET device 130 is driven by an input signal having a Vin voltage level to be turned off. In this mode, the output on the Vout signal is effectively varied and does not draw current other than the leakage current, and the logic powered by the Vout signal is in a power off mode.

When the nSLEEP input signal is at a logic 1 potential and the nRET input signal is at a logic 0 potential, the PFET device 130 coupling the Vin input voltage source to the Vout signal is turned on, and the NFET device coupling the Vin voltage source to the Vout signal 120 is turned on, and the Vin voltage source is coupled to the Vout signal by the PFET device 130 and the NFET device 120. This mode is inefficient and generally not used.

When the nSLEEP input signal is at a logic 0 potential and the nRET input signal is at a logic 0 potential, the PFET device 130 is turned off and overdriven as previously described. The PFET device 130 no longer couples the Vin voltage source to the Vout signal. The NFET device 120 turns on and couples the Vin voltage source to the Vout output signal having at least a level sufficient to maintain the logic device powered by the Vout signal to maintain a hold mode.

The disclosed is a second circuit of enhanced power gating with reduced leakage when in a low power mode and a hold mode. In the disclosed circuit, a bottom unit adds an input inverter controlled by the uniform energy signal and powered by a supply voltage Vssod, which is lower than the ground supply Vssin. In a similar manner, the disclosed circuit includes a second inverter controlled by a second enable signal and powered by a lower voltage, which is configured to provide a voltage level slightly above the Vssin The leakage current is reduced when the ground connection of the connected logic circuit is maintained at a voltage level of a hold mode.

2A shows that the disclosed circuit adds the second inverter, the second inverter comprising: NFET devices 210 and 215 coupled to the RET signal enable and PFET device 205. The inverter and PFET 220 operate to provide a higher voltage on the ground source suitable for maintaining the storage device coupled to the Vssout signal in a hold state.

In the disclosed circuit, the spliced NFET devices 210, 215, 240, and 245 are biased using a higher Vssin voltage to cause a reduction in leakage characteristics when the device is turned off. The input voltage source 225 is driven to a positive voltage. The lower voltage on the Vssod voltage source applied to the gate of the NFET device 230 enables the NFET device 230 to couple the Vssin ground supply to the Vssout signal for overdriving to a closed state, as compared to having The voltage level of the Vssin voltage source is characterized by a smaller leakage current of the same device.

When the SLEEP input signal is a logic 0 potential and the RET input signal is a logic 0 potential, the NFET device 230 that couples the Vin input voltage source to the Vout signal is turned on, and the output Vssout signal is effectively at the Vssin voltage level. Above ground level. The PFET device 220 that couples the Vssin voltage source to the Vssout output is turned off. In this mode, the logic coupled to the Vssout signal is operatively coupled to ground and operates in a full power on mode.

When the SLEEP input signal is at a logic 1 potential and the RET input signal is at a logic 0 potential, the NFET device 230 that couples Vin to Vout is turned off, and the PFET device 220 that couples Vin to Vout is turned off, causing the output signal Vout not to be The Vssin input voltage is recoupled to the Vssout signal. The first inverter (which includes NFET devices 240 and 245, and PFET device 235) driven by the SLEEP signal drives the gate of the NFET device 230 to an input voltage lower than Vssin, which effectively overdrives the NFET The device 230 is in a closed state and significantly reduces the leakage current present if the NFET device 230 is driven to be off by an input signal having a Vssin voltage level. In this mode, the output on the Vssout signal is effectively varied, and no current other than the leakage current is drawn, and the logic powered by the Vssout signal is in a power off mode.

When the SLEEP input signal is at a logic 0 potential and the RET input signal is at a logic 1 potential, the NFET device 230 coupling the Vssin input voltage source to the Vssout signal is turned on, and the PFET device 220 coupling the Vssin voltage source to the Vssout signal is turned on. And the Vssin voltage source is coupled to the Vssout signal by both the NFET device 230 and the PFET device 220. This mode is inefficient and generally not used.

When the SLEEP input signal is at a logic 1 potential and the RET input signal is at a logic 1 potential, the NFET device 230 is turned off and overdriven as previously described. The NFET device 230 no longer couples the Vssin voltage source to the Vssout signal. The PFET device 220 turns on and couples the Vssin voltage source to the Vssout signal having at least a level sufficient to maintain the logic device effectively coupled to ground by the Vssout signal to maintain a hold mode.

The disclosed is a third circuit of enhanced power gating with reduced leakage when in a low power mode and a hold mode. In the disclosed circuit, a header power unit is increased by a constant energy signal control and an input inverter is supplied by a higher supply voltage, and the power supply is connected to control the coupling of the Vin supply voltage to the reverse of the Vout signal. The gate of the phaser is input to a higher voltage, providing a reduction in leakage current when the circuit is driven into a low power mode. In a similar manner, the disclosed circuit can include: a second inverter controlled by a second enable signal and powered by a higher voltage, wherein the circuit is configured to draw a reduced amount of the Vout signal The voltage provides a reduced leakage current to maintain the connected logic circuit in a hold mode. Moreover, a PFET device 350 is coupled between the Vin voltage source and the gate of the PFET device 330 and is controlled by the nRET input signal.

Figure 4A shows that the disclosed circuit adds the second inverter, the second inverter comprising: NFET device 315 and PFET devices 305 and 310 coupled to the nRET signal enable. The inverter and NFET 320 operate to provide a reduced voltage suitable for maintaining a storage device coupled to the Vout signal in a hold mode.

In the disclosed circuit, the stacked PFET devices 305, 310, 340, and 345 are biased using a lower Vin voltage to induce a reduced leakage characteristic when the device is turned off.

In the disclosed circuit, the circuit discussed above and shown in Figure 1A of a particular embodiment adds a PFET device 350 controlled by the nRET input signal. When the nRET input signal is at a logic 0 potential and the nSLEEP signal is at a logic 0 potential, the disclosed header circuit is in a hold mode. When the circuit transitions from the hold mode to a full power on mode, and the PFET device in this and other similar standard cells begins to conduct a large current, an intrusion of current may be encountered. The intrusion of this current has the potential to cause a voltage drop across the Vin voltage source. This voltage drop can cause the logic element connected to the Vout signal (which is in the hold mode prior to the conversion of nSLEEP and nRET) to lose the data content held in the hold latch. This can be avoided by introducing a PFET device 350 coupled between the Vin voltage source and the gate of the PFET device 330. By delaying the conversion of the nRET signal after the nSLEEP signal conversion, the gate voltage observed by the PFET device 330 is higher than the gate voltage of only the NFET device 335, which causes the PFET device 330 to be only partially turned on. State and draw a smaller amount of current to the Vout pin. The voltage at the gate of the PFET device 330 can be selected by adjusting the size of the PFET device 350, and thus the amount of current drawn by the PFET device 330 can be reduced to ensure that the inrush current is not compromised by the circuit designer. the behavior of. The nRET signal is maintained at a logic 0 potential until any voltage drop across the voltage source Vin has recovered after the inrush current has decreased and the circuit has stabilized. After this point in time, the nRET signal transitions to a logic one potential, which causes the PFET device 350 to turn off, and the PFET device 330 to enter a fully on state.

A similar adjustment of the PFET device can be made as shown in FIG. 4A for the enhanced bottom unit described in FIG. 2A, adding an NFET device that couples the Vssin voltage source to the Vssout output signal and is controlled by the nRET input signal.

The disclosed is a fourth circuit of enhanced power gating with reduced leakage when in a low power mode and a hold mode. In the disclosed circuit, a header power unit adds an input inverter controlled by a uniform power signal and powered by a higher supply voltage, and the power supply is coupled to control the coupling of the Vin supply voltage to the inversion of the Vout signal. The gate of the device is input to a higher voltage, providing a reduction in leakage current when the circuit is driven into a low power mode. In a similar manner, the disclosed circuit can include: a second inverter controlled by a second enable signal and powered by a higher voltage, wherein the circuit is configured to draw a decrease in the Vout signal The voltage is maintained to provide a reduction in leakage current when the connected logic circuit is maintained in a hold mode. Furthermore, an inverter is added to the output of each of the two inverters coupled to the nSLEEP signal and the nRET input signal.

Figure 5 shows that the disclosed circuit adds the second inverter, which includes: NFET device 415 and PFET devices 405 and 410 coupled to the RET signal enable. The inverter and NFET 420 operate to provide a reduced voltage suitable for maintaining a storage device coupled to the Vout signal in a hold mode.

In the disclosed circuit, the circuit previously discussed and shown in FIG. 1A of the embodiment adds an inverter 470 coupled to the output of the nSLEEP inverter, the nSLEEP inverter comprising: an NFET device 435 and PFET devices 440 and 445, and further an inverter 460 coupled to the output of the nRET inverter, the nRET inverter comprising: NFET device 415 and PFET devices 405 and 410. The two additional inverters 470 and 460 individually buffer the input signals nSLEEP and nRET, and individually generate the output signals nSLEEPOUT and nRETOUT. The inverters 470 and 460 are powered by the voltage source Vin. When such drivers are driven by a logic one potential input, the inverters will be overdriven in the same manner as the PFET device 430 and the NFET device 420, which results in a reduced leakage current.

These signals can be driven to the nSLEEP and nRET inputs of the header unit of the type shown in Figures 1 and 3 above, and drive the same circuits.

Similar adjustments can be made to the boosting bottom unit described in accordance with FIG. 2A and the promotional header unit as described in FIG. 4A.

102. . . inverter

105, 110. . . PFET

115. . . NFET

120. . . Keep switching device

130. . . PFET

132. . . inverter

135. . . NFET

140, 145. . . PFET

150. . . Ground voltage rail

152. . . Overdrive voltage rail

202. . . inverter

205. . . PFET

210, 215. . . NFET

220. . . Keep switching device

225. . . Input voltage source

230. . . Voltage switching device

235. . . PFET

240, 245. . . NFET

250. . . Overdrive voltage supply rail

252. . . Voltage supply rail

302. . . Half latch

305, 310. . . PFET

315. . . NFET

320. . . NFET

330. . . PFET

332. . . Half latch circuit

335. . . NFET

340, 345. . . PFET

350. . . PFET

405. . . PFET

410. . . PFET

415. . . NFET

420. . . NFET

430. . . PFET

435. . . NFET

440, 445. . . PFET

460. . . inverter

470. . . inverter

FIG. 1A schematically illustrates a power control integrated circuit including: a header voltage switching device, the power control integrated circuit being in a full power on configuration;

1B is a schematic illustration of the power control integrated circuit of FIG. 1A with a header voltage switching device in a power-off configuration;

1C is a schematic illustration of the power control integrated circuit of FIG. 1A having a header voltage switching device and a hold switching device and in a hold enable configuration;

2A, 2B, and 2C are diagrams schematically illustrating a power control integrated circuit similar to the circuits of FIGS. 1A, 1B, and 1C, wherein the voltage switching device is a bottom voltage switching device, and representatives of FIGS. 2A to 2C represent The voltage switching device is in a power on, power off, and hold mode;

FIG. 3 is a schematic diagram showing an alternative embodiment of a power control integrated circuit having: a header voltage switching device, wherein a switching device is connected and the voltage switching device is connected to the A voltage quasi-displacer that supplies overdrive voltage can be implemented as a half latch;

Figure 4A schematically illustrates a header voltage switching device having: a hold switching device coupled to the overdrive voltage supply, and further comprising: an intrusion current limiting circuit, the illustrated circuit being in a hold mode;

FIG. 4B is a diagram schematically illustrating a power control integrated circuit of FIG. 4A having an intrusion limiting configuration instead of a holding mode;

4C is a schematic diagram of a power control integrated circuit of FIG. 4A, which has a full power on configuration circuit;

Figure 5 is a schematic diagram of a power control integrated circuit comprising: a header voltage switching device similar to the circuit of Figure 1A, wherein the buffer control element is provided for both the power control input signal and the hold control signal ;

Figure 6 is a schematic illustration of the configuration of standby power in Watts versus gate voltage in Volt for three example power control circuits.

102. . . inverter

105, 110. . . PFET

115. . . NFET

120. . . Keep switching device

130. . . PFET

132. . . inverter

135. . . NFET

140, 145. . . PFET

150. . . Ground voltage rail

152. . . Overdrive voltage rail

Claims (32)

A power control integrated circuit unit comprising: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output is switchably coupled to the voltage supply input Responding to a power control input signal such that in a power swing configuration of the voltage switching device, the voltage supply output is coupled to the voltage supply input; a hold switching device (120, 220) coupled to the voltage switching device And configured to switchably couple the voltage supply output to the voltage supply input in response to a hold enable signal such that in a hold enable configuration of the hold switching device, the voltage supply output corresponds to The input voltage is reduced relative to the voltage supply input; wherein the hold switching device (120, 220) has an additional voltage input from an overdrive voltage supply (Vod, Vssod) such that in the hold enable configuration, The holding switching device is relatively powerfully turned on with respect to being coupled to the voltage supply input signal and driven by the voltage supply input signal, and In a power-off configuration of the voltage switching device, the voltage supply output is determined by the hold switching device. The power control integrated circuit unit of claim 1, wherein: the voltage switching device is a header switching device, wherein the input supply voltage corresponds to a positive supply voltage, and the overdrive is The voltage supply is higher than the voltage supply input. The power control integrated circuit unit of claim 1, wherein the voltage switching device is a bottom switching device, wherein the input supply voltage corresponds to a ground voltage level, and the overdrive voltage The supply is below this voltage supply input. The power control integrated circuit unit of claim 1, wherein when one of the following occurs: (i) the voltage switching device is in the power-off configuration, and the holding switching device is configured such that The voltage supply output is decoupled from the voltage supply input; and (ii) the voltage switching device is in the power shutdown configuration, and the hold switching device is configured such that the voltage supply output is coupled to the voltage switching output A voltage supply input having an overdrive input for coupling the voltage switching device to the overdrive voltage supply. The power control integrated circuit unit of claim 4, wherein the voltage switching device is coupled to the overdrive voltage supply by a first voltage quasi-displacer, and the first voltage quasi-displacement The bit is controlled by the power control input signal. The power control integrated circuit unit of claim 5, wherein the first voltage quasi-bit shifter comprises: a first inverter. The power control integrated circuit unit of claim 5, wherein the first voltage level shifter comprises: a half latch. The power control integrated circuit unit of claim 6, wherein the inverter comprises: a pair of stacked transistors biased by the input supply voltage. The power control integrated circuit unit of claim 1, wherein the voltage supply input is an essentially fixed input voltage, and wherein the overdrive voltage supply is configured such that an overdrive voltage is self-contained One of the ranges of overdrive voltages is selected. The power control integrated circuit unit of claim 1, wherein the hold switching device is coupled to the overdrive voltage supply by a second voltage quasi-displacer, and the first voltage quasi-displacement The bit is controlled by the hold enable signal. The power control integrated circuit unit of claim 10, wherein the second voltage quasi-bit shifter comprises: a second inverter. The power control integrated circuit unit of claim 10, wherein the second voltage quasi-positioner comprises: a half latch. The power control integrated circuit unit of claim 11, wherein the second inverter comprises: a pair of stacked transistors biased using the input supply voltage. The power control integrated circuit unit of claim 1, wherein at least one of the voltage switching device and the holding switching device comprises: a field effect transistor. The power control integrated circuit unit of claim 1, comprising: an intrusion protection switching device controlled by the hold enable signal, and configured to switch the power control integrated circuit from a hold mode In the power-on mode, the intrusion of a current is blocked. The power control integrated circuit unit of claim 15, wherein the intrusion protection switching device is coupled between the voltage supply input and an input of the voltage switching device. The power control integrated circuit unit of claim 16, wherein the voltage switching device comprises: a field effect transistor, and the input of the voltage switching device comprises: a gate of the voltage switching device. The power control integrated circuit unit of claim 17, wherein the intrusion protection switching device comprises: a type of field effect transistor matched to the voltage switching device field effect transistor, the type being PFET and NFET One of them. The power control integrated circuit unit of claim 18, wherein the electrical characteristics of the intrusion protection switching device are balanced with respect to electrical characteristics of the voltage switching device to generate a blocking of the intrusion of the current. The power control integrated circuit unit of claim 5, comprising: a first buffer circuit component coupled to an output of the first voltage quasi-bit shifter, and configured to buffer the power control Enter the signal. The power control integrated circuit unit of claim 20, wherein the first buffer circuit component is powered by the voltage supply input. The power control integrated circuit unit of claim 10, comprising: a second buffer circuit component coupled to an output of the second voltage quasi-displacer, and configured to buffer the hold-up Can signal. The power control integrated circuit unit of claim 22, wherein the second buffer circuit component is powered by the voltage supply input. A power control integrated circuit unit comprising: a hold switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output is switchably coupled to the voltage supply input Responding to a hold enable signal such that when the coupling is caused, the voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input; wherein the hold switching device has an input from an overdrive voltage supply So that when the switching device is enabled, it is more powerfully turned on with respect to being coupled to the voltage supply input signal and driving from the voltage supply input signal. A computer readable storage medium storing a data structure, the data structure comprising: a standard unit circuit definition for controlling a computer to generate and verify a circuit configuration of a circuit unit of an integrated circuit, the circuit unit The method includes: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), wherein the voltage supply output is switchably coupled to the voltage supply input in response to a power control input signal to In a power-up configuration of the voltage switching device, the voltage supply output is coupled to the voltage supply input; a hold switching device (120, 220) coupled to the voltage switching device, and configured to switchably Coupling the voltage supply output to the voltage supply input in response to a hold enable signal such that in a hold enable configuration of the hold switching device, the voltage supply output corresponds to a decrease relative to the voltage supply input Maintaining a voltage; wherein the hold switching device (120, 220) has an additional voltage input from an overdrive voltage supply (Vod, Vssod), So that in the hold-enabled configuration, the holding switching device is relatively powerfully activated with respect to being coupled to the voltage supply input signal and driven by the voltage supply input signal, and a power-off group thereof in the voltage switching device In the state, the voltage supply output is determined by the hold switching device. A computer readable storage medium storing a data structure, the data structure comprising: a standard unit circuit definition for controlling a computer to generate and verify a circuit configuration of a circuit unit of an integrated circuit, the circuit unit The method includes: a hold switching device having a voltage supply input (Vin) and a voltage supply output (Vout), wherein the voltage supply output is switchably coupled to the voltage supply input in response to a hold enable signal to When the coupling is caused, the voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input; wherein the hold switching device has an input from an overdrive voltage supply such that when the hold is enabled When the device is switched, it is more powerfully turned on with respect to being coupled to the voltage supply input signal and driving from the voltage supply input signal. A computer readable storage medium storing a data structure, the data structure comprising: a standard unit circuit definition for controlling a computer to generate and verify a circuit configuration of a circuit unit of an integrated circuit, the circuit unit The method includes: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), wherein the voltage supply output is switchably coupled to the voltage supply input in response to a power control input signal to Having the voltage supply output coupled to the voltage supply input in a power swing configuration of the voltage switching device; wherein the voltage switching device has an additional voltage input from an overdrive voltage supply such that when the voltage is switched When the device is in a power-off configuration, wherein the voltage supply output is decoupled from the voltage supply input, the voltage switching device is coupled to the voltage supply input signal and driven by the voltage supply input signal, which is more powerful The ground is closed. A computer implementation method for designing an integrated circuit includes the steps of: selecting at least one standard unit from a standard unit database, and incorporating the at least one standard unit in the integrated circuit, the at least one standard unit comprising: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output is switchably coupled to the voltage supply input in response to a power control input signal such that In a power swing configuration of the voltage switching device, the voltage supply output is coupled to the voltage supply input; a hold switching device (120, 220) coupled to the voltage switching device, and configured to switchably couple the And outputting a voltage supply to the voltage supply input in response to a hold enable signal such that in a hold enable configuration of the hold switching device, the voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input Wherein the hold switching device (120, 220) has an additional voltage input from an overdrive voltage supply (Vod, Vssod) such that In the hold-enabled configuration, the hold switching device is relatively powerfully activated with respect to being coupled to the voltage supply input signal and driven by the voltage supply input signal, and in a power-off configuration of the voltage switching device, The voltage supply output is determined by the hold switching device. A computer implementation method for designing an integrated circuit includes the steps of: selecting at least one standard unit from a standard unit database, and incorporating the at least one standard unit in the integrated circuit, the at least one standard unit comprising: a hold switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the voltage supply output is switchably coupled to the voltage supply input in response to a hold enable signal such that When the coupling is caused, the voltage supply output corresponds to a holding voltage that is reduced relative to the voltage supply input; wherein the hold switching device has an input from an overdrive voltage supply such that when the hold switching device is enabled At the same time, it is more powerfully turned on with respect to being coupled to the voltage supply input signal and driving from the voltage supply input signal. A computer implementation method for designing an integrated circuit includes the steps of: selecting at least one standard unit from a standard unit database, and incorporating the at least one standard unit in the integrated circuit, the at least one standard unit comprising: a voltage switching device having a voltage supply input (Vin) and a voltage supply output (Vout), and wherein the power supply output is switchably coupled to the voltage supply input in response to a power control input signal such that In a power switching configuration of the voltage switching device, the voltage supply output is coupled to the voltage supply input; wherein the voltage switching device has an additional voltage input from an overdrive voltage supply such that when the voltage switching device is When the power is turned off, the voltage supply output is decoupled from the voltage supply input, and the voltage switching device is coupled to the voltage supply input signal and driven by the voltage supply input signal, and is more effectively turned off. . A method of providing power control in an integrated circuit, the method comprising the steps of: switchably coupling a voltage supply input of a voltage switching device in response to a power control input signal such that the voltage switching device In a power-on configuration, a voltage supply output of the switching device is coupled to the voltage supply input; and a voltage switching output is switched to couple the voltage supply output to the voltage supply input using a hold switching device coupled to the voltage switching device, In response to a hold enable signal, such that in a hold enable configuration of the hold switching device, the voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input; wherein the hold switching device (120, 220) Having an additional voltage input from an overdrive voltage supply (Vod, Vssod) such that in the hold enable configuration, the hold switching device is coupled to the voltage supply input signal and from the voltage supply input signal Drive, more powerfully turned on, and in the power-off configuration of the voltage switching device, the voltage Output lines should be determined by the holding switching means. A method of providing power control in an integrated circuit, the method comprising the steps of: switchingly coupling a voltage supply output of a hold switching device to a voltage supply input of the voltage switching device in response to a hold enable a signal such that when the coupling is caused, the voltage supply output corresponds to a hold voltage that is reduced relative to the voltage supply input; wherein the hold switching device has an input from an overdrive voltage supply to cause When the switching device can be held, it is more powerfully turned on with respect to being coupled to the voltage supply input signal and driving from the voltage supply input signal.