TWI511140B - Devices and methods of non-volatile memory writing - Google Patents

Description

Non-volatile memory writing device and method

The present invention relates to a non-volatile memory writing device and method, and more particularly to a flash memory writing device and method for mitigating write interference with a memory array having separate bit lines.

The flash memory system is a special type of non-volatile memory, and its logic data is stored in the memory unit. Flash memory typically places memory cells in rows and columns, with each row representing the bit line of the data. The flash memory uses a voltage applied to the memory unit to set the threshold voltage, and the threshold voltage level represents the data stored in the memory unit. The operation of flash memory is usually divided into erase and program. The eraser applies a high voltage to the base of the memory cell and applies a negative voltage to the gate in units of blocks or blocks to reduce the electrons stored in the floating gate and lower the threshold voltage of the memory cell. Data "1" stands for; writing is for a byte or a group of words, applying a gate write voltage to the selected memory cell via the word line and applying a source voltage to the selected bit line to The electrons are fed into the floating gate to increase the threshold voltage of the memory cell.

When a write operation is performed on the flash memory, the unselected memory cells are disturbed by the write of the selected memory cells. For the case of write interference, it can generally be divided into the gate of the unselected memory unit due to the write character The high voltage of the line causes a slight write, or the unselected memory unit is slightly written due to the source voltage on the bit line. Especially for flash memory with a separate bit line architecture, since the source of the unselected memory cell is subject to the coupling effect and the induced charge is accumulated, the write interference is particularly affected.

In view of this, the present invention provides a non-volatile memory writing device and a writing method, which can effectively reduce write interference of non-volatile memory.

The non-volatile memory writing device of the present invention comprises: a flash memory, comprising a selection array, the selection array comprising a substrate, a plurality of bit lines and a complex digital element line; and a boosting module generating a row of high voltage, a column of voltages and a negative voltage; a selection module coupled to the word line and the boosting module, the selection module receiving the column high voltage and the negative voltage from the boosting module, And the selecting module selects one of the bit lines as the write bit line according to the address signal and selects one of the word lines as the write word line, wherein the adjacent bit of the write bit line is The input line is coupled to the bit line and the boost module, and the write module receives the line high voltage and the negative voltage from the boost module; When the boosting module is in the boosting process, the writing module applies the negative voltage to the bit line, and when the boosting module finishes generating the row high voltage, the column high voltage and the negative voltage When the above selection module will The high voltage is applied to the write word line, and the write module applies the row high voltage to the write bit line for writing data to the write word line and the write bit The memory unit corresponding to the line.

According to an embodiment of the present invention, wherein the selection module is cut The above negative voltage is also applied to the above bit line before switching to the next word line address.

According to an embodiment of the present invention, wherein the negative voltage is above When one of the substrates has a voltage greater than the junction voltage of the substrate, the writing module floats the substrate.

According to an embodiment of the invention, wherein the writing module is applied The write module applies the negative voltage to the bit line before the row high voltage is written to the bit line.

The method for writing non-volatile memory of the present invention is applicable to one The flash memory, wherein the flash memory has a selected array, the selected array includes a substrate, a plurality of bit lines, and a complex digital line, comprising: providing a row of high voltage, a column of high voltage, and a negative voltage, The negative voltage is applied to the bit line; one of the word lines is selected as a write word line and one of the bit lines is a write bit line, and the column high voltage is applied to the above Writing a word line; applying the row high voltage to the write bit line to write data to the write word line and one of the memory cells corresponding to the write bit line; and stopping generating the line height Voltage, the above column high voltage, and the above negative voltage. According to an embodiment of the invention, adjacent bit lines of the write bit line are floating.

According to an embodiment of the invention, wherein switching to the next character The above negative voltage is also applied to the above bit line before the line address.

According to an embodiment of the present invention, wherein the negative voltage is above When one of the substrates has a voltage greater than the junction voltage of the substrate, the substrate is floated.

According to an embodiment of the invention, the negative voltage is applied to the bit line before applying the row high voltage to the write bit line.

Based on the above, the present invention provides a non-volatile memory writing device and a writing method. In the non-volatile memory writing operation, before the writing of the bit line line is provided with a high voltage, all the status is performed first. The negative line provides a negative voltage, which can effectively reduce the write interference caused by the coupling effect of the local element line of the adjacent write bit line.

The above described objects, features and advantages of the present invention will become more apparent and understood.

100‧‧‧Non-volatile memory writing device

101‧‧‧Flash memory

102‧‧‧Select module

103‧‧‧Write module

104‧‧‧Boost Module

110‧‧‧Select array

111‧‧‧The status line

111A‧‧‧Global Bit Line

112‧‧‧ character line

113‧‧‧Transmission gate

114‧‧‧ column decoder

115‧‧‧ line decoder

201, 301‧‧‧ boost phase

202, 204, 302, 304, 306‧‧‧ write phase

203, 205, 303, 305‧‧‧ Switching addresses

501‧‧‧Inverter

502‧‧‧Anti-gate

503‧‧‧High-voltage level shifting circuit

504‧‧‧P type transistor

505, 507‧‧‧N type transistor

506‧‧‧Negative pressure level shift circuit

Address‧‧‧Select address

Data‧‧‧Write information

L0‧‧‧First logic signal

L1‧‧‧ second logic signal

S41~S48‧‧‧Steps

S _D ‧‧‧Write data signal

S _N ‧‧‧Negative pressure enable signal

S _R ‧‧‧ write enable signal

V _D ‧‧‧ high voltage

V _G ‧‧‧ high voltage

V _N ‧‧‧negative voltage

1 is a block diagram showing a non-volatile memory writing device according to an embodiment of the present invention; and FIG. 2 is a view showing a non-volatile memory writing device according to an embodiment of the present invention. FIG. 3 is an operation waveform diagram of a non-volatile memory writing device according to another embodiment of the present invention; and FIG. 4 is a view showing a non-volatile memory writing device according to an embodiment of the present invention; A flowchart of a method of writing a volatile memory; and a fifth diagram showing a circuit diagram of a write module according to an embodiment of the present invention.

Preferred embodiments in accordance with the present invention are described below. must It is to be understood that the invention is not limited to the scope of the invention.

Figure 1 shows a non-swing according to an embodiment of the present invention. A block diagram of a memory write device. As shown in FIG. 1, the non-volatile memory writing device 100 includes a flash memory 101, a selection module 102, a write module 103, and a boost module 104. The flash memory 101 includes a selection array 110 of one of a plurality of memory arrays, a global bit line 111A, a transfer gate 113, a column decoder 114, and a row decoder 115. The selection array 110 includes a plurality of local bit lines 111 and Many word lines 112. The selection module 102 selects the global bit line 111A via the row decoder 115 according to the selected address Address, and selects one of the plurality of local element lines 111 on the array 110 as the write bit line via the transmission gate 113. The module 102 selects one of the plurality of word lines 112 as a write word line through the column decoder 114.

The boosting module 104 is configured to generate a column high voltage V _G , a row high voltage V _{D ,} and a negative voltage V _N , and provide the row high voltage V _D and the negative voltage V _N to the write module 103 to set the column high voltage V _G and a negative voltage V _{N are} provided to the selection module 102. The write module 103 outputs a write data signal S _D according to the write data Data. When the boost module 104 is in the boosting process, the write module 103 applies a negative voltage V _N to all of the local bit lines 111 via the row decoder 115, the global bit line 111A, and the transfer gate 113, when boosting When the module 104 finishes generating the row high voltage V _D , the write module 103 applies the row high voltage V _D to the write bit line selected by the selection module 102 , and the selection module 102 applies the column high voltage v _G to The word line is written to write data to the write word line and to the memory unit corresponding to the write bit line. According to an embodiment of the invention, the write module 103 also applies a negative voltage V _N to all of the local element lines 111 before the selection module 102 switches to the next word line address.

Since the row decoder 115 is coupled to the transfer gate 113 via the global bit line 110A, wherein only one of the transfer gates 113 is coupled to the corresponding write bit line, so that the adjacent bit element of the write bit line is written. The lines are all in a floating state. When the write module 103 applies the row high voltage V _D to the write bit line, the floating position is caused by the capacitive coupling effect between the local elements. The induced charge is stored to generate a drain voltage. In addition, the induced charge on the floating element's local line will accumulate, and the accumulated induced charge will cause an erroneous write action on the unselected word line.

According to an embodiment of the present invention, when the voltage across the negative voltage V _N to the substrate of the array 110 (not shown in FIG. 1 ) is greater than the junction voltage of the substrate to the bit line, the write module 103 will be the substrate. Floating. According to a preferred embodiment of the present invention, the negative voltage V _N is -1 V. If the junction voltage of the base-to-bit line of the memory cell is greater than 1 V, the write module 103 does not need to float the substrate.

Figure 2 is a diagram showing the operation waveforms of a non-volatile memory writing device according to an embodiment of the present invention. The following description of Fig. 2 will be accompanied by Fig. 1 for detailed explanation. As shown in FIG. 2, in the boosting phase 201, the boosting module 104 first charges the column high voltage V _G and the negative voltage V _N , and selects the module 102 to select all the local element lines while charging, and The write module 103 supplies the negative voltage V _N to all of the local element lines 111 via the global bit line 111A and the transfer gate 113. When entering the writing phase 202, the selection module 102 and the writing module 103 apply the column high voltage V _G and the row high voltage V _D to the first word line and the first bit respectively according to the selection of the selection module 102. Yuan line. However, since the previous second bit line has been charged to the negative voltage V _N , when a voltage change occurs on the adjacent first bit line, the write disturbance caused by the charge coupling effect of the second bit line will be greatly increased. reduce.

When the address stage 203 is switched, the write module 103 stops applying the row high voltage V _D to the first bit line, and in the writing stage 204, the write module 103 sets the row high voltage according to the selection module 102. V _{D is} applied to the second bit line. Since the voltage is gradually discharged to 0V when the first bit line is switched at the address stage 203, when the write module 103 applies the row high voltage V _D to the second bit line, the first bit line is subjected to charge coupling. Interference with effects.

When entering the switch column address stage 205, the write module 103 re-sends the negative voltage to all of the local element lines 111 via the global bit line 111A and the traversing gate 113, at which time the first bit line and the second bit line The line is charged to a negative voltage V _N , and the charge accumulation caused by the charge coupling effect on the first bit line and the second bit line will be removed together.

Figure 3 is a diagram showing the operation waveforms of a non-volatile memory writing device according to another embodiment of the present invention. Figure 3 is substantially the same as Figure 2, except that the write module 103 in Figure 3 does not apply a negative voltage V _N to the bit line, and is only for the same word line, adjacent floating bit lines. The write interference caused by the coupled line is described.

As shown in FIG. 3, at the writing stage 302, the write module 103 applies the row high voltage V _D to the first bit line, and at this time, the second bit line and the third bit line of the floating line The charge is stored due to the capacitive coupling effect between the bit lines, so that the source voltage also applies write interference caused by adjacent memory cells of the high voltage V _G to the same word line. When writing to stage 304, the write module 103 applies the row high voltage V _D to the second bit line, and also adds more coupling charges to the floating first bit line and the third bit line, resulting in Higher source coupling voltage. Since the third bit line has been capacitively coupled to store charge during the write phase 302, it is again affected by capacitive coupling during the write phase 304, such that the voltage on the third bit line is close to the row high voltage V _D , such that The third bit line exhibits a state of being slightly written when writing to stage 304. In addition, since the charge stored on the floating bit line due to the coupling capacitance is not cleared, when entering the writing phase 306, the writing module 103 applies the row high voltage V _D to the third bit line, adjacent And the floating first bit line and the second bit line continue to accumulate induced charges and are continuously subjected to write disturb during subsequent writing.

Therefore, the present invention proposes charging the bit line to a negative voltage. The method helps to solve the interference problem caused by the failure of the architecture to ground the status line, and the charge accumulated on the status line will switch the address of the word line, and then charge the bit line again to Negative voltage is cleared and reset to zero.

Figure 4 is a flow chart showing a non-volatile memory writing method according to an embodiment of the present invention. As shown in Fig. 4, the following description of Fig. 4 will be accompanied by Fig. 1 for detailed explanation. Initially, during boosting, the boost module 104 provides the column high voltage V _G , the row high voltage V _{D ,} and the negative voltage V _N , and applies the negative voltage V _N to the local bit line 111 (step S41). During the writing period, the selection module 102 selects the write word line and the write bit line according to the input address Address, and applies the column high voltage V _G to the write word line (step S42); The module 103 applies the row high voltage V _D to the write bit line relative to the data “0” according to the write data Data to write the data to the write word line and the memory unit corresponding to the write bit line. (Step S43), and it is confirmed whether or not all the materials are written (step S44).

If the result of the step S44 is no, it is confirmed whether the column address is changed (step S45); when the result of the step S45 is YES, the selection module 102 switches to the next write word line and applies a negative voltage to all. The status element line 111 (step S46). Subsequently, the selection module 102 switches to the next write bit line (step S47) and repeats steps S43-S47 until all data writing actions are completed. When the data writing operation is completed, if the result of the determination in step S44 is YES, the generation of the column high voltage V _G , the row high voltage V _{D ,} and the negative voltage V _N is stopped (step S48).

Figure 5 is a circuit diagram showing a write module in accordance with an embodiment of the present invention. The write module 103 includes an inverter 501, an inverse gate 502, a high voltage level shift circuit 503, a P-type transistor 504, an N-type transistor 505, a negative voltage level shift circuit 506, and an N-type transistor 507. . When the write enable signal S _R is a high logic level when the write operation is performed, if the write data Data is data "0" at this time, the first logic signal L0 outputted by the inverse gate 502 is a low logic bit. When the P-type transistor 504 is turned on and the N-type transistor 505 is turned off, the P-type transistor 504 pulls the write data signal S _D to the row high voltage V _D and passes through the row decoder 115 and the transfer gate 113. Provide to the selected write bit line.

Since the source of the P-type transistor 504 is coupled to the row high voltage V _D and is higher than the high logic level of the inverter 501 and the inverse gate 502, when the first logic signal L0 is at a high logic level, the high voltage The level shift circuit 503 converts the high logic level of the first logic signal L0 to the row high voltage V _D to completely disconnect the P-type transistor 504. When the data to be written Data is "1", the first logic signal L0 outputted by the gate 502 is a high logic level, thereby turning on the N-type transistor 505 and disconnecting the P-type transistor 504, and by N. The type semiconductor 505 pulls the write data signal S _D to a low logic level.

Before the write operation, the negative voltage enable signal S _N is at a high logic level to turn on the N-type semiconductor 507, and the N-type transistor 507 pulls the write data signal S _D to the negative voltage V _N and passes through the row decoder 115. And provide all the status lines. When the write operation is performed, the negative voltage enable signal S _N returns to the low logic level, and the negative voltage enable signal S _{N is} converted to the low logic level by the negative voltage level shift circuit 506 to a negative voltage V. _N logic signals L1 and the second N-type transistor 507 open circuit.

The features of many embodiments are described above in the art. Those having ordinary knowledge can clearly understand the form of the present specification. Those having ordinary skill in the art will appreciate that the objectives of the above-described embodiments and/or advantages consistent with the above-described embodiments can be accomplished by designing or modifying other processes and structures based on the present disclosure. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

100‧‧‧Non-volatile memory writing device

101‧‧‧Flash memory

102‧‧‧Select module

103‧‧‧Write module

104‧‧‧Boost Module

110‧‧‧Select array

111‧‧‧The status line

111A‧‧‧Global Bit Line

112‧‧‧ character line

113‧‧‧Transmission gate

114‧‧‧ column decoder

115‧‧‧ line decoder

Address‧‧‧Select address

Data‧‧‧Write information

S _D ‧‧‧Write data signal

V _D ‧‧‧ high voltage

V _G ‧‧‧ high voltage

V _N ‧‧‧negative voltage

Claims (9)

A non-volatile memory writing device comprises: a flash memory, comprising a selection array, wherein the selection array comprises a base, a plurality of bit lines and a complex digital element line; and a boosting module generates a line height a voltage, a high voltage and a negative voltage; a selection module coupled to the word line and the boost module, the selection module receiving the column high voltage and the negative voltage from the boost module, and The selection module selects one of the bit lines as a write bit line according to the address signal and selects one of the word lines as a write word line, wherein the adjacent bit of the write bit line is The line is floating; a write module is coupled to the bit line and the boost module, and the write module receives the line high voltage and the negative voltage from the boost module; The boosting module is configured to apply the negative voltage to the bit line during the boosting process, and when the boosting module completes generating the row high voltage, the column high voltage, and the negative voltage, Select the module to the above column Applying a voltage to the write word line, the write module applying the row high voltage to the write bit line for writing data to the write word line and the write bit line Memory unit. The non-volatile memory writing device of claim 1, wherein the negative voltage is applied to the bit line before the selection module switches to the next word line address. The non-volatile memory writing device of claim 1, wherein the negative voltage to the one of the substrates is greater than the substrate When the surface voltage is applied, the writing module floats the substrate. The memory writing device of claim 1, wherein the writing module applies the negative voltage to the bit line before applying the row high voltage to the writing bit line. . A non-volatile memory writing method is applicable to a flash memory, wherein the flash memory has a selection array, and the selection array comprises a substrate, a plurality of bit lines, and a complex digital line, including: Providing a row of high voltage, a column of high voltage, and a negative voltage, wherein the negative voltage is applied to the bit line; and one of the word lines is selected as a write word line and one of the bit lines is written a bit line, and applying the column high voltage to the write word line; applying the row high voltage to the write bit line to write data to the write word line and the write bit line Corresponding to one of the memory cells; and stopping generating the row high voltage, the column high voltage, and the negative voltage. The non-volatile memory writing method of claim 5, wherein the adjacent bit line of the write bit line is floating. The non-volatile memory writing method of claim 5, wherein the negative voltage is applied to the bit line before switching to the next word line address. The non-volatile memory writing method according to claim 5, wherein the substrate is floated when the negative voltage reaches a junction voltage of the substrate greater than a junction voltage of the substrate. The non-volatile memory writing method as described in claim 5, The negative voltage is applied to the bit line before the row high voltage is applied to the write bit line.