TWI506798B - High voltage resistance semiconductor device and method of manufacturing a high voltage resistance semiconductor device - Google Patents

Description

High voltage resistance semiconductor device and method of manufacturing high voltage resistance semiconductor device

This invention relates to semiconductor technology, and more particularly to semiconductor devices suitable for providing high voltage resistance.

A semiconductor high voltage (HV) diode such as the HV diode 100 shown in FIG. 1 is known, for example, for use in a driver or the like in a semiconductor device. The diode 100 includes a cathode 102 and an anode 104. The general method is to arrange the cathode in parallel with the polysilicon resistor 110 for isolation purposes. Fig. 1B shows an equivalent circuit diagram of the diode 100 and the resistor 110 in Fig. 1A. The high voltage input 112 is typically provided to the cathode 102 of the diode 100 between the cathode 102 and the resistor 110.

As shown in FIG. 1A, the polysilicon resistor 110 typically forms a pattern comprising elongated stripes. The elongated stripes are joined together to form a polycrystalline structure. The polysilicon structure has a length selected according to a desired resistance. As a result, the general resistance 110 shown in FIG. 1A occupies portions 114 of the layout area of the semiconductor device, in addition to the layout area of the diode 100. It is therefore desirable to reduce the layout area 114 occupied by the resistor 110 to reduce the size of the semiconductor layout including the HV diode.

A method related to a semiconductor device and a semiconductor device. According to an aspect of the present disclosure, a semiconductor device may include a semiconductor substrate and a lateral semiconductor diode formed in a surface region of the semiconductor substrate. The diode may have a cathode electrode and an anode electrode. A field insulating structure may be disposed between the cathode electrode and the anode electrode. The polysilicon resistor can be formed on the field insulating structure or between the cathode electrode and the anode electrode. The polysilicon resistor can be electrically connected to the cathode electrode and electrically insulated from the anode electrode.

In some embodiments, a polysilicon resistor can be formed on the upper surface of the field insulating structure to at least partially surround the cathode electrode. The polysilicon resistor can include a plurality of half-ring blocks concentrically arranged between the cathode electrode and the anode electrode. The block may include at least one innermost block electrically connected to the cathode electrode. Adjacent blocks are electrically connected to form a continuous polysilicon resistor structure from the cathode electrode to the outside of the semiconductor diode.

In some embodiments, the anode electrode comprises a ring structure surrounding the cathode electrode.

In some embodiments, the polysilicon resistor comprises a plurality of half-ring blocks arranged in a concentric pattern with the anode electrode surrounding the half-ring block.

In accordance with another aspect of the present disclosure, a method of fabricating a semiconductor device can include providing a semiconductor substrate and forming a lateral semiconductor diode in a surface region of the semiconductor substrate. The formation of the lateral semiconductor diode can include forming a cathode electrode and forming an anode electrode. The method can also include forming a field insulating structure between the cathode electrode and the anode electrode, forming a polysilicon resistor on the field insulating structure, and between the cathode electrode and the anode electrode. The formation of the polysilicon resistor may include forming a polysilicon resistor electrically connected to the cathode electrode and electrically insulating the anode electrode.

In some embodiments, the formation of the polysilicon resistor can include forming a polysilicon resistor on the upper surface of the field insulating structure to at least partially surround the cathode electrode. The formation of the polysilicon resistor may comprise forming a polysilicon resistor to include a plurality of half-ring blocks concentrically arranged between the cathode electrode and the anode electrode. The formation of the polysilicon resistor may include forming a block to include at least one innermost block, the innermost block being electrically connected to the cathode electrode. The formation of the polysilicon resistor may include forming adjacent blocks to be electrically connected to form a continuous polysilicon resistor structure from the cathode electrode to the outside of the semiconductor diode.

In some embodiments, the forming of the anode electrode includes forming a ring structure, such as an anode electrode surrounding the cathode electrode.

In some embodiments, the formation of the polysilicon resistor can include forming a polysilicon resistor to include a plurality of half-ring blocks arranged in a concentric pattern. The anode electrode can surround the half ring block.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

The embodiments of the present application are described in detail with reference to Figs. 2 to 6L.

FIG. 2 shows a plan view of the semiconductor device 200. The semiconductor device 200 includes an HV diode 202 and a polysilicon resistor 204. 3A-3B shows an equivalent circuit diagram of the semiconductor device 200. Fig. 4A is a cross-sectional view showing the semiconductor device 200 taken along the line A-A in Fig. 2. Fig. 4B is a cross-sectional view showing the semiconductor device 200 taken along the line B-B in Fig. 2.

Referring to FIG. 2, the diode 202 is a lateral semiconductor device formed in a surface region of the semiconductor substrate 206 (shown in FIGS. 4A and 4B). The diode 202 includes a central cathode electrode 208. The anode electrode 210 surrounds the cathode electrode 208. The cathode electrode 208 can be an annular disk electrode, and the anode electrode 210 can be a ring electrode that concentrically surrounds the cathode electrode 208. Cathode electrode 208 and anode electrode 210 are separated by a drift region 212 (shown in Figures 4A and 4B) that controls the flow of current between cathode electrode 208 and anode electrode 210 in a manner generally compliant with a diode.

The resistor 204 is disposed on the drift region 212 in the space between the cathode electrode 208 and the anode electrode 210. More specifically, as shown in Figures 4A and 4B, resistor 204 may be formed from a set of polysilicon structures 204a disposed on field oxide (FOX) structure 214, which is disposed on drift region 212. Note that although the figure shows that the resistor 204 is formed directly on the upper surface of the FOX structure 214, other arrangements can be used, for example, one or more additional thin film systems are disposed between the FOX structure 214 and the resistor 204. Resistor 204 is electrically coupled to cathode electrode 208 at contact 216. Resistor 204 is electrically insulated from anode electrode 210, but extends over anode electrode 210 to end 218 to connect other devices.

Resistor 204 can thus be formed on the upper surface of FOX structure 214. Resistor 204 at least partially surrounds cathode electrode 208, and anode electrode 210 also at least partially surrounds resistor 204. This arrangement advantageously allows the device 200 to be provided with a resistor 204 without occupying an additional layout area outside of the diode 202, which is different from the resistor 110 occupying the additional layout area 114 shown in FIG. 1A.

FIG. 3A shows an equivalent circuit diagram of the semiconductor device 200. The diode 202 is connected in parallel with the resistor 204 such that the resistor 204 is provided between the cathode electrode 208 and the outer end 218. Cathode electrode 208 is also electrically coupled to high voltage (HV) terminal 220.

In the layout shown in FIG. 2, the resistor 204 is formed by a pair of polysilicon resistor structures 204a that are connected in parallel between the cathode electrode 208 and the outer end 218. Each polysilicon resistor structure 204a is comprised of a set of concentric annular resistor blocks 204b, each block 204b being depicted as an individual resistor in Figure 3A. In the embodiment shown in FIG. 2, the innermost resistive block 204b can be connected to the cathode electrode 208 and the outermost resistive block 204b can be connected to the outer end 218. The adjacent resistive blocks 204b between the innermost and outermost blocks 204b are joined together to form two sets of parallel electrical resistance between the cathode electrode 208 and the outer end 218.

As shown in FIG. 3B, one or more of the blocks 204b can be further further divided into a set of two or more parallel resistive substructures 204c by changing the layout design, and the resistive substructures 204c are each made up of some resistive subblocks 204d. Composition. Those skilled in the art will appreciate that this change will allow the total resistance of the resistor 204 to be trimmed. It should be noted that the exact number of resistor structures 204a, 204b, sub-structure 204c, and sub-block 204d may vary from the number provided by the illustrated embodiment.

Figure 5 shows a plan view of a portion of the resistor 204. More specifically, Fig. 5 shows a pair of blocks 204b of a pair of resistor structures 204a (shown separately as 204a_1 and 204a_2 in Fig. 5). Figure 5 more clearly illustrates how blocks 204b can be arranged into a set of concentric annular polycrystalline structures. Each structure may have a predetermined width a1 or a2. Depending on the desired total resistance value of resistor 204 and other considerations such as layout constraints, width a1 may be equal to width a2, or width a1 may be different from width a2. The space between concentrically adjacent blocks 204b may be limited by design, for example to avoid shorting during manufacturing. The blocks 204b are connected to each other by a metal contact region 204e.

The dimensions c1 and c2 represent the respective lengths of the metal structures forming the partial contact regions 204e. The dimension d1 represents the distance between the adjacent ends of the resistive block 204b. The dimension e1 represents the distance between the adjacent contact structures 204e of the resistive block 204b. The resistive structures 204a_1 and 204a_2 are equidistant from the cathode electrode 208 and thus form opposing corresponding resistive structures 204a. Preferably, each of the corresponding corresponding resistive structures 204a is symmetrical, and each of the opposing pairs of corresponding resistive structures 204a has the same size.

Referring to FIGS. 4A and 4B, an embodiment of a process (shown in FIGS. 6A-6O) which can be used to fabricate the semiconductor device 200 will be described later.

Fig. 4A is a cross-sectional view showing the semiconductor device 200 taken along the line A-A in Fig. 2. Fig. 4B is a cross-sectional view showing the semiconductor device 200 taken along the line B-B in Fig. 2.

The semiconductor device 200 may be formed on the semiconductor substrate 206. The semiconductor substrate 206 is typically germanium and has a first conductivity type, typically a P conductivity type. The drift channel 212 has a second conductivity type, typically an N conductivity type. The drift channel 212 is formed in a high voltage n-well (HVNW) region 230 of the substrate 206. The drift channel 212 can include an n-type surface region 212a that is separated from the HVNW region 230 by a p-type liner 212b.

The anode region 210 includes a first P-well 232 and a second P-well 234. A first P-well 232 is formed in the substrate 206 and a second P-well 234 is formed in the HVNW region 230. A P+ buried diffusion region 236 is formed in the first P-well 232. An N+ buried diffusion region 238 is formed in the second P-well 234. Additionally, a P+ pickup region 240 is formed in the second P-well 234 adjacent to the N+ buried diffusion region 238. The cathode region 208 includes an N+ buried diffusion region 242 formed in the HVNW region 230.

The multilayer gate structure 244 includes a gate oxide layer 246 and one or more additional gate layers, which may include, for example, a polysilicon layer 247 on the gate oxide layer 246 and a tungsten germanium (WSi) layer 249 in the polysilicon layer. On 247. A portion of the gate structure 244 is referred to as a field plate and extends over the FOX structure 214. The FOX structure 214 is a relatively thick insulating region extending between the cathode 208 and the anode 210. For example, an additional FOX region 214 is also formed between the corners of device 200 and first P well 232 and second P well 234 as an isolation structure.

Figures 4A and 4B also show resistive block 204b formed on the upper surface of FOX structure 214 between cathode 208 and anode 210. The resistive block 204b can be a single or multi-layer polysilicon structure. Resistive block 204 is electrically insulated from each other by an interlayer dielectric (ILD) structure 248 in FIG. 4A. Figure 4B shows the metal structure used as the contact area 204e electrically connected to the adjacent resistive block 204b.

Figure 4A shows anode contact region 250 and cathode contact region 252. The anode contact region 250 is a conductive material, typically a metal, that provides electrical connection to buried diffusion regions 236, 238 and 240, and gate structure 244. Cathode contact region 252 is also a conductive material, typically a metal, that provides electrical connection to buried diffusion region 242.

Figure 4B shows how the cathode contact region 252 also provides an electrical connection between the cathode 208 and the resistor 204 by connecting the buried diffusion region 242 to the innermost resistive block 204b. Figure 4B also shows a resistive contact region 254 that provides an electrical connection between the outermost resistive block 204b and the outer end 218 (shown in Figure 2).

Please refer to FIGS. 6A-6O, which illustrate a process suitable for fabricating the semiconductor device 200 in an embodiment. The diagrams shown in Figs. 6A-6K are the same as the cross-sectional views taken along section line A-A and section line B-B in Fig. 2. Figures 6L and 6M show the metallization process along section line A-A, while the 6N and 6O diagrams show the metallization process along section line B-B.

Starting from the P-type germanium substrate 206 of Figure 6A, for example, the HVNW region 230 is first formed using known lithography and HVNW implantation processes. Then, in FIG. 6B, the first P-well 232 and the second P-well 234 are formed again by a known lithography and ion implantation process. In Figure 6C, an n-type surface region 212a and a p-type liner 212b are formed in accordance with known lithography and ion implantation processes. Then, FIG. 6D shows the results of the lithography, oxidation, and etching processes that can be used to form the FOX region 214.

Then, the gate structure 244 is formed by a process as shown in FIGS. 6E and 6F. Figure 6E shows an oxide layer 246a that will become the gate oxide layer 246. The oxide layer 246a can be formed using a sacrificial oxidation (SAC) process. Then, a polysilicon layer 247 is deposited on the oxide layer 246a using a deposition process, and then a WSi layer 249 is deposited on the polysilicon layer 247. The mask layer 260 is then selectively deposited on the WSi layer 249, and the subsequent etching results are shown in the structure shown in Fig. 6F.

At the 6Gth diagram, the process of forming the resistor 204 is then started. The resistive block 204b can comprise a multilayer structure including, for example, a lower oxide layer and an upper polysilicon layer. To form such a structure, a lower oxide layer 262 can be formed using, for example, a high temperature oxidation (HTO) process typically used to form a PIP capacitor structure, and then a subsequent PIP polysilicon deposition process can be used to deposit a polysilicon layer 264 on the oxide layer 262. As illustrated in FIG. 6G, the conductivity of the polysilicon layer 264 can be modulated by the ion implantation process used to dope the polysilicon layer 264. The final structure is then etched using a lithography process to form a resistive block 204b as shown in Figure 6H. The reticle material 266 is also shown in Figure 6H. The spacers 268 shown in FIG. 6I can also be deposited on the sidewalls of the resistive block 204b and the gate structure 244 using tetra-ethyl-ortho silicate (TEOS) deposition followed by photolithography and etching processes. On the side wall.

Then, FIGS. 6J and 6K show processes for forming buried diffusion regions 236, 238, 240, and 242. Figure 6J shows a mask layer 270 that is selectively formed using lithography. The exposed regions are then diffused using ion implantation to form N+ buried diffusion regions 238 and 242. Similarly, Figure 6K shows a mask layer 272 that is first selectively formed using lithography and then ion implanted to diffuse the exposed regions to form P+ buried diffusion regions 236 and 240.

Figures 6L and 6M show the metallization process along section line A-A, while panels 6N and 6O show the metallization process along section line B-B. The metallization process can include depositing ILD, lithography, and etching to produce the structures shown in Figures 6L and 6N. Metal deposition, lithography, and etching are then performed to produce the structures shown in Figures 6M and 60.

While the invention has been described above in various embodiments, it is not intended to limit the invention. The scope of the present invention is defined by the scope of the appended claims, unless otherwise claimed.

Prior art:

102. . . cathode

104. . . anode

100. . . Dipole

110. . . Polysilicon resistor

112. . . High voltage input

114. . . section

Implementation method:

200. . . Semiconductor device

202. . . Dipole

204. . . Polysilicon resistor

204a. . . Resistance structure

204a_1, 204a_2. . . Resistance structure

204b. . . Block

204c. . . Resistance substructure

204d. . . Resistance sub-block

204e. . . Contact area

206. . . Semiconductor substrate

208. . . Cathode electrode

210. . . Anode electrode

212. . . Drift channel

212a. . . Surface area

212b. . . lining

214. . . Field oxidation structure

216. . . contact

218, 220. . . End

230. . . High pressure n-well area

232. . . First P-well

234. . . Second P-well

236. . . P+ buried diffusion area

238. . . N+ buried diffusion area

240. . . P+ stimulation area

242. . . N+ buried diffusion area

244. . . Gate structure

246. . . Gate oxide layer

246a. . . Oxide layer

247. . . Polycrystalline layer

248. . . Interlayer dielectric structure

249. . . Tungsten carbide layer

250. . . Anode contact area

252. . . Cathodic contact area

254. . . Resistance contact area

260. . . Mask layer

262. . . Oxide layer

264. . . Polycrystalline layer

266. . . Photomask material

268. . . Clearance wall

270, 272. . . Mask layer

A1, a2. . . width

C1, c2, d1, e1. . . size

Figure 1A shows a plan view of a typical HV diode and polysilicon resistor device.

Fig. 1B shows a circuit diagram corresponding to the device shown in Fig. 1A.

Figure 2 shows a plan view of an HV diode and polysilicon resistor device in accordance with the present disclosure.

Figures 3A and 3B show circuit diagrams corresponding to the device shown in Figure 2.

Fig. 4A shows a cross-sectional view taken along section line A-A in Fig. 2.

Fig. 4B shows a cross-sectional view taken along line B-B in Fig. 2.

Fig. 5 is a partial plan view showing the polysilicon resistor of an embodiment.

Figures 6A-6O show the process of a semiconductor device.

200. . . Semiconductor device

202. . . Dipole

204. . . Polysilicon resistor

208. . . Cathode electrode

210. . . Anode electrode

216. . . contact

218. . . End

Claims (12)

A semiconductor device comprising: a semiconductor substrate; a lateral semiconductor diode formed in a surface region of the semiconductor substrate, the diode having a cathode electrode and an anode electrode; and a field insulating structure disposed on the cathode electrode And the anode electrode; and a polysilicon resistor formed on the field insulation structure between the cathode electrode and the anode electrode, the polysilicon resistor is electrically connected to the cathode electrode, and electrically insulated The anode electrode, wherein the polysilicon resistor comprises a plurality of half-ring blocks arranged in a concentric pattern, the anode electrode surrounding the half-ring block. The semiconductor structure of claim 1, wherein the polysilicon resistor is formed on an upper surface of the field insulating structure to at least partially surround the cathode electrode. The semiconductor structure of claim 2, wherein the polysilicon resistor comprises a plurality of half-ring blocks concentrically arranged between the cathode electrode and the anode electrode. The semiconductor structure of claim 3, wherein the blocks comprise at least one innermost block electrically connected to the cathode electrode. The semiconductor structure of claim 4, wherein the adjacent blocks are electrically connected to form a continuous polysilicon resistor structure from an end of the cathode electrode to the outside of the semiconductor diode. The semiconductor structure of claim 1, wherein the anode electrode comprises a ring structure surrounding the cathode electrode. A method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate; forming a lateral semiconductor diode in a surface region of the semiconductor substrate, the lateral semiconductor diode forming comprising forming a cathode electrode and forming an anode An electrode is formed between the cathode electrode and the anode electrode; and a polysilicon resistor is formed on the field insulation structure, and between the cathode electrode and the anode electrode, the formation of the polysilicon resistor comprises forming the polysilicon resistor Electrically connected to the cathode electrode and electrically insulated from the anode electrode; wherein the polysilicon resistor comprises a plurality of half-ring blocks arranged in a concentric pattern, the anode electrode surrounding the half-ring block. The method of fabricating a semiconductor device according to claim 7, wherein the forming of the polysilicon resistor comprises forming the polysilicon resistor on an upper surface of the field insulating structure to at least partially surround the cathode electrode. The method of fabricating a semiconductor device according to claim 8, wherein the forming of the polysilicon resistor comprises forming the polysilicon resistor to include a plurality of half ring blocks, the half ring blocks being concentrically arranged at the cathode electrode and Between the anode electrodes. The method of fabricating a semiconductor device according to claim 9, wherein the forming of the polysilicon resistor comprises forming the plurality of blocks to include at least one innermost block electrically connected to the cathode electrode. The method of fabricating a semiconductor device according to claim 10, wherein the forming of the polysilicon resistor comprises forming adjacent blocks to Electrically connected to form a continuous polysilicon resistor structure from an end of the cathode electrode to the outside of the semiconductor diode. The method of fabricating a semiconductor device according to claim 7, wherein the forming of the anode electrode comprises forming an annular structure, such as the anode electrode surrounding the cathode electrode.